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213 978-1-4799-5296-0/14/$31.00 © 2014 IEEE PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014 Drain Current Modelling in Silicon MOSFETs A. Lakhlef 1 and A. Benfdila 1 * Abstract- The present paper deals with the modeling of silicon MOSFET in the variety of channel range from submicron to nanoMOSFET aiming the study of the degradation and aging of MOSFET transistor used in VLSI Integrated circuits. The proposed model can be used for better understanding of the device reliability in the operating regions of interest. Moreover, it can be seen as a characterization tool for extracting more information on the interface Si-SiO 2 , the channel and the oxide itself. The model is expressed as current versus voltage in the possible full range of gate voltage and meant to comply with the unified current model Index Terms- MOSFET, Current Model, I-V Characteristic; Operating Regimes, Carrier Mobility I. INTRODUCTION The advancement of CMOS technology is based on the deep understanding of the MOSFET used as basic unit in the VLSI-ULSI Circuits [1]. Downsizing of devices resulted in many physical parameters that need be well understood and mastered in order to build reliable devices and hence ICs. This is achieved by a quite adequate characterization tools and modeling [2]. Device modeling is an important issue for the understanding and the investigation on better device performances. For this issue, several techniques are used to study and extract parameters on both virgin and degraded devices aiming determination of the device reliability and lifetime. This is done using characterization and modeling techniques. Various device modeling aspects have been studied these last decades. Compact modeling [3,4] was a sound for many device models. In low dimensional devices modeling should obey other constraints such as short channel effects [5] and quantum behaviors at ultimate dimensions [6]. Ahcene Lakhlef and Arezki Benfdila are within the Microelectronics and Nanotechnology Research Group GRMNT, FGEI, University M. Mammeri, Tizi-Ouzou, Algeriab [email protected] Arezki Benfdila is a Senior Assoc. Abdus Salam ICTP- UNESCO-IAEA Trieste, Italy [email protected] Several device models have been introduced and each taking some assumptions. In our study we have introduced a unified current model in which the impact of mobility is introduced in the gate voltage. Our model is found accurate after simulation of measured data in different device operating regions. Moreover, it can be used to extract device parameters and also to model using bottom up approach. II. THE DRAIN CURRENT MODEL The proposed model is based on the classical model expressed in Eq.1 where some substitutions have been made. th g d ox V V V μ C L W = Id(Vg) . 0 (1) The different parameters have their usual meanings. Accordingly, the channel inversion layer charge in the static regime is given as follows: ox g th Q Vgs C V V , (2) with symbols have their usual meanings, of capacitance, voltage and threshold voltage. In the same aspect, the effective mobility is related to the standard carrier mobility by a correction factor that we have treated and substituted in or model. This mobility is given by: 0 2 1 1( ) 2( ) eff gs th gs th V V V V (3) θ 1 and θ 2 are correction factors. In order to use the model in the subthreshold region, we have introduced a correction for the channel total charge and assumed it by a hyperbolic function in terms of Vgs. This voltage is called effective gate voltage Vgs eff.

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Page 1: [IEEE 2014 IEEE 29th International Conference on Microelectronics (MIEL) - Belgrade, Serbia (2014.5.12-2014.5.14)] 2014 29th International Conference on Microelectronics Proceedings

213978-1-4799-5296-0/14/$31.00 © 2014 IEEE

PROC. 29th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2014), BELGRADE, SERBIA, 12-14 MAY, 2014

Drain Current Modelling in Silicon MOSFETs

A. Lakhlef1 and A. Benfdila1*

Abstract- The present paper deals with the modeling of silicon MOSFET in the variety of channel range from submicron to nanoMOSFET aiming the study of the degradation and aging of MOSFET transistor used in VLSI Integrated circuits. The proposed model can be used for better understanding of the device reliability in the operating regions of interest. Moreover, it can be seen as a characterization tool for extracting more information on the interface Si-SiO2, the channel and the oxide itself. The model is expressed as current versus voltage in the possible full range of gate voltage and meant to comply with the unified current model

Index Terms- MOSFET, Current Model, I-V Characteristic; Operating Regimes, Carrier Mobility

I. INTRODUCTION

The advancement of CMOS technology is based on the deep understanding of the MOSFET used as basic unit in the VLSI-ULSI Circuits [1]. Downsizing of devices resulted in many physical parameters that need be well understood and mastered in order to build reliable devices and hence ICs. This is achieved by a quite adequate characterization tools and modeling [2]. Device modeling is an important issue for the understanding and the investigation on better device performances. For this issue, several techniques are used to study and extract parameters on both virgin and degraded devices aiming determination of the device reliability and lifetime. This is done using characterization and modeling techniques.

Various device modeling aspects have been studied

these last decades. Compact modeling [3,4] was a sound for many device models. In low dimensional devices modeling should obey other constraints such as short channel effects [5] and quantum behaviors at ultimate dimensions [6].

Ahcene Lakhlef and Arezki Benfdila are within the Microelectronics and Nanotechnology Research Group GRMNT, FGEI, University M. Mammeri, Tizi-Ouzou, Algeriab [email protected] Arezki Benfdila is a Senior Assoc. Abdus Salam ICTP-UNESCO-IAEA Trieste, Italy [email protected]

Several device models have been introduced and each taking some assumptions. In our study we have introduced a unified current model in which the impact of mobility is introduced in the gate voltage.

Our model is found accurate after simulation of measured data in different device operating regions. Moreover, it can be used to extract device parameters and also to model using bottom up approach.

II. THE DRAIN CURRENT MODEL

The proposed model is based on the classical model expressed in Eq.1 where some substitutions have been made.

thgdox VVVµCL

W=Id(Vg) .0 (1)

The different parameters have their usual meanings.

Accordingly, the channel inversion layer charge in the static regime is given as follows:

ox g thQ Vgs C V V , (2) with symbols have their usual meanings, of capacitance, voltage and threshold voltage. In the same aspect, the effective mobility is related to the standard carrier mobility by a correction factor that we have treated and substituted in or model. This mobility is given by:

021 1( ) 2( )eff

gs th gs thV V V V

(3)

θ1 and θ2 are correction factors. In order to use the model in the subthreshold region, we have introduced a correction for the channel total charge and assumed it by a hyperbolic function in terms of Vgs. This voltage is called effective gate voltage Vgseff.

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214

When (Vgs-Vth) > (ηθthVth), Vgseff tends towards (Vgs-Vth), and after substituting using Eqs.2 and 3 in the gate voltage expression, the effective gate voltage is found to be:

2

... 2. tththgstththgs

eff

VVVVVVVgs

(4)

Where η is the correction coefficient as introduced in this work and φt is the thermal coefficient. To suite our modeling view, the channel charge is corrected based on the gate capacitance and after substitution using Eq.4, it becomes:

( )eff Canal effQ C Vgs (5)

As it is known the channel capacitance is a function of the gate bias and if one substitutes different terms using Eqs.3,4 and 5 and after mathematical analysis and simplification, the channel capacitance becomes:

tththgs

tththgsthgsoxcanal

VVV

VVVVVCC

.2

2

.2

.. (6)

After mathematical manipulation and transformation using approximations and substitutions in Eq.1, the drain current becomes:

2

.2

2

)(2)(110

...2

..

thgsthgseff

tththgs

tththgsthgsox

VVVVVds

VgsVVV

VVVVVC

LWIds

(7)

As we reported earlier [7], in the saturation region current does saturate and hence shows a more or less linear evolution starting from the hard saturation of the I-V curve. As a summary the model includes the subthreshol part, the linear part, the soft saturation and the modified saturation region as reported in Ref [8]. The model with that given by Ref [9] is then used and investigation on its application on device characterization is achieved. In order to confirm our results, experimental work has been achieved. This experimental work has been done at IMEP Grenoble France. We can notice that as VD gets close to 1V, theoretical and experimental curves meet and the model suites very good. We have shown only the part from below threshold to soft

saturation to emphasize on the validity of the proposed model in the mentioned range.

III. RESULTS AND DISCUSSIONS

A set of I-V measurements has been done at the above mentioned laboratory. After data analysis and treatment some interesting curves have been chosen. A sample of I-V curves obtained on typical devices is shown in Eq. 1.

Figure 1: Typical experimental and theoretical I-V curves obtained on a variety of devices

As it is shown in Fig.2, the effect of VDS on the IDVGS curves is shown for the model that experiences the same behavior in the whole range of drain and gate biases. Due to the lower dimensions, we can see that as VD increases the ID-VGS shows a more pronounced linearity in the channel saturation region.

We can see that as the drain voltage approaches 1V there is a very good agreement between the theoretical and experimental curves for the transconduction and critical points as show in Fig. 4.

The model is simulated and compared to practical data obtained on MOSFET from the IMEP Grenoble France) and found to be in good agreement

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215

Figure 2: Typical experimental ID-VGS curves obtained on a variety of devices for different VD bias

Little discrepancy is observed at the staring of the saturation region which is modeled by other equations and phenomena as given by Equation 8.

In the same aspect we found that the model fits for the ID-VDS behavior as shown in Fig.3

Figure 3: Typical experimental IDS-VDS curve for a fixed VGS obtained on a variety of devices

Figure 4: Typical experimental and theoretical gm-V curves obtained on a variety of devices The mathematical expressions of the current given by Eqs. 7, 8 and 9 are compared to experimental results showed good agreements. One has to notice that in case of low dimensional devices, there is interdependence in phenomena in the current saturation region. Theses phenomena are mainly related to Short channel effects and ultime dimensions side effects. For degraded devices, it gas been found that the total curve experience a shift for both axis and parameters such as leakage current and threshold voltage have been shifted and then the device reliability will be quantified using these values compared to standards.

VI. CONCLUSION The present work is carried out both experimentally and theoretically, the proposed model is found to fit the experimental data in the whole range of gate voltage. To confirm the model, the experimental work has been enlarged to different sets of curves including I-V, gm-V, and mobility. The model is found experience the different variations accordingly. However, there are some discrepancies in the saturation parts of the current; this may be due to phenomena that will be investigated.

Further improvement can be done by introducing other parameters related to the low dimension effects both on channel and oxide in conjunction to the applied field.

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216

Using correspondences of experimental data and curves with the model expressions, several electrical parameters could be easily extracted.

We believe that the model in conjunction with experimental data and other models will help in extracting a large variety of device parameters.

ACKNOWLEDGEMENT We would like to express our gratitude to the IMEP-LAHC Institute in Grenoble France where the experimental measurements presented in this work were done.

REFERENCES

[1]. Wong H., Iwai H, On the scaling issues and Hi k replacement of ultrathin gate dielectric for nanoscale MOS transistor, Microelectronic Engineering. 83, 1867-1904, 2006 [2]. Chen E., Wang A., Chen H., Hsieh W., Yu T.-H., Shen T., Wu J., Diaz C.H., 2012, Proceedings of SISPAD 2012 Denver CO, USA 344-347, 2012.

[3] Gildenblat G., Wang. H., Chen T., Gu X., Cai X;, SP: an advanced surface-potential-based compact MOSFET model, IEEE J.SSC, Vol. 39, No. 9, 1394-1406, 2004. [4] Watts J., MacAndre C., Christian E., Galop-Montoro C., Gildenblat G, Chenming H,, Longeveld R., Mattusch M., NSTI-Nanotech 2005, WCM, 3-12. 2005 [5] Qian X. , Jun X & Yuan T, , Review and Critique of Analytic Models of MOSFET Short-Channel Effects in Subthreshold, IEEE Trans Elect. Dev.59; 1569-1579, 2012 [6] Lihui W, PhD Thesis, Georgia Institute of Technology, Georgia, USA, 2006 [7] Benfdila A., Balestra F., On the drain current saturation in short channel MOSFETs, Microelectronics Journal 37, 635-641, 2006. [8] Loong Peng MT, Ismail R., Modeling of nanoscale MOSFET performance in the velocity saturation region, ELEKTRIKA Journal of Electrical Engineering, 9, 37-41, 2007

[9] Kumar Maiti T., Satya Sopan M., Chakraborty P., Kumar Maiti C., Subir Kumar S., Negative bias temperature instability in strain-engineered p-MOSFETs: a simulation study , J Comput Electron 9; 1-7, 2010