Low Power D-latch design using MCML Tri-state Buffers

Radhika, Neeta Pandey, Kirti Gupta Electronics and Communication Department

Delhi Technological University New Delhi, India

radhikatanwar90@gmail.com, n66pandey@rediffmail.com, kirtigupta_22@yahoo.com

Maneesha Gupta Electronics and Communication Department

NSIT, Delhi University New Delhi, India

maneeshapub@gmail.com

Abstract—This paper presents a low power D-latch designed using two low power tri-state MCML buffers. The proposed D-latch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state. The proposed low power D-latch is simulated in PSPICE using 0.18μm TSMC CMOS technology parameters. The power consumption of the proposed D-latch is compared with the D-latch designed using switched based MCML tri-state buffers which indicate that the proposed low power D-latch is power efficient. The simulation result also proves that the low power D-latch consumes 50% less efficient than the other D-latch.

Keywords—MCML, Tri-state Inverter, D-latch, Low Power

I. INTRODUCTION In recent years, the growing demand for portable electronic

devices require low power building blocks that enable long lasting battery life of the system [1]. This has lead to the development of low power digital circuits. D-latch is the basic circuit used for implementing many fundamental blocks whose performance strongly depends on the D-latch gate performance. D-latch acts as an integral part of various practical applications such as pre-scalars, frequency dividers, and sequential logic circuits [2-4].

MOS current mode logic (MCML) has emerged as a

promising technology due to its various advantages over other logic styles [5]. At high frequency power dissipation in MCML circuits is significantly less as power dissipation in MCML is independent of its operation frequency. MCML style generates low switching noise as current supplied during switching is constant. They offer high performance due to low voltage swing, high noise margin and high switching speed [5-8]. Therefore, MCML style is appropriate for designing high performance digital circuits.

The paper first presents a brief introduction to MCML style in section II. Thereafter, Section III covers the review of MCML tri-state buffers. The D-latch design is presented in section IV and the proposed Low power D-latch design is also discussed. The proposed circuit is implemented, simulated and the results are discussed in section IV. All the simulations are performed

in PSPICE using TSMC 180 nm CMOS technology parameters. Finally, the conclusions are drawn in section V.

II. MCML CIRCUITS A MCML circuit consists of three main components which

includes a pull-down network (PDN), a constant current source, and a load circuit [7]. The basic MCML block is shown in Fig. 1. Its PDN consists of source coupled NMOS transistor pairs. The constant current source generates the bias current Ibias while the load resistance RL determines the output voltage swing [8].

The circuit works on the principle of current steering. MCML is completely differential logic i.e. all signals with their compliments is required [3]. Depending on the logic implemented by PDN, the current is steered through one of the two branches, providing complimentary output signals. When the voltage at input A of one transistor is low, the bias current Ibias is steered to the other transistor. The voltage at the output of the branch with no current reaches high (VOH = OUT = VR), conversely, for the other branch some voltage drops across load resistor and the output voltage in that branch become low (VOL = OUT = -VR ). A basic MCML inverter/buffer circuit is shown in Fig.2.

Fig. 1 Basic MCML Block

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Fig. 2 the MCML Inverter

The load resistor can be modeled by PMOS transistors in triode region [8]. The PMOS load transistors (M1, M2) with grounded gate are always on transistors and are used as the load resistors in the MCML circuit. This offers static power dissipation in the circuit. The biasing current source Ibias can be modeled using NMOS transistor in saturation region. The voltage VB is used to bias the NMOS transistor (M5) to get the required biasing current. The differential input is applied to the NMOS transistor M3-M4 and depending upon the input logic applied complimentary outputs is available.

III. MCML TRI-STATE BUFFERS

A tri-state circuit has an extra terminal where enable is connected. It behaves as a normal gate when enabled and it goes in high impedance state when disabled [9]. In literature, two MCML tri-state inverters have been proposed which are shown in the following section.

A. Switched based MCML tri-state buffer The MCML tri-state buffer that is shown in Fig.3 uses

switch to incorporate enable circuitry. The switch based tri-state buffer (Fig. 2) consists of a MCML buffer (M1---M5) and two PMOS transistors (M6---M7) acting as switches [10]. The PMOS transistors are switched by the enable voltage VE that is applied at their gate terminal to switch the transistors ON and OFF. When VE signal is low, the buffer acts as normal gate. Conversely, when VE signal is high, the buffer enters the high-impedance state. During high impedance state, the transistors (M6-M7) are OFF but at the same time the transistors M1-M2 are ON. This leads to power dissipation in the circuit as all the current sources remain ON even in the high-impedance state.

Fig. 3 Switched based MCML tri-state buffer B. Low Power MCML tri-state buffer

The low-power MCML tri-state buffer is shown in Fig. 4. This circuit makes use of modi ed MCML buffer (M1–M7) [11]. The enable signal is applied to the PMOS transistor that is acting as load resistor which efficiently turns ON/OFF the transistors (M1–M2, M5-M7) in the modi ed MCML buffer. The enable signal VE switches ON the load transistors (M1- M2) of the modi ed buffer and also controls the operation of current source (M5) via transistors M6 and M7. For low VE signal, the transistors M1 and M2 are turned ON and they act as load to the MCML buffer. At the same time, the transistor M7 charges the gate terminal of transistor M5 to the potential VBIAS as the transistor M6 is OFF. Therefore, the transistor M5 acts as a current source and provides the bias current Ibias to the MCML buffer. Thus, for low value of VE signal the circuit behaves as a normal MCML buffer. For high value of signal VE, the transistor M1, M2 and M7 are turned OFF whereas the transistors M6 conducts and pulls the gate terminal of transistor M5 to the ground potential.

Fig. 4 Low Power MCML tri-state buffer

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Thus, the output node is disconnected from the power supply VDD as well as ground leading to high-impedance at the output of the buffer. This circuit offers reduced power consumption as the circuit is deprived of current source in high impedance state. Therefore, the buffer can be utilized for low power circuit design.

IV. D-LATCH DESIGN The D-latch design using tri-state inverters is given in [9].

The D-latch in [9] makes use of one inverter and two tri-state inverters shown in Fig.5 is based on CMOS. The clock signal is used to enable and disable the two inverters (I1 and I3) alternately so that one inverter is in normal mode and the other in high impedance mode or visa-versa. When clock signal is high then the input data is transferred to the output and when it is low the output state is preserved by the loop created by the two back to back inverters.

The proposed D-latch design using MCML based tri-state buffers require two buffers as MCML is differential logic and has both inverted and non-inverted outputs simultaneously. The D-latch design for MCML based buffers is shown in Fig.6. The clock signal is fed to the enable port of the two buffers operating alternately. When the clock signal is high, the buffer B1 is in normal state and the latch is transparent, thus the input is obtained at the output. The buffer B2 enters high impedance state and the loop breaks.

Fig. 5 D-latch design

Fig.6 D-latch design using two tri-state MCML buffers

When the clock signal is low, the buffer B1 is in high impedance mode and thus there is no direct path between input and output. The buffer B2 is activated, thus completing the loop and the last output state is preserved till the next clock transition.

V. SIMULATION RESULTS The low power D-Latch is simulated in PSPICE using

CMOS TSMC 180 nm technology parameters with a voltage swing of 400 mV. The input parameters taken in the simulation of the circuits are shown in Table I.

TABLE I. SIMULATION ENVIRONMENT

Technology 180 nm Temperature 27 ºC

Supply Voltage 1.8V Output Load Capacitor 10 fF

Bias Current 50 μA Input Data Frequency 166 MHz

Clock Frequency 500 MHz The clock and data inputs that are fed to the circuit are

shown in the Fig.7(a) and 7(b). The output waveforms of the proposed low power MCML D-latch is shown in Fig. 7(c). The above waveforms confirm to the functionality.

(a)

(b)

(c)

Fig. 7(a) Input Clock (b) Input Data (c) Output of the proposed D-latch

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The performance of the proposed Low power MCML D-

latch designed using low power MCML tri-state inverters is compared with MCML D-latch designed using switched based MCML tri-state inverters to verify the reduction in power dissipation with the use of the proposed circuit. The power comparison of both circuits is stated in Table II. Also, the delays associated with the Latches for high to low clock transition (H->L) and low to high clock transition (L->H) are also stated in Table III and Table IV.

TABLE II. POWER DISSIPATION (μW) OF LATCHES

Latch Power MCML D_Latch 200

Low Power MCML D-latch

100

.

TABLE III. DELAY (PS) OF MCML D- LATCH

H->L L->H clk -> Q 275.8 271.6 D -> Q 306.8 302.9

TABLE IV. DELAY (PS) OF LOW POWER D-LATCH

H->L L->H clk -> Q 305.1 320.1 D -> Q 201.6 206.7

VI. CONCLUSION In this paper a Low power D-latch which uses two

tri-state MCML buffers is presented. The proposed low power D-latch has been implemented and its performance is compared with D-latch designed using switched based tri-state MCML buffers. It is found that the proposed low power D-latch reduces the power consumption by 50%. It is also observed that the input data to stable output data (D->Q) delay of the low power D-latch is 34.28% and 31.76% less for high to low and low to high clock transition respectively as compared to the D-latch designed using switched based tri-state MCML buffers. An increment in clock edge transition to

stable output data (C->Q) delay by 10.62% and 17.85% for high to low and low to high clock transition respectively is seen in the proposed latch in comparison to the other latch. The Proposed D-latch is suitable for portable devices where power is the major concern. MCML based circuitry makes the latch immune to noise and suitable for mixed signal environment.

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[3] Muhammad Usama, Tad Kwasniewski, “ Design and comparision of CMOS current mode logic latches”, IEEE proceedings in International Symposium on Circuit and System, 2004.

[4] K. Gupta, N. Pandey, M. Gupta, ‘‘MCML D-Latch Using Triple-Tail Cells: Analysis and Design,’’ Hindawi Publishing Corporation, Active and Passive Electronic Components, Volume 2013.

[5] T. K. Agarwal, A. Sawhney, A. K. Kureshi,M. Hasan, Performance Comparison of Static CMOS and MCML gates in sub- threshold region of operation for 32nm CMOS Technology, Proceedings of the International Conference on Computer and Communication Engineering, Malaysia pp. 284-287, 2008.

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[7] M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, H. Yamada, A GHz MOS, Adaptive Pipeline Technique using MOS Current-Mode Logic, IEEE J. Solid-state Circuits, Vol. 31, pp. 784-791, No. 6, June 1996.

[8] M. Alioto and G. Palumbo, Model and Design of Bipolar and MOS Current-Mode logic (CML, ECL and SCL Digital Circuits), Springer, New York,2005.

[9] Sung-Mo Kang, Yusuf Leblebici, “Cmos Digital Integrated Circuits,” Tata McGraw-Hill Education, 2003.

[10] 10. Badel, S., & Leblebici, Y. (2007). Tri-state buffer/bus driver circuits in MOS current-mode logic. In Proceedings of Research in Microelectronics and Electronics Conference (pp. 237–240).

[11] Kirti Gupta, Neeta Pandey , Maneesha Gupta, “Low-power tri-state buffer in MOS current mode logic”, An international journal on Analog Integrated Circuits and Signal Processing, volume-74, number-1, January 2013.

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