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117 New Algorithms in Piecewise Linear Resistive Simulation J. S. Augusto INESC/IST, Aptd. 13069 1000 Lisboa, Portugal +351 13100242 j as a@dalt on. inesc .p t ABSTRACT This paper presents a piecewise linear (PWL) resistive simulator [I]. It uses an efficient algorithm [2] to ob- tain the constraint matrix of a linear multiport from the modified nodal analysis (MNA) equations [3] and a novel algorithm to solve the generalized linear complementari- ty problem (GLCP) [4] that arises from the PWL circuit equations. INT ROD U C TI0 N PWL simulators [5] allow efficient fault simulation in the fault dictionary diagnosis method [6]. The nonlinear de- vices are modeled with linear elements and ideal diodes (simply called diodes, from now on). The PWL circuit can be seen as a linear multiport terminated with diodes whose equations lead to a linear complementarity prob- lem (LCP) or to a GLCP. Several algorithms have been used to solve LCPs arising from electrical networks [5]. In the present simulator the GLCP formulation is solved with a novel method that combines two LCP algorithms. THE SIMULATOR The simulator is described in [l]. The circuit input file is similar to SPICE. The line Pxxx nl n2 describes a port between nodes n l and n2. The devices presently support- ed are semiconductor diodes (normal and Zener), BJTs, MOSFETs and OPAMPs. These devices are expanded to their PWL models and the MNA matrix is filled according to the element rubber stamps [3]. The MNA equations are reduced to obtain the constraint matrix C . Final- ly, the GLCP describing the PWL circuit is solved. The simulation results include the node voltages and the mod- e of operation of the devices. An example is presented in appendix. FORMULATION OF THE CONSTRAINT MATRIX Several methods to obtain an hybrid matrix H of a mul- tiport are known, based on the MNA formalism [7] and based on the topological matrices [8, 91. In most cases, H results from a reduction to the echelon form of the, con- straint matrix C [8]. In this simulator was implemented a method to formulate C based on MNA [2], efficient than other methods [7, 8, 91. The MNA equations of a linear multiport termznated wzth norators have the form [M][e i i,lT = [JEIT, where M C. F. B. Almeida INESC/IST, Aptd. 13069 1000 Lisboa, Portugal $351 13100240 [email protected] is the (n + m) x (n + m +p) MNA matrix, e is the node voltages vector, i is the vector of currents in the (m) in- ternal branches not voltage-controlled, i, is the vector of port currents and J and E are due to the independent sources. Each norator current is a MNA variable, but, as these elements do not add equations, the MNA system of equations is overdetermined. The formulation of C given the former equations, is not possible because the port voltages are not variables. The method proposed here to solve this problem, performs the substitution of p node voltages by the p port voltages (vector .up ) in the MNA system of equations without increasing its dimen- sion. Then, C is formulated from the reduction of (1). [M’I [e’ i w, i,lT = [J ~1~ (1) where e‘ has the node voltages not substituted. The algorzthin The substitution of variables is based on graph theory. In the multiport termmated with norators we define: Definition: A port tree (PT) zs a tree, In the czrcuzt subgraph P whose edges are the port norators. P is a set of trees if and only if there are no loops of ports, which is a necessary condition for the application of the method. Each PT has a number of nodes equal to the number of edges plus one. A level d(.) is attributed to the nodes in the PTs: 1. In each PT is chosen a root node that must be the reference node, if present. 2. All nodes are numbered with a level d(.), indepen- dently in each P T , as follows: (i) d(root) = 0; (ii) d(.) = 1 for all the nodes adjacent to the root; (iii) d( .) = 2 for all the non-numbered nodes adjacent to level 1 nodes . . . etc . . . until all the nodes in the PT have an attributed level. The node voltages in the PTs are substituted by port voltages, except for the roots. Since the reference node is not a variable, it cannot be substituted and, accordingly, must be the root if it is in a PT. The substitution is made in decreasing order of levels, assuring that eliminated n- ode voltages will not be needed anymore. The algorithm to perform the substitution is presented below. In the beginning, all the nodes in the PTs are considered unmarked.

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Page 1: [IEEE IEEE International Symposium on Circuits and Systems - ISCAS '94 - London, UK (30 May-2 June 1994)] Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS

117

New Algorithms in Piecewise Linear Resistive Simulation J. S. Augusto

INESC/IST, Aptd. 13069 1000 Lisboa, Portugal

+351 13100242 j as a@dalt on. inesc .p t

ABSTRACT This paper presents a piecewise linear (PWL) resistive simulator [I]. It uses an efficient algorithm [2] to ob- tain the constraint matrix of a linear multiport from the modified nodal analysis (MNA) equations [3] and a novel algorithm to solve the generalized linear complementari- ty problem (GLCP) [4] that arises from the PWL circuit equations.

INT ROD U C T I 0 N PWL simulators [5] allow efficient fault simulation in the fault dictionary diagnosis method [6]. The nonlinear de- vices are modeled with linear elements and ideal diodes (simply called diodes, from now on). The PWL circuit can be seen as a linear multiport terminated with diodes whose equations lead to a linear complementarity prob- lem (LCP) or to a GLCP. Several algorithms have been used to solve LCPs arising from electrical networks [5]. In the present simulator the GLCP formulation is solved with a novel method that combines two LCP algorithms.

THE SIMULATOR The simulator is described in [l]. The circuit input file is similar to SPICE. The line Pxxx nl n2 describes a port between nodes n l and n2. The devices presently support- ed are semiconductor diodes (normal and Zener), BJTs, MOSFETs and OPAMPs. These devices are expanded to their PWL models and the MNA matrix is filled according to the element rubber stamps [3]. The MNA equations are reduced to obtain the constraint matrix C . Final- ly, the GLCP describing the PWL circuit is solved. The simulation results include the node voltages and the mod- e of operation of the devices. An example is presented in appendix.

FORMULATION OF THE CONSTRAINT MATRIX

Several methods to obtain an hybrid matrix H of a mul- tiport are known, based on the MNA formalism [7] and based on the topological matrices [8, 91. In most cases, H results from a reduction to the echelon form of the, con- straint matrix C [8]. In this simulator was implemented a method to formulate C based on M N A [2] , efficient than other methods [7, 8, 91.

The MNA equations of a linear multiport termznated wzth norators have the form [M][e i i,lT = [JEIT, where M

C. F. B. Almeida INESC/IST, Aptd. 13069

1000 Lisboa, Portugal $351 13100240

[email protected]

is the (n + m) x ( n + m + p ) MNA matrix, e is the node voltages vector, i is the vector of currents in the ( m ) in- ternal branches not voltage-controlled, i, is the vector of port currents and J and E are due to the independent sources. Each norator current is a MNA variable, but, as these elements do not add equations, the MNA system of equations is overdetermined. The formulation of C given the former equations, is not possible because the port voltages are not variables. The method proposed here to solve this problem, performs the substitution of p node voltages by the p port voltages (vector .up ) in the MNA system of equations without increasing its dimen- sion. Then, C is formulated from the reduction of (1).

[M’I [e’ i w, i,lT = [ J ~1~ (1) where e‘ has the node voltages not substituted.

The algorzthin

The substitution of variables is based on graph theory. In the multiport termmated with norators we define:

Definition: A port tree (PT) zs a tree, In the czrcuzt subgraph P whose edges are the port norators. P is a set of trees if and only if there are no loops of ports, which is a necessary condition for the application of the method. Each PT has a number of nodes equal to the number of edges plus one.

A level d( . ) is attributed to the nodes in the PTs:

1. In each PT is chosen a root node that must be the reference node, if present.

2. All nodes are numbered with a level d(.) , indepen- dently in each P T , as follows: (i) d(root) = 0; (ii) d(.) = 1 for all the nodes adjacent to the root; (iii) d( .) = 2 for all the non-numbered nodes adjacent to level 1 nodes . . . etc . . . until all the nodes in the P T have an attributed level.

The node voltages in the PTs are substituted by port voltages, except for the roots. Since the reference node is not a variable, it cannot be substituted and, accordingly, must be the root if it is in a PT. The substitution is made in decreasing order of levels, assuring that eliminated n- ode voltages will not be needed anymore.

The algorithm to perform the substitution is presented below. In the beginning, all the nodes in the PTs are considered unmarked.

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118

G4 S

CPI

Subgraph P

Figure 1: FET amplifier seen as a %port.

FORALL port trees DO REPEAT in each port tree 1. Pick an unmarked node (node x) with the higher

available level in the PT. If it is the root, go to the next PT. If there are no more PTs STOP.

2. Identify the unmarked node y adjacent to x via the edge (port) xy. Note that d ( z ) = d ( y ) + 1.

3. Substitute e, by the port voltage vpxy or vpyz in the MNA equations, as is described below. Mark node a. GOT0 1.

end FORALL. Since d ( a ) > d ( y ) , the port voltage vpxy or vpyx sub- stitutes e, in the MNA equations. M,, and M,, are, respectively, the columns of M corresponding to e, and e y . Two cases are possible:

end REPEAT

Case (i): if v p x y = e, - ey j e, = ey + vpxy

... + M,xe, + ... + M,yey + ... = = ... + M a ~ ~ p x y + ... + (May + Max)ey + ...

The column of e, is added to the column of e y .

... + M,xe, + ... + Maye, + ... = = ... - M 0 ~ v p y , + ... + (May + M,x)ey + ...

The column of e, is added to the column of ey and the sign of the former column is reversed.

If y is the reference node, the addition is not performed.

Example

The small-signal model of a FET differential amplifier [8] in fig. 1 is a 3-port. It is terminated with norators. The right side of the MNA system of equations is null and, so, it is omitted. The left side is:

Case (ii): if wpyx = ey - e, j ez = ey - wpyx

0 0 0 0 1 0 0 r : 0 0 0 0 0 1 0

X

Tree S I

Level0 @ (roots) vpA

Level 1

0 0

Figure 2: Subgraph P and port trees SI and SZ

The subgraph P in fig. 2 has two PTs: S1 has nodes 0, 1 and 2 and ports pl and p2; S2 has port p3 and nodes 4 and 5 . The root in S1 is the reference node and in S2 is, arbitrarily, node 4. The levels are shown in fig. 2.

SI has nodes 1 and 2 with the higher level. Since el - 0 = vpl and e2 - 0 = vp2, the substitutions resume to the change of variables in the columns of nodes 1 and 2, applying case (i) twice. In Sz, node 5 has the higher level and e5 = e4 - vp3. To substitute e5 by vp3, column 5 is added to column 4 and the sign of column 5 is reversed, as stated in case (ii). The left side of the MNA system of equations, after the substitutions, is:

0 0 0 0 1 0 0 r 8 0 0 0 0 0 1 0 1

Substituting numerical values, reordering and reducing, the constraint matrix of the 3-port is obtained:

V P l [ 0 0 0 0 : K :] [z] = [i] (4)

-0.01 0.01 -0.00012 0 0 -2 fP2 ‘LP3

The admittance matrix can be easily extracted from (4). Note that the port currents are opposed to the conven- tional direction (current entering in the + node).

THE SOLUTION OF THE GLCP If the constraint matrix is partitioned (C = [Yp Z,] ) we have:

where s is due to the independent sources and Z , and Yp are submatrices of C . When the multiport is terminated with ideal diodes (fig.3) the variables must verify i, 2 0, up 2 o and vFi, = 0 . The set of equations leads to the following GLCP:

Obtainip 2 o E RP, up 2 o E RP with

[ y p Z , ] [UP iPlT = s ( 5 )

(6) Z i, + Yp up = s vf i, = 0

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119

Z4

U 2

Table 1: Siniulation results

U Circuit 11 p I Wolfe I Lemke

TTL inverter (“I” in input) TTL inverter (“0” in input)

26 Bistable symmetric circuit 5 0

43 94 * *

Multiport

Figure 3: Multiport terminated with ideal diodes. The port voltages and currents respect the nonnegativity and the complementarity .

This GLCP can be solved with an algorithm from Wolfe [4, 101 that is a generalization of the SIMPLEX method for a linear program (LP). The GLCP is transformed in the artificial linear program (7) ) where the artificial vari- ables uj are basic and Ip is the identity matrix:

Min f = E,”=, U3 Subject to : Zpip + Ypvp + Ipu = s (7)

i, 2 0, up 2 0, U 2 0.

The SIMPLEX algorithm is applied to (7) with the re- striction that a variable is made basic only if the com- plementary variable is not basic: if it is, other variable is chosen to enter the basis. This method is the “modi- fied SIMPLEX” or “quadratic SIMPLEX” and if it stops with all the uj nonbasic, the solution of the artificial LP satisfies the complementarity and solves the GLCP.

The class of problems processed by the quadratic sim- plex is restricted. To improve the simulator, Lemke’s pivoting method [4, 111 was implemented. This algorith- m processes a broad class of problems and, accordingly, is widely used. The reduction of the GLCP (6) to an LCP involves the inversion of a p x p complementary submatrix of C (if a given column is in the submatrix, the complementary column is out) which is a slow pro- cess. To avoid this limitation, it was developed a method to “start” Lemke’s method from the last “tableau” of the quadratic SIMPLEX, leading to an efficient algorithm to solve the GLCP.

When the quadratic SIMPLEX terminates without a so- lution, some uj are still in the basis. Lemke’s method can be successively applied to the resulting tableau, reducing the number of basic u j , one by one. To exemplify, con- sider a quadratic SIMPLEX tableau (with p = 4)) where the artificial variables u1 and u2 are basic:

’The LCP formulation is (6) with the equality substituted by yp = q + H x p , where H is an hybrid matrix and yp and x p group the port variables in a complementary way. Each of these vectors has both port voltages and port currents.

In this tableau T the ratios - f & / t j k are calculated for the positions marked with an asterisk, where the columns IC corresponding to pairs of nonbasic complementary vari- ables (23, w3,~4,w4) cross the lines j corresponding to basic artificial variables (211, u2). After finding the vari- able (column) which corresponds to the most negative ratio, its complementary variable is chosen to enter the base, preserving the nonnegativity of q. For example, if the minimum ratio is -y4/t43 in the column of 23, it’s complement, w3, is chosen to enter the basis and start Lemke’s method.

Whenever an uj leaves the basis, it is discarded. The tableau is again searched for the minimum ratio - y j / t j k , and Lemke’s algorithm proceeds. If all the uj leave the basis, the problem is solved. In the example if, after some pivots, u1 swaps with 24 in the basis, the new tableau is:

where there is only one artificial variable (212). The posi- tions with an asterisk are again searched for the most neg- ative value of - q j / n i j k and the process described above continues until u2 leaves the basis.

SIMULATION RESULTS Table 1 shows some simulation results. A detailed ex- ample is shown in the appendix. Only for a TTL chain of 8 inverters the GLCP was solved using Lemke’s pivot- ing method: two artificial variables were basic when the quadratic SIMPLEX ended. In the bistable circuit, two DC solutions c,an be obtained by changing the order of the lines in the input file.

CONCLUSIONS This paper presented new algorithms implemented in a PWL resistive simulator dedicated to fault diagnosis. The algorithm to obtain the constraint matrix is efficient. The resolution of the GLCP is based on the quadratic SIM- PLEX and, if necessary, Lemke’s method. It uses only the constraint matrix, an important advantage since it

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is easier to obtain than an hybrid matrix. SPICE 2G.5 results were compared with actual simulations and the errors were within a 3.5% margin.

* REFERENCES

[l] J . A. S. Augusto, A Resastive Gircuzt Simulator Based on Piecewise Linear Analysis, MSEE Thesis, Lisboa, Instituto Superior TCcnico, July 1993 (in Portuguese).

[a] J . A. S. Augusto, C. F . B. Almeida, “The use of MNA to write the Multiport Hybrid Matrix” , Electronics Letters, 27, 19, pp. 1750-1, 1991.

[3] C. W. Ho, A. E. Ruehli, P. A. Brennan, “The Modified Nodal Approach to Network Analysis” , IEEE Tr. on Circuits and Systems, 22, 6, pp. 504-9, June 1975.

[4] R. Cottle, J-S Pang, R. Stone, The Linear Comple- mentarity Problem, San Diego, Academic Press, 1992.

[5] T.T.J. van Eijndhoven, “Solving the liner complemen- tarity problem in circuit simulation”, SIAM J. of Gon- trol and Optimizalion, 24, 5, pp. 1050-1062, 1986.

[6] P.M. Lin, Y. S. Elcherif, “Analogue Circuits Fault Dictionary - New Approaches and Implementation” , Jour. o f Cir. Th. and Applications, 12, pp. 149-172, April 1985.

[7] I. 0. Hajj, “Formulation of Multiport Equations via Block Matrix Elimination” , Proceedings of the IEEE, 66, 10, pp. 1275-7,1978.

[SI L . 0. Chua, and P. M. Lin, Computer Aided Analy- sis of Electronic Circuits, New Jersey, Prentice-Hall, 1975.

[9] P. M . Lin, “Formulation of Hybrid Matrices for Linear Multiports Containing Controlled Sources” , ZEEE Tr. on Circuit Theory, 21, 3, pp. 169-75, March 1974.

[lo] P. Wolfe, “The Simplex Method for Quadratic Pro- gramming”, Econometrica, 27, 3, July 1959.

[ll] C . E. Lemke, “Bimatrix equilibrium points and mathematical programming”, Management Science, 11, pp. 681-9, 1965.

APPENDIX: SIMULATION OF A CASCODE DIFFERENTIAL AMPLIFIER

A cascode differential amplifier is shown in fig.4a). The input file and the expansion of the nonlinear devices Q1 and Z 1 with the PWL models (shown in fig.4b) and c)). Simulation results are shown below.

* CASCODE DIF. AMPLIFIER

v c c 1 0 16 VEE 2 0 -16 RB 1 3 12000 21 0 3 1E-11 0 . 0 2 6 0.02 2 5 10 v s 1 4 0 0.002 v s 2 6 0 0.002 RC1 1 6 10000 RC2 I ’I 10000 Q3 6 3 8 N IE-11 0.026 0.99 0.8 0.01 4 4 ? 3 9 N 1E-11 0.025 0.99 0.8 0.01 RS1 4 10 1000 RS2 5 11 1000 Q1 8 10 12 N ]Ell 0.026 0.99 0.8 0 .01 4 2 9 11 12 N lEll 0 026 0.99 0.8 0 01 R E 12 2 ‘1600 DI

-- ZENER 21 PZ1 13 0 RZ1 14 3 3.267632 VZ1 1 3 14 0 481683

RC

Q

V cc A

i

+ C l b

Figure 4: a)Differential amplifier CE-CB (“cascode”). b) PWL Ebers-Moll model of a BJT (npn). c) PWL Zener model.

VZZl 16 16 2 S O 0 0 0 0 RI21 0 3 1000000.000000 LEAKAGE RESISTOR -- B J T Q1 P E 4 1 25 10 P C Q l 27 10 R E Q l 26 12 6.635264 RCQl 2 8 8 6.535264 VEQl 25 26 0.464355 V C Q l 2? 98 0.469028 F E Q l 12 10 VCQl 0.800000 FCQl 8 10 V E Q l 0.990000 RAQl 8 12 10000000 000000 * LEAKAGE RESISTOR

__ NODAL VOLTAGES------

EXTERNAL NODE 1 1.600E+01 EXTERNAL NODE 2 -l .sooE+Ol

2.610E+00 EXTERNAL NODE 3 EXTERNAL NODE 4 2.000E-03 EXTERNAL NODE 5 2.000E-03 EXTERNAL NODE 6 S.S13E+OO EXTERNAL NODE 7 6.614E+00 EXTERNAL NODE 8 Z.O40E+OO EXTERNAL NODE 9 2.040E+00 EXTERNAL NODE 10 -7.6?8%03 EXTERNAL NODE 11 -7.677EO3 EXTERNAL NODE 12 -4.784E-01

--NONLINEAR E L E M E N T DIAGNOSIS--

ZENER DIODES 21 ZENER; Z C = 1.019E-03

81 PO LA R TRA NSlSTO R S 9 3 ACTIVE; EPC= 9.5798-04 4 4 ACTIVE; EPC= 9.579E-04 0 1 ACTIVE: EPC= 9.677E-04

PZZl 0 15 R Z Z l 16 3 1 0 OOOUOO

Q 2 ACTIVE, EPC= Y 677EO;