A WIDE BANDWIDTH PC-BASED WAVEFORM ANALYZER USING FPGA

A. El-Sherbini, I. S. Ashour, A. H. Shahein, KH. M Assar, N. Abdel-Hamid, Gh. A. Fahmy

National Telecommunication Institute, iashour@nti.sci. com

Abstract- This paper proposes a novel method to implement a compact size PC-Bused Waveform Analyzer with sampling frequency 30 MHz which can be extended to 200 MS/sec. The main feature of this novel method is the use of FPGA, which enables us to handle high frequency data rates. Moreover high level of integration has been reached Sofmare was developed to display waveforms, signal harmonic components, and data processing.

Index Terms- Autocorrelation Function, Crosscorrelation Function, Harmonics, Virtual Instrumentation, Waveform Analyzer, FPGA.

I. INTRODUCTION

In today’s educational institutes, especially in electrical engineering streams, digital oscilloscopes have become popular for signal acquisition and analysis. Another attractive feature of the digital oscilloscopes over its analog counterpart, the cathode-ray oscilloscopes, is the capability of the digital oscilloscopes for effective storage of the data for subsequent analysis. In recent times, digital storage oscilloscopes (DSOs) have been implemented with the added feature of PC connectivity, such that the signal can be stored in the PC for later analysis. However, with increasing features, these oscilloscopes have become more expensive and less accessible for undergraduate-level novice students. The advanced features of these commercially available oscilloscopes often are underutilized in the low-power and both low-frequency and high frequency. Moreover, the use of PCs in almost every step of any laboratory course, from analysis to data representation to report preparation, motivated the development of a device that will combine to a great extent the features of the digital oscilloscope and the PC [I].

With the continual advances in VLSI technology, applications that were once too difficult for computing hardware to handle are becoming more and more feasible by using Field Programmable Gate Arrays (FPGAs) [2]. FPGA devices feature a gate-array-like architecture, with a matrix of logic cells surrounded by a periphery of U 0 cells, as shown in figure 1 . FPGA can be programmed and verified compare to normal gate arrays. The offered advantages also include higher integration than existing standard solutions and no non- recurring engineering charges or associated risk possible for mask-programmed gate arrays [3].

The appearance of high performance FPGA devices and its rapid development give us a solution and lead the system integration into a new stage. FPGA has the characteristic of short development cycle, low development price and reprogrammability and is very suitable for ASIC and integrated system prototype design [4]. Moreover, the designed circuits can be upgraded after production to add more functionality.

Figure 1 FPGA Architecture

Our system is designed with full knowledge of high-speed digital signal processing and software development. The result is an inexpensive PC-based analyzer with the power of middlehigh end stand-alone digital analyzers. Combined with a PC with Parallel interface, that becomes a powerful diagnostic & engineering tool at a fraction of the cost for an equivalent stand-alone unit.

A case study was presented, using high speed ADC with maximum 32h”z sampling frequency, but we are looking forward to extend our work up too 200MHz (FPGA limiting data rate).

The main contribution of this paper is to present the integrated system with PC-based data acquisition hardware, software, and display modules at higher frequencies in compact size with low cost.

In section (2) both the software and hardware of the proposed system are introduced. Results and specifications of the proposed system are outlined in section (3). Finally, section (4) summarizes the conclusion.

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11. PROPOSED SYSTEM

The proposed system is designed to analyze signals up to 30MHz. The design of this device involves both Hardware and Software. In the sequel these designs are outlined:

(A)- Software The instrumentation industry is moving steadily and

rapidly in the direction of virtual instrumentation. Virtual instruments are centered on a PC, used with as little specialized hardware as possible to link it to devices it must measurekontrol. This hardware typically is plug-in boards for digitizing a signal directly or for controlling stand-alone instruments. Virtual instruments are known for its flexibility, modularity, and low cost [ 13.

Several data acquisition systems through the parallel port have been built in the past [SI-[7] with various combinations of hardware and software. In this paper a novel method to implement a compact size PC-Based Waveform Analyzer with sampling frequency up to 200 MSIsec is proposed.

Fully dedicated software was developed for controlling the data acquisition system. The program is designed to manage and control the hardware as well as storing, processing, and tracing the received data. The flow chart corresponding to the main program is illustrated in Figure 2.

The principle objective of the developed software is automatically control and process the input signals to calculate all signal parameters (frequency domain, time domain, autocorrelation, and crosscorrelation functions). Signal processing is based on DFT analysis. The Graphical User Interface (CUI) windows based program, is an essential element in perhaps the majority of the present day systems [SI. The CUI was developed in VB 6.0. Apart from real-time display of the two different analog signals, the CUI also allows demonstration of common oscilloscope tasks like time- scale and voltage-scale changes. It can display the value at any point of the signal by simply placing the cursor over the required point on the waveform. . Figures 7 & 8 shows a sample GUI window of the developed system. The harmonics of voltage signals are calculated using:

Where: A : calibration factor K : harmonic order N : total number of samples n : number of cycles

B)- Hardware

Wait ii Read Data From I RAM ,+, Processing

1 Plot Data in Time

DomainErequency Domain

I

Figure 2 Flowchart of the developed software

FPGA is the kernel of this system. Most of our digital circuits are implemented at this block. Figure (3) shows system block diagram, each block will be discussed below.

The hardware has been implemented using high speed ADC with sampling frequency 32MHz, and FPGA 200K system gates (system gates are CLB “Configurable Logic Block”, PSM “Programmable Switch Matrix”, IOB “Input (Output Block” and embedded RAM) [9].

Figure 3 System Block Diagram

Analog input is fed to the high speed ADC, digital out is coupled directly to the FPGA, and data is stored at high speed

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(sampling frequency) in the embedded FPGA RAM. The proposed system is fully controlled through PC.

To overcome the problems of using varies input signal frequency ranges the sampling frequency was swept over a wide range from 3 KHz up to 25MHz. Another implementation problem is the slow access time of computer RAM through parallel port. The proposed system was synchronized with two different clocks. First, the system clock which represents the sampling frequency (up to 30MHz in our case study), and write speed over embedded FPGA RAM. Second, read speed from FPGA RAM to PC (parallel port speed rate limitation).

In the sequel we will illustrate both digital and analog parts of the proposed system.

Voltage Step Down

Figure 4 Digital Circuits Implemented on FPCA

HIGH

ADC - Buffer - SPEED *

Figure (4) shows a diagram of the digital circuits implemented on the FPGA, the different control signals and the internal designed blocks are illustrated. where - RST: reset address for counters control signal - WR: Read/Write control signal for embedded RAM on FPGA. - IO: input/output control signal - CLK-RD: read clock from FPGA to PC - DRAM: embedded RAM on the FPGA, (access speed up to 200MHz) [9]. - Address Counters: one for write mode, which is synchronized with system clock, the second for read mode synchronized with PC clock. - Frquency Range : provides the system with variable master clock from 3 KHz up to 25MHz. - Parallel Peripheral Interface: to facilitate the parallel interfacing between the PC and external circuits

freq <= "7m/T/7.':

freq <= pc: w Figure 6

Flowchart Shows the Logic of PPI Block

111. RESULTS

The over all system was tested using various signal waveforms to verify the output results.

To verify our results, a test setup has been prepared, which consists of: a function generator, to provide us with variable frequency waveforms, square wave, sinusoidal wave, triangle wave, the proposed system hardware and finally a PC control unit.

Samples of the waveform analyzer outputs are displayed in figure (7) and figure (8). Synthesis report is shown below:

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Device utilization summary:

Number of Slices: 240 outof 2352 Number of Slice Flip Flops: 256 out of 4704 Number of 4 input LUTs: 396 outof 4704 Number of bonded IOBs: 80 outof 144 Number of TBUFs: 120 outof 2352 Number of BRAMs: 8 out of 14 Number of GCLKs: 2 outof 4

___-________-_______~------

4% 5 6% 5 0%

Figure (7 a and b) shows the output of a triangle signal in run- time and frequency domains respectively. The measured harmonic contents of the triangle wave were compared with mathematically calculated values.

Table (1) shows the electrical specifications of the proposed system. Number of channels can be increased due to the available embedded RAM on the FPGA, 1-Kbyte RAM used for each channel for the proposed system. Analyzing low frequency signals requires larger RAMS capacity; sweeping sampling frequency between different ranges from 3KHz up to 30MHz optimized the usage of the embedded RAM available on FPGA.

I I Figure 7-a

Time Domain Representation of a Triangle Signal (500 KHz)

3 3

2 2

. I 1

91 D

Figure 7-b Frequency Domain Representation of a Triangle Signal (500 KHz)

/ A d

Maximum input voltage used for high speed ADC is 2V, p, extending input analog voltage range has been achieved up to 20V, Higher voltage ranges can be achieved with a trade off between system sensitivity and maximum input voltage magnitudes proposed system sensitivity is 7.8%, at 20V. Designed system power supply provides us with three different voltages, 5V for crystal oscillator and high speed ADC, 3.3V for FPGA IO and output logic level from the high speed ADC, and 2.5V for FPGA core. PC was used for system control and data processing.

Table ( 1 ) Specifications of Proposed System

The prototype of the entire system with associated hardware interface cables, and PC under operation is shown in figure 9.

Figure 9 Prototype System in Operation Figure 8-a

Time Domain Representation of Square Wave Signal (500 KHz)

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IV. CONCLUSION

A low cost compact size Waveform Analyzer was completely designed and implemented. The proposed system was successfully designed , implemented and tested.

As a byproduct of using FPGA we were able to suppress noise effects and eliminate it in the designed range of frequency. We are looking forward to extend our work, such as; memory extension, increasing the input analog signal frequency range.

ACKNOWLEDGMENT This paper has been inspired by many discussions with Prof. Hani F. Ragai and Dr. Ayman Wahba, Ain Shams University.

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