A High Performance Low Voltage Switched-Current Multiplier

G.H.M. Joordens J.A.Hegt D.M.WLeenaerts Dept. of Electrical Engineering

Eindhoven University of Technology PO Box 513, NL 5600 ME5 Eindhoven

The Netherlands

Abstract- This paper presents an accurate switched- current multiplier, designed for 3.3V supply voltage, performing 1.25M multiplications per second with a maximum non-linearity of 0.18%.

I. INTRODUCTION

Current domain techniques and especially switched- current (SI) circuits are receiving more and more attention. Compared with switched-capacitor sampled- data circuits SI circuits have a number of important advantages: they are exclusively composed of MOS transistors, switches and current sources instead of opamps and precise linear floating capacitors, making them suitable for implementation in standard CMOS processes. As capacitors in SI technique are only used for holding voltages, SI circuits have no problems with capacitor mismatch. Furthermore SI circuits are well suited for low-voltage applications.

Central element in this technique is the SI memory cell [l], see Fig. 1, allowing for short-term storage of currents. SI technique is often applied in filters, but its application area is rapidly growing [2] and comprises oscillators, DACs, algorithmic ADCs, Sigma-Delta converters, Cellular Neural Networks, etc. As far as the authors know, this paper is the first proposal for a SI multiplier, being candidate for an essential elementary building block in many systems.

Section I1 deals with the basic concepts of current multipliers. In section I11 a structure for a SI multiplier based on the quarter square principle is analysed. In section IV the actual implementation of a slightly adapted version of this principle is described. Finally some concluding remarks are given in section V.

11. CURRENT D O W N MULTIPLICATION

There is a variety of existing current domain multiplier principles, such as the: 0 translinear multiplier [3] 0

pulse modulation multiplier [5]

0 quarter square principle [7].

current domain multiplier based on a Gilbert cell [41

multiplication based on ADC/DAC conversion [6]

0-7803-2570-2/95 $4.00 01995 IEEE 1856

This latter principle is based on the equation

When both x and y represent currents, two current squarers are required which should be perfectly matched, in order to cancel the quadratic terms completely. Application of a SI memory cell gives the possibility to reduce this to only one current squarer, as depicted in Fig. 2, circumventing the problem of matching. In this approach, fist Z, and Z, are summed in the input circuit, the result is squared in the current squarer and temporarily stored in the memory circuit. In the next phase, I, and Zy are subtracted, the result is squared and subtracted f" the current that was stored in the memory circuit, resulting in an output current IOU, proportional to the product of Z, and Z,. This principle was used as a starting-point for the proposed SI multiplier, which is worked out in more detail in the next section.

( x + y)2 - ( x - y y = 4xy. (1)

III. SWITCHED-CURRENT QUARTEB SQUARE MULTIPLIER

The SI multiplier of Fig. 2 is composed of three sub- circuits:

A. an input circuit, B . a current squarer, and C. a SI memory cell.

These three sub-circuits will be described in the next paragraphs.

A. Znput circuit

The input circuit of Fig. 2 adds currents: I i = I , + I, during one clock phase and subtracts them: I i = Z, - Z, during another clock phase. This can be realised using the SI memory cell given in Fig. 1. In the ideal case, this circuit functions as follows. Clock phases and $2 are non-overlapping. Transistor M , operates in the saturation region. During phase the sum of the input current Zin(@,) and bias current I flow through transistor MI , which is diodeconnected. The parasitic gate capacitance C8s is charged to a voltage V8$ that corresponds with this current I j n ( $ l ) + Z . On phase @2 the input is disconnected and S, is opened,

arge and V8# is held, such that the stays I , (+,)+ I. The resulting

,) is then equal to Iin($, j. ~ o t e that non-ideal effects like clock-feedthrough and channel length modulation have not been taken into account here.

This SI memory cell can be applied in the input circuit, see Fig. 3. In principle this circuit delivers a current I i in clock phases 9, and O3 of Ii ( $, 1 = I, + I y and Ii ($3) = I, - I y respectively. However, it can be shown that due to the memory cell, the current inverter has an approximately constant error e,, such that I (+,) = I , + I y and I ( $ 3 ) = I , - I y +eo . This will result in a multiplier output current according to

(3)

showing a signal independent error of d, but more

important also a signal dependant error of

. For this reason no memory cell was used

in the actual implementation of the input circuit, which will be described in section IV.

41,

e o k - 1,)

210

B. Current squarer

For the current squarer in Fig. 2 several circuits exist, such as [7] and [8]. This latter circuit, see Fig. 4 , was chosen for its simplicity. It has an (idealised) transfer

of I m = I , + A in which Io is a constant current,

which depends on Kirrs. The transfer function of the non-idealised current squarer of Fig. 4 can in first order be approximated as

I2

41,

with errors e, and e, being almost constant. The resulting multiplier output current equals

I o v r = (Ix , so the offset error e, cancels.

However, e, results in a signal dependent error of 10

- at the output of the multiplier. A thorough I ,

analysis of this circuit yields that the body effect of M, and channel length modulation may deteriorate its performance. For that reason this circuit was slightly adapted in the actual implementation, as will be described in section IV.

C. Memory circuit

The third sub-circuit in Fig. 2 is a SI memory cell, for which several solutions exist. The application of the accurate SI memory cell [9] of Fig. 5 will be advantageous. This circuit is based on the principle of Fig. 1, but circuitry has been added to improve its performance. Switching transistor S,, which has the same size as SI, and capacitor C, were added to reduce the clock feedthrough effects, caused by S,. Cascode stage M,,M, was added to reduce the effects due to the channel length modulation of M, . The error at the output of the multiplier caused by this memory cell can in practice be neglected, compared to the errors caused by the non-idealities of the input circuit and the current squarer.

IV. ACTUAL IMPLEMENTATION

Note that some of the constant errors cancel by subtraction, but others don’t. This is due to the quarter square principle of eq. (1). For this reason *a slightly adapted version of this principle was used, based on

( 4 ) This principle has two important advantages. First, the input currents of the current squarer during the clock phases are I, +Iy I , and Ir . As no subtraction is needed anymore, these currents can easily be realised using only a few switches, without the need for a current inverter with its related error e,. Secondly, the constant errors e, and e, of the current squarer now completely cancel. Using eq. (2) as the transfer function of the non-ideal current squarer, the output current of the multiplier will be:

( x + y), - x2 - y2 = 2xy.

- I, +e, +A}+{I~ ( I + e ), +e, +%} =LL ( 5 ) { 410 210

Note that an extra clock phase is required in which no current is provided to the current squarer, so that in the end all errors are subtracted. In total four phases are required and therefore this multiplier is called a four-phase quarter-square SI multiplier. The block diagram of this multiplier is given in Fig. 6. In the fourth clock phase only a signal independent error is subtracted, which may not be essential for some applications, in which case three clock phases suffice.

The total four-phase quarter-square SI multiplier circuit is depicted in Fig. 7. A PMOS version ( M , - M 3 ) of the current squarer of Fig. 4 can be

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recognised. In an n-well CMOS process this gives the REFJ2RENcz.s opportunity to connect the source of M , to the n-well, such that the squarer does not suffer from the body effect anymore. The output of the current squarer is fed to a regulated cascoded current mirror ( M4 - M7). In this way problems caused by the finite output resistance of the current squarer, due to channel length modulation were tackled. Two PMOS versions

C,) of the accurate SI memory cell of Fig. 5 were used. The cascoded current source (M,, - M,, ) was added to ensure a positive current through the second memory cell. Simulations with Spice of this circuit show a non- linearity of 0.18% at a speed of 1.25.106 multiplications/sec. Additional specifications are given in Table 1.

(M8- S,, S,, C1, Cz) and - M14,s7, &, C,,

V. CONCLUSION

In this paper a SI multiplier was proposed, which basically consists of only one current squarer and two accurate SI memory cells. It is based on a slightly altered version of the 'quarter square' principle. In this way the problem of matching of two current squarers is circumvented and furthermore a number of non- idealities of the building blocks are cancelled, resulting in an accurate multiplier in the current domain. The most important contribution to the final error is caused by the non-idealities of the current squarer. Application of other more accurate current squarers, such as [7] is under investigation.

FIGURES T

r - l

Fig. 1: SI basic memory cell.

A B C L-yHTHyp circuit squarer circuit

Fig. 2: block diagram SI multiplier.

[i] J.B. Hughes, I.C. Macbeth, and D.M. Pattullo, "Second generation switched-current signal processing," in Proc. IEEE Int. Symp. Circuits and Systems, pp. 2805-2808, May 1990.

[2] C. Toumazou, J.B. Hughes, and N.C. Battersby, "Switched-currents an analogue technique for digital technology," IEEE Circuits and Systems Series, Vo1.5, London: Peter Peregrinus Ltd, 1993.

[3] E. Seevinck, and R.J. Wiegerink, "Generalized Translinear Circuit Principle," IEEE J . Solid-State Circuits, Vol. 26, pp. 1098-1102, Aug. 1991.

[4] Liang-Yong Song, "A VLSI Design Methodology for Artificial Neural Networks," Univ. of Waterloo, Ontario, 1993.

[ 5 ] D.H. Sheingold, "Nonlinear Circuits Handbook," Analog Devices Inc., Norwood Ma., 1974.

[6] M.S. Piedade, and A. Pinto, "A new multiplier- Qvider circuit based on switched capacitor data converters," in Proc. IEEE Int. Symp. Circuits and Systems, pp. 2224-2227, May 1990.

Translinear Circuits," Ph.D. dissertation, Univ. of Twente, Enschede, The Netherlands, 1992.

[8] K. Bult, and H. Wallinga, "Analog CMOS Computational Circuits," in Proc. ESSCIRC'86, pp. 119-121, Sept. 1986.

[9] H.J. Reitsma, "Development of a 12 bit Digital to Analogue Converter using Switched Current Techniques," master thesis, Eindhoven Univ. of Techn., The Netherlands, Aug. 1993.

[7] R.J. Wiegerink, "Analysis and Synthesis of MOS

I I I

Fig. 3: input circuit using SI memory cell.

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p1"

Fig. 4: current squarer.

T

Fig. 5: accurate SI memory cell.

I currant mirror 1:1 I

Fig. 6: block diagram four-phase quarter-square SI multiplier.

I T

I out +

Fig. 7: four-phase quarter-square SI multiplier circuit.

Table 1: specifications.

Supply voltage: 3.3v Speed: 1.25. lo6 multiplications/sec

Max. output current: 13.2pA Max. output error current: 42nA (incl. offset) 24nA (excl. offset) Max. non-linearity: 0.32% (incl. offset) 0.18% (excl. offset) Technology: CMOS, MIETJX 2 . 4 ~ N-well

Input current range: -6OpA to +60@

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