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IEEE MCSoC-14

Advance Program Version August 26, 2014

University of Aizu, Aizu-Wakamatsu, Japan, September 23-25, 2014

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MCSoC-14 Program at a Glance

Sept. 23 Sept. 24 Sept. 25

8:30

-

9:00

Registration

8:00

-

8:50

Registration 8:30

-

9:00

Registration

8:50

-

9:20

Opening

9:00

-

10:00

Keynote 1 @ UBIC 3D Theater

(Xiang-Yang Li (Illinois Inst. of Tech,

USA)

9:20

-

10:20

Keynote 4 @ Lecture Hall

Hoi-Jun Yoo (KAIST, South Korea)

9:00

-

10:00

Keynote 7 @ UBIC 3D Theater

Jiang Xu (HKUST, Hong Kong

SAR)

10:00

-

10:15

Coffee Break

10:20

-

10:35

Coffee Break

10:00

-

10:15

Coffee Break

10:15

-

12:20

Session

2-1

Session

2-2

10:35

-

12:15

Session

7-1

Session

7-2

Session

7-3

10:15

-

12:20

Session

12-1

Session

12-2

12:20

-

13:20

Lunch

12:15

-

13:15

Lunch

12:20

-

12:30

Closing

13:20

-

14:25

Keynote 2 @ UBIC 3D Theater

Adel Alimi (Univ. of Sfax, Tunisia)

13:15

-

14:15

Keynote 5 @ Lecture Hall

Sedukhin Stanislav (Univ.of Aizu, Japan)

12:30

-

16:35

MCSoC-14 Social Event (Lunch

and Excursion. Fee: Free for

registered participants)

Keynote 3 @ UBIC 3D Theater

Paulo Blikstein (Stanford Univ., USA)

14:25

-

14:35

Coffee Break

14:15

-

14:30

Coffee Break

14:35

-

16:15

Session

4-1

Session

4-2

Session

4-3

14:30

-

15:30

Keynote 6 @ Lecture Hall

Luca Benini (University of Bologna, Italy)

16:15

-

16:30

Coffee Break

15:30

-

15:45

Coffee Break

16:30

-

18:35

Session

5-1

Session

5-2

15:45

-

17:50

Session

10-1

Session

10-2

18:50

-

Welcome Reception

18:30

-

MCSoC-14 Banquet

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Time-Table & Program

Tuesday 23

Start End Duration Session(Room) Details

8:30 9:00 30min Registration

9:00

10:00

60min

Session 1

(UBIC 3D-Theatre)

Keynote 1

“Large Scale Wireless Network Systems: Theory, Experience, and Lessons”

Xiang-Yang Li ( Illinois Institute of Technology, USA)

Chair: Song Guo (The Univ. of Aizu, Japan)

10:00 10:15 15min Coffee Break + Open Networking

10:15

11:30

75min

Session 2-1

(Room: S3 )

Networked Embedded Systems for Internet of Things I

Session Co-Chairs: Song Guo (The University of Aizu, Japan), Peng Li (The University of

Aizu, Japan)

“An Information Classification Approach Based on Knowledge Network”

Huakang Li, Guozi Sun, Bei Xu (Nanjing University of Posts and Telecommunications,

P.R. China), Li Li (Shanghai Jiao Tong University), Jie Huang, Keita Tanno (The

University of Aizu, Japan), Wenxu Wu, Changen Xu (Wenzhou Medical University, P.R.

China)

“A Network-Friendly Disk I/O Optimization Framework in a Virtualized

Cloud System”

Dingding Li, Yong Tang, Bing Liu, Zhendong Yang, Gansen Zhao, Jianguo Li (South

China Normal University, P.R. China)

“Stackelberg Game Theoretic Approach for Probabilistic Network Coding

in Retransmission Mechanism”

Bin Cao, Li Qiao, Yun Li (ChongQing University of Posts and Telecommunications of

China, P.R. China)

4

10:15

11:30

75min

Session 2-2

(Room: S4)

High-Performance Computing in Nuclear Science and

Engineering

Session Co-Chairs: Hui Wang (State Nuclear Power Technology Corporation

(SNPTC), P.R. China), Xin Zhu (The University of Aizu, Japan)

“Phase Distribution Parameter Prediction Using Logistic Model in the

Analysis of Two-Phase Flow”

Ping Lv, Han Wang, Hui Wang (SNPTRD, P.R. China)

“Evaluation of Memory Optimization in a Large-Scale Structural Finite

Element Pre-processor”

Hui Wang, Ping Lv (SNPTRD, P.R. China)

“Numerical Simulation of 3-D Elastic Moduli with Elliptical Cracks Using

FM-DBEM”

Lie Jin, Hongtao Wang, Haitao Wang, XinXin Wu (Tsinghua University, P.R. China)

12:20 13:20 60min Lunch The University of Aizu Restaurant (KEIYAKI)

13:20

14:25

60min

Session 3

(UBIC 3D-Theatre)

Keynotes 2

“Big Data Streams Analytics - Analysis, Application and Challenges ”

Adel Alimi (University of Sfax, Tunisia)

Keynotes 3

"Bringing hands-on learning to the masses: the challenges and

solutions for offering deep learning experiences at scale"

Paulo Blikstein (Stanford University, USA)

Co-Chairs: Mohamed Hamada (The University of Aizu, Japan), Xiang-Yang Li ( Illinois

Institute of Technology, USA)

14:25 14:35 10min Coffee Break + Open Networking

14:35

16:15

100min

Session 4-1

(Room: S3)

Cloud Computing based e-Learning Systems I Session Chair: Mohamed Hamada (The University of Aizu, Japan)

“Symbols and Rules for a Self-Explanatory Machine Model”

Keiko Igarashi, Saki Seino, Rentaro Yoshioka (The University of Aizu, Japan)

“NoobLab: An E-learning Platform for Teaching Programming”

Paul Neve, Gordon Hunter, David Livingstone (Kingston University, United Kingdom)

“Mobile Learning with Google App Engine”

Arreytambe Tabot (AUST University, Nigeria), Mohamed Hamada (The University of

Aizu, Japan)

“Smart Cloud-Based Implementation of a Learning Style Index”

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Mohamed Hamada (The University of Aizu, Japan), Aree Muhammed (Sulaimani

Polytechnic Univrsity, Iraq), Kadir Tufan (Fatih University, Turkey)

14:35

15:25

50min

Session 4-2

(Room: S4)

Networked Embedded Systems for Internet of Things II

Session Co-Chairs: Song Guo (The University of Aizu, Japan), Peng Li (The University of

Aizu, Japan)

“Stochastic Analysis of Epidemic Routing Based Anycast in Throwbox-

Equipped DTNs”

Deze Zeng, Chao Teng, Hong Yao, Qingzhong Liang, Chengyu Hu, Xuesong Yan

(China University of Geosciences, P.R. China)

“Towards Latency-Aware Data Acquisition in Wireless Sensor Network”

Huan Ke, Song Guo, Toshiaki Miyazaki (The University of Aizu, Japan)

14:35

16:15

100min

Session 4-3

(Room: S5 )

Auto-Tuning for Multicore and GPU I

Session Chair: Reiji Suda (The University of Tokyo, Japan)

Invited Speaker: Jakub Kurzak (University of Tennessee, Knoxville, USA)

“BEAST: An Automatic Tuner for Numerical Kernels on Accelerators”

“Auto-tuning of Computation Kernels from an FDM Code with ppOpen-

AT”

Takahiro Katagiri, Satoshi Ohshima, Masaharu Matsumoto (The University of Tokyo,

Japan)

“An Approach to Customization of Compiler Directives for Application-

Specific Code Transformations”

Xiong Xiao, Shoichi Hirasawa, Hiroyuki Takizawa, Hiroaki Kobayashi (Tohoku

University, Japan)

16:15 16:30 15min Coffee Break + Open Networking

16:30

18:35

125min

Session 5-1

(Room: S3)

Cloud Computing based e-Learning Systems II

Session Chair: Mohamed Hamada (The University of Aizu, Japan)

“Are Mobile Devices More Useful than Conventional Means as Tools for

Learning Vocabulary?”

Piyu Lee (Tamkang University, Taiwan)

“Cloud-Based Service for eBooks Using EPUB under the Aspect of Learning

Analytics”

Martin Ebner, Christoph Prettenthaler (Graz University of Technology, Austria),

Mohamed Hamada (The University of Aizu, Japan)

“A Format for Work Specification”

Hidehito Sawai, Rentaro Yoshioka (The University of Aizu, Japan)

“Automatic Glossing Services for E-Learning Cloud Environments”

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Ruth Cortez, Alexander Vazhenin, John Brine (The University of Aizu, Japan)

“An Analysis Tool for a Programming Contest for High-School Students”

Shota Furuya, Katsuki Yanai, Rentaro Yoshioka (The University of Aizu, Japan)

16:30

18:05

95min

Session 5-2

(Room: S4)

Legacy HPC Application Migration I

Session Chair: Hiroyuki Takizawa (Tohoku University, Japan)

"A High-Level Approach for Parallelizing Legacy Applications for Multiple

Target Platforms"

Ritu Arora (Texas Advanced Computing Center, USA)

"An Extension of OpenACC for Pipelined Processing of Large Data on a GPU"

Fumihiko Ino, Akihito Nakano, and Kenichi Hagihara (Osaka University)

"OpenMP Parallelization Method using Compiler Information of Automatic

Optimization"

Kazuhiko Komatsu, Ryusuke Egawa, Hiroyuki Takizawa, and Hiroaki Kobayashi (Tohoku

University)

18:50

Welcome Reception

Venue: The University of Aizu Restaurant (KEYAKI)

Wednesday 24

Start End Duration Session(Room) Details

8:00 8:50 50min Registration

8:50 9:20 30min Opening

(Lecture Theatre)

Welcome & Opening Remarks

9:20

10:20

60 min

Session 6

(Lecture Theatre)

Keynote 4

“Humanistic Intelligence System: Bio-Inspired Multi-core Pattern Recognition

Processor with on-chip Machine Learning”

Hoi-Jun Yoo (Korea Advanced Institute of Science and Technology (KAIST), South Korea)

Chair: Hideharu Amano (Keio University, Japan)

10:20 10:35 15 min Coffee Break + Open Networking

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10:35

12:15

100 min

Session 7-1

(Room: S3)

Embedded Multicore/Many-core Design

Session Chair: Tohru Ishihara (Kyoto University, Japan)

“A Code Partitioning Tool for Simulink Models to Implement on FPGA-Based

Network-on-Chip Architecture”

Satoru Miyasono, Yosuke Moriai, Hiroshi Saito (The University of Aizu, Japan)

“Accelerating Parallel Computations with OpenMP-Driven System-on-Chip

Generation for FPGAs”

Artur Podobas (KTH, Royal Institute of Technology, Sweden)

“Model-Based Platform Composition for Embedded System Design”

Nicolas Hili, Christian Fabre, Ivan Llopard (CEA, LETI, DACLE/LIALP, France), Sophie

Dupuy-Chessa, Dominique Rieu (CNRS, LIG, France)

“A Thermal Management System for Building Block Computing Systems”

Yu Fujita (Keio University, Japan), Kimiyoshi Usami (Shibaura Institute of Technology,

Japan), Hideharu Amano (Keio University, Japan)

10:35

12:15

100min

Session 7-2

(Room:S4 )

Embedded Multicore/Many-core Interconnection Networks

Session Chair: Tsutomu Yoshinaga (The University of Electro-Communications, Japan)

“ Investigating Core-Level N-Modular Redundancy in Multiprocessors”

Aleksandar Simevski (BTU Cottbus-Senftenberg, Germany), Rolf Kraemer (IHP

Microelectronics, Frankfurt/Oder, Germany), Milos Krstic (IHP, Germany)

“SAMNoC: A Novel Optical Network-on-Chip for Energy-Efficient Memory

Access”

Weiwei Fu, Mingmin Yuan, Tianzhou Chen (Zhejiang University, P.R. China), Li Liu

(Zhejiang Sci-Tech University, P.R. China), Minghui Wu (City College Zhejiang University,

P.R. China)

“Low Overhead Monitor Mechanism for Fault-Tolerant Analysis of NoC”

Junxiu Liu, Jim Harkin, Yuhua Li, Liam Maguire (University of Ulster, United Kingdom),

Alejandro Linares Barranco (University of Seville, Spain)

“Adaptive Error- and Traffic-Aware Router Architecture for 3D Network-on-

Chip Systems”

Akram Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah (The

University of Aizu, Japan)

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10:35

12:10

95min

Session 7-3

(Room:S5 )

Legacy HPC Application Migration II

Session Chair: Hiroyuki Takizawa (Tohoku University, Japan)

"Dataflow based Task Execution through PaRSEC for High Performance

Computing Systems"

Anthony Danalis, (Innovative Computing Laboratory at the University of Tennessee,

Knoxville, USA)

"User-defined Source-to-source Code Transformation Tools using Xevolver"

Reiji Suda (The University of Tokyo), Shoichi Hirasawa, and Hiroyuki Takizawa

(Tohoku University)

"Communication Optimization Technique of Algebraic multi-grid solver to Each

Computing System"

Akihiro Fujii, Takuya Nomura, and Teruo Tanaka (Kogakuin University)

12:15 13:15 60min Lunch The University of Aizu Restaurant (KEIYAKI)

13:15

14:15

60min

Session 8

(Lecture Theatre)

Keynote 5

“Algorithms/Architecture Co-design for Exa-scale Computer”

Sedukhin Stanislav, (University of Aizu, Japan)

Chair: Hoi-Jun Yoo (Korea Advanced Institute of Science and Technology (KAIST), South

Korea), Adel Alimi (University of Sfax, Tunisia)

14:15 14:30 15min Coffee Break + Open Networking

14:30

15:30

60min

Session 9

(Lecture Theatre)

Keynote 6

“Near-threshold Parallel Computing in a mW Power Envelope: How and Why?”

Luca Benini, (University of Bologna, Italy)

Chairs: Hiroshi Saito (The University of Aizu, Japan), Jiang Xu (Hong Kong University of

Science and Technology, Hong Kong SAR)

15:30 15:45 15min Coffee Break + Open Networking

15:45

17:50

125min

Session 10-1

(Room: S3)

Embedded Multicore/Many-core Architectures

Session Chair: Naohito Nakasato (University of Aizu, Japan)

“Design and Performance Evaluation of a Manycore Processor for Large

FPGA”

Haruka Mori, Kenji Kise (Tokyo Institute of Technology, Japan)

“KNoCEmu: High Speed FPGA Emulator for Kilo-Node Scale NoCs”

Thiem Van Chu, Shimpei Sato, Kenji Kise (Tokyo Institute of Technology, Japan)

“A Multicore Architecture for High-Performance Scientific Computing using

FPGAs”

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J.P. Cobos Carrascosa, B. Aparicio del Moral, J.L. Ramos, A.C. López Jiménez, J.C

del Toro Iniesta (Instituto de Astrofisica de Andalucia, Spain)

“A Buffered Flow Control Scheme with Flit Weight-Based Dropping Mechanism

for Efficient Communication in NOC”

Ahmed Aldammas, Adel Soudani, Abdullah Al-Dhelaan (King Saud University,

Saudi Arabia)

“Design of a Coarse-Grained Processing Element for Matrix Multiplication on

FPGA”

Yuichi Okuyama (The University of Aizu, Japan), Shigeyuki Takano (ON

Semiconductor, Japan), Tokimasa Shirai (NJK Corporation, Japan)

15:45

17:25

100min

Session 10-2

(Room: S4)

Auto-Tuning for Multicore and GPU II

Session Chair: Daisuke Takahashi, (University of Tsukuba, Japan)

“A GPGPU-Based Acceleration of Fault-Tolerant MLP Learnings”

Tadayoshi Horita (Polytechnic University, Japan), Itsuo Takanami (Retiered), Masakazu

Akiba, Mina Terauchi and Tsuneo Kanno (Polytechnic University, Japan)

“Performance Optimization of SpMV Using CRS Format by Considering

OpenMP Scheduling on CPUs and MIC”

Satoshi Ohshima, Takahiro Katagiri, Masaharu Matsumoto (The University of Tokyo, Japan)

“Application of GPU to Three Computational Models”

Qiangqiang Shi, Yiyang Yang, Xiaolin Li (Stony Brook University, USA)

“A Cache Aware Multithreading Decision Scheme on GPGPUs ”

Ta-Kang Yen, Bo-Yao Yu, Bo-Cheng Charles Lai (National Chiao Tung University, Taiwan)

18:30 MCSoC-14 Banquet

Venue: Washington Hotel

Thursday 25

Start End Duration Session(Room) Details

8:30 9:00 30min Registration

9:00

10:00

60 min

Session 11 (UBIC 3D-Theatre)

Keynote 7

“Inter/Intra-Chip Optical Networks: Opportunities and Challenges”

Jiang Xu (Hong Kong University of Science and Technology, Hong Kong SAR)

Chair: Tomohiro Yoneda (National Institute of Informatics, Japan)

10:00 10:15 15min Coffee Break + Open Networking

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10:15

12:20

125min

Session 12-1

(Room: S3 )

Embedded Multicore/Many-core Applications

Session Co-Chairs: Hiroshi Saito (The University of Aizu, Japan), Artur Podobas (KTH, Royal

Institute of Technology, Sweden)

“An Acceleration for Any-Angle Routing Using Quasi-Newton Method on

GPGPU”

Takahiro Honda, Yukihide Kohira (The University of Aizu, Japan)

“An FPGA-Based Tightly Coupled Accelerator for Data-Intensive Applications”

Masato Yoshimi, Ryu Kudo, Yasin Oge (The University of Electro-Communications, Japan),

Yuta Terada (AVAL DATA, Japan), Hidetsugu Irie, Tsutomu Yoshinaga (The University of

Electro-Communications, Japan)

“Adaptive V-Set Cache for Multi-core Processors”

Ali A. El-Moursy (University of Sharjah, UAE)

“Using the Spring Physical Model to Extend a Cooperative Caching Protocol for

Many-Core Processors”

Safae Dahmani, Loïc Cudennec, Stéphane Louise (CEA, LIST, France), Guy Gogniat

(University of Bretagne Sud, France)

“Time-Based Least Memory Intensive scheduling”

Amr S. Elhelw (Egyptian Financial Supervisory Authority, Egypt), Ali El-Moursy (University

of Sharjah, UAE), Hossam A. H. Fahmy (Cairo University, Egypt)

10:15

12:20

125min

Session 12-2

(Room: S4 )

Embedded Multicore/Many-core Programming

Session Co-Chairs: Adel Alimi (University of Sfax, Tunisia), Stéphane Louise (CEA LIST,

France)

“Introducing A-Cell for Scalable and Portable SIMD Programming”

Hamed Khandan (RIKEN Advanced Institute for Computational Science, Japan)

“A Performance Evaluation of Multi-programming Model on a Multicore

System with Virtual Machines”

Hitoshi Ueno (Uresearch Office, Japan)

“Performance Validation of the Multicore SoC for Spacecraft Applications”

Feiyao Wang, Wenyan Wang (China Academy of Space Technology, P.R. China)

“A Model of Computation for Real-Time Applications on Embedded

Manycores”

Stéphane Louise, Paul Dubrulle, Thierry Goubier (CEA LIST, France)

“Classifying Performance Bottlenecks in Multi-threaded Applications”

Sourav Dutta, Sheheeda Manakkadu, Dimitri Kagaris (Southern Illinois University, USA)

12:20 12:30 10min Closing (Lecture Theatre)

Social Event (Lunch & Excursion)

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12:30 Session 13

Fee: Free for all registered participants.

IEEE MCSoC-14 Invited Speakers

Luca Benini, University of Bologna, Italy

Near-threshold Parallel Computing in a mW Power Envelope: How and Why?

Biography: Luca Benini is Full Professor at the University of Bologna and he is the chair of digital Circuits and systems at

ETHZ. He has served as Chief Architect for the Platform2012/STHORM project in STmicroelectronics, Grenoble in the period

2009-2013. He has held visiting and consulting researcher positions at EPFL, IMEC, Hewlett-Packard Laboratories, Stanford

University. Dr. Benini’s research interests are in energy-efficient system design and Multi-Core SoC design. He is also active in

the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications. In these areas

he has coordinated tens of funded projects, including an on-going ERC Advanced Grant on Multi-scale thermal management of

Computing Systems. He has published more than 700 papers in peer-reviewed international journals and conferences, four books

and several book chapters. He is a Fellow of the IEEE and a member of the Academia Europaea and has served for two terms as a

member of the steering board of the ARTEMISIA European Association on Advanced Research & Technology for Embedded

Intelligence and Systems.

Sedukhin Stanislav, University of Aizu, Japan

Algorithms/Architecture Co-design for Exa-scale Computer

To keep further historically exponential improvement of computer performance we have to overcome at least two fundamental

barriers imposed by speed of light (frequency wall) and, related to it, heat generation (power wall). In this talk, I will refresh the

50 years old and forgotten today idea of increasing the performance of a single-clock massively-parallel computer system

by decreasing its operating frequency. This controversial idea is based on the fact that linear decreasing of frequency leads to the

nonlinear enlargement of the system size, which can be used for increasing the concurrency level in a planar or cubical system.

Moreover, decreasing the operating frequency results in a reduction of power consumption. I also will introduce a revised,

computing-in-place version of the well-known systolic model of massively-parallel computing, where all initial/intermediate data

are immediately available for concurrent computing and cyclical data exchange (reusing). In these array processors, the

concurrency level might be scaled up to the maximum possible (extreme) number, which is equal to the size of computed-in-place

matrix/tensor data. Co-design methodology of such extremely scalable algorithms and array processors will be illustrated on an

example of multidimensional linear transforms, which are frequently the principal limiters that prevent many practical

applications from scaling to the extremely large number of processing elements.

Biography: Stanislav G. Sedukhin received his Ph.D. in Computer Science from the Institute of Mathematics of the Siberian

Branch (SB) of the USSR Academy of Sciences in 1981. In 1992 he received a second academic degree of Doctor of Physical and

Mathematical Sciences (Habilitation) from the USSR (Russian) Academy of Sciences. He worked at the Institute of Mathematics

and then at the Computing Center until 1993. From 1993 he is a Professor at the University of Aizu. From 2010 he served as

Vice-President and Dean of the Graduate School. His interests in High-Performance Computing (HPC), parallel and distributed

numerical computing, co-design of the extremely scalable VLSI-oriented algorithms/processors, clusters of computers and

distributed OS for critical-mission applications. His recent research includes the architectural design of technology scalable

cellular array processors to support scientific, engineering, and multimedia applications. He has published more than 170 articles,

papers, chapters in books, reports and he is coauthor of several books. He is a member of the ACM, the IEEE Computer Society,

and IEICE.

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Hoi-Jun Yoo, Korea Advanced Institute of Science and Technology (KAIST), South Korea

Humanistic Intelligence System: Bio-Inspired Multi-core Pattern Recognition Processor with on-chip Machine Learning

Multi-core processors are useful for the real-time pattern recognition for car navigation, autonomous robot, surveillance camera,

and humanistic interface to consumer products. In this lecture, the benefits and methods of the integration of the neuro-fuzzy logic

or soft-computing with multi-core processor will be explained, especially for high speed low power pattern recognition

application. Analog-digital mixed mode neuro-fuzzy logic circuits are integrated with multi-cores to provide the ‘attention’ of the

cluttered view to speed up the recognition process and improve its accuracy. In addition, learning in the neuro-fuzzy logic enables

to adapt its operation to the input over time. The various multi-core architectures are implemented with the help of high

performance Network on Chip, and the low power schemes such as DVFS and gate control. System demonstrations such as

autonomous robot, car navigation, and HMD (K-Glass) will be introduced.

Biography: Prof. Hoi-Jun Yoo is the full professor of Department of Electrical Engineering at KAIST and the director of

SDIA(System Design Innovation and Application Research Center). From 2003 to 2005, he was the full time Advisor to the

Minister of Korean Ministry of Information and Communication for SoC and Next Generation Computing. His current research

interests are Bio Inspired Intelligence SoC Design, Wearable Computing and Wearable Healthcare. He published more than 200

papers, and wrote 5 books including “Biomedical CMOS ICs”(2011, Springer). Dr. Yoo received the National Medal for his

contribution to Korean Memory Industry in December of 2011, the Korean Scientist of the Month award in Dec. 2010, Best

Research of KAIST Award in 2007, Design Award of 2001 ASP-DAC, and Outstanding Design Awards 2005, 2006, 2007 A-

SSCC. He is an IEEE Fellow, a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC. He was the

TPC Co-Chair of ISWC 2010, IEEE Distinguished Lecturer(’10-’11), and Asia Chair of ISSCC(‘10-‘11) and Vice TPC Chair of

ISSCC 2014. He is TPC Chair of ISSCC 2015 and recognized as the top 4 paper-contributor for 2004-2013 ISSCCs and top 10

paper contributor for 1954-2013 ISSCCs

Jiang Xu, Hong Kong University of Science and Technology, Hong Kong SAR

Inter/Intra-Chip Optical Networks: Opportunities and Challenges

The performance and energy efficiency of a multi-core system is determined by not only its processor cores but also how

efficiently they collaborate with each other. As new applications continuously require more communication bandwidth, metallic

interconnects gradually become the bottlenecks of multi-core systems due to their high power consumption, limited bandwidth,

and signal integrity issues. Optical interconnects are promising candidates to bring low power, high bandwidth, and low latency to

address inter-chip as well as intra-chip communication challenges. Silicon-based photonic devices, such as optical waveguides

and microresonators, have been demonstrated in CMOS-compatible fabrication processes and can be used to build inter/intra-chip

optical networks. This talk will discuss the opportunities and challenges of this emerging technology and present our recent

findings.

Biography: Jiang Xu received his Ph.D. degree from Princeton University. From 2001 to 2002, he worked at Bell Labs, NJ, as a

Research Associate and discovered the First Generation Dilemma in platform-based SoC design methodologies. He was a

Research Associate at NEC Laboratories America, NJ, from 2003 to 2005 and working on Network-on-Chip designs and

implementations. He joined a startup company, Sandbridge Technologies, NY, from 2005 to 2007 and worked on the

development and implementation of two generations of NoC-based ultra-low power Multiprocessor Systems-on-Chip for mobile

platforms. Dr. Xu established Mobile Computing System Lab and Xilinx-HKUST Joint Lab at the Hong Kong University of

Science and Technology. He currently serves as the Area Editor of NoC, SoC, and GPU for ACM Transactions on Embedded

Computing Systems and Associate Editor for IEEE Transactions on Very Large Scale Integration (VLSI) Systems. He served on

the steering committees, organizing committees, and technical program committees of many international conferences, including

ICCAD, CASES, ISVLSI, ICCD, VLSI, EMSOFT, CODES+ISSS, VLSI-SoC, ICESS, RTCSA, NOCS, ASP-DAC, etc. Dr. Xu is

an ACM Distinguished Speaker and a Distinguished Visitor of IEEE Computer Society. He authored or coauthored more than 70

book chapters and papers in peer-reviewed journals and international conferences. He and his students received Best Paper Award

from IEEE Computer Society Annual Symposium on VLSI in 2009, and Best Poster Award from AMD Technical Forum and

Exhibition in 2010. He coauthored a book titled Algorithms, Architecture and System-on-Chip Design for Wireless Applications

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(Cambridge University Press). His research areas include network-on-chip, multiprocessor system-on-chip, embedded system,

computer architecture, low-power VLSI design, and HW/SW codesign.

Adel Alimi, University of Sfax, Tunisia

Big Data Streams Analytics - Analysis, Application and Challenges.

Big data is not just about storage of and access to data. Analytics play a big role in making sense of that data and exploiting its

value. Big Data analytics is considered an imperative aspect to be further improved in order to increase the operating margin of both

public and private enterprises, and represents the next frontier for their innovation, competition, and productivity. Big Data are

typically produced in different sectors of the above organizations, often geographically distributed throughout the world, and are

characterized by a large size and variety. Therefore, there is a strong need for such Big Data streams analytics which is becoming

a significant challenge and requires development of new types of algorithms. Most nowadays algorithms can’t easily scale up to big

data. Plus there are challenges of high-dimensionality, velocity and variety. Thus the aim of this talk is to promote new advances

and research directions in efficient and innovative algorithmic approaches to analyzing big data streams, implementations on

different computing platforms (e.g. neuromorphic, GPUs, clouds, clusters) and applications of Big Data Analytics to solve real-

world problems (e.g. weather prediction, transportation, energy management).

Biography: Adel M. Alimi (S’91, M’96, SM’00). He graduated in Electrical Engineering in 1990. He obtained a PhD and then an

HDR both in Electrical & Computer Engineering in 1995 and 2000 respectively. He is full Professor in Electrical Engineering at

the University of Sfax since 2006. Prof. Alimi is founder and director of the REGIM-Lab. on intelligent Machines. He published

more than 300 papers in international indexed journals and conferences, and 20 chapters in edited scientific books. His research

interests include applications of intelligent methods (neural networks, fuzzy logic, evolutionary algorithms) to pattern recognition,

robotic systems, vision systems, and industrial processes. He focuses his research on intelligent pattern recognition, learning,

analysis and intelligent control of large scale complex systems. He was the advisor of 24 Ph.D. thesis. He is the holder of 15

Tunisian patents. He managed funds for 16 international scientific projects. Prof. Alimi served as associate editor and member of

the editorial board of many international scientific journals (e.g. “IEEE Trans. Fuzzy Systems”, “Pattern Recognition Letters”,

“NeuroComputing”, “Neural Processing Letters”, “International Journal of Image and Graphics”, “Neural Computing and

Applications”, “International Journal of Robotics and Automation”, “International Journal of Systems Science”, etc.). He was

guest editor of several special issues of international journals (e.g. Fuzzy Sets & Systems, Soft Computing, Journal of Decision

Systems, Integrated Computer Aided Engineering, Systems Analysis Modelling and Simulations). He organized many

International Conferences ISI’12, NGNS’11, ROBOCOMP’11&10, LOGISTIQUA’11, ACIDCA-ICMI’05,

SCS’04ACIDCA’2000. Prof. Alimi has been awarded with the IEEE Outstanding Branch Counselor Award for the IEEE ENIS

Student Branch in 2011, with the Tunisian Presidency Award for Scientific Research and Technology in 2010, with the IEEE

Certificate Appreciation for contributions as Chair of the Tunisia Computational Intelligence Society Chapter in 2010 and 2009,

with the IEEE Certificate of Appreciation for contributions as Chair of the Tunisia Aerospace and Electronic Systems Society

Chapter in 2009, with the IEEE Certificate of Appreciation for contributions as Chair of the Tunisia Systems, Man, and

Cybernetics Society Chapter in 2009, with the IEEE Outstanding Award for the establishment project of the Tunisia Section in

2008, with the International Neural Network Society (INNS) Certificate of Recognition for contribution on Neural Networks in

2008, with the Tunisian National Order of Merit, at the title of the Education and Science Sector in 2006, with the IEEE

Certificate of Appreciation and Recognition of contribution towards establishing IEEE Tunisia Section in 2001 and 2000. He is

the Founder and Chair of many IEEE Chapters in Tunisia section. He is IEEE CIS ECTC Education TF Chair (since 2011), IEEE

Sfax Subsection Chair (since 2011), IEEE Systems, Man, and Cybernetics Society Tunisia Chapter Chair (since 2011), IEEE

Computer Society Tunisia Chapter Chair (since 2010), IEEE ENIS Student Branch Counselor (since 2010), He served also as

Expert evaluator for the European Agency for Research. since 2009.

Xiang-Yang Li, Illinois Institute of Technology, USA

Large Scale Wireless Network Systems: Theory, Experience, and Lessons

Wireless sensor networks have been extensively studied from many aspects in the last decade. In this talk, I will share our

experiences and lessons in building real operational large scale wireless sensor networking systems, our recent theoretical results

on the asymptotical behavior of large scale sensor networks, and systems for coexisting ZigBee and WiFi networks. In the first

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part of the presentation, I will discuss the challenges and the lessons we learned from large scale operational sensor system

deployments. In the second part of the presentation, I will summarize our results on the asymptotical network capacity of large

scale wireless sensor networks (mainly the asymptotical multicast capacity in large scale wireless networks under various wireless

interference models using various techniques such as optimal routing and scheduling, VC dimension, Percolation Theory), and the

system implementation of ZIMO for harmonious coexistence of ZigBee and WiFi based on MIMO. Since 2007, collaborated with

several schools, we deployed prototype sensor networks in the Yellow Sea (OceanSense 2007-2009), in Tian-Mu

Mountain (GreenOrbs 2009-2011), and now we are working towards a 4000 sensor system (CitySee 2011-now) for urban sensing

in WuXi City, China. Currently more than 1500 sensor nodes have been deployed in WuXi, which covers several square

kilometers area. These systems provide us a unique opportunity to observe and understand the behavior of large scale sensor

networking systems. Both our theoretical exercises and system investigations are motivated by and then validated in these real

operational systems.

Biography: Dr. Xiang-Yang Li is a professor at Computer Science Department of IIT, and EMC Visiting Chair Professor at

Department of Computer Science and Technology, Tsinghua University (2014-2017). He was an Associate Professor (from 2006

to 2012) and Assistant Professor (from 2000 to 2006) of Computer Science at the Illinois Institute of Technology. He is recipient

of China NSF Outstanding Overseas Young Researcher (B). Dr. Li received MS (2000) and PhD (2001) degree at Department of

Computer Science from University of Illinois at Urbana-Champaign. He received a Bachelor degree at Department of Computer

Science and a Bachelor degree at Department of Business Management from Tsinghua University, P.R. China, both in 1995. He

published a monograph “Wireless Ad Hoc and Sensor Networks: Theory and Applications”. He also co-edited the book

“Encyclopedia of Algorithms”. The research of Dr. Li has been supported by NSF of USA, RGC of HongKong, and NSF of

China. His research interests include cyber physical systems, wireless networks, mobile computing, privacy and security, and

algorithms. Dr. Li is an editor of several journals, including IEEE Transaction on Parallel and Distributed Systems, IEEE

Transaction on Mobile Computing. He served at various capacities (conference chair, TPC chair, or local arrangement chair) in a

number of conferences. He has graduated eleven PhD students since 2004, and co-advised 15 PhD students since 2005.

Paulo Blikstein, Stanford University, USA

Bringing hands-on learning to the masses: the challenges and solutions for offering deep learning experiences at scale

Abstract: to be added.

Biography: Prof. Paulo Blikstein is at Stanford University’s Graduate School of Education and (by courtesy) Computer Science

Department, where he directs the Transformative Learning Technologies Lab (tltl.stanford.edu). Blikstein’s academic research

focus on how new technologies can deeply transform the learning of science, engineering, and mathematics. He creates and

researches cutting-edge educational technologies, such as computer modeling, robotics, and digital fabrication, creating hands-on

learning environments in which students learn science and mathematics by building sophisticated projects and devices. A recipient

of the prestigious National Science Foundation Early Career Award, the most important award for early-career professors in the

US, and two Google Faculty awards, he holds a PhD. from Northwestern University and a MSc. from the MIT Media Lab.