A 1GHz-Bandwidth CMOS Integrator ForCompressive Sensing and RF Applications

Brian DupaixDepartment of Electrical & Computer Engineering

The Ohio State UniversityColumbus, Ohio 43210

Email: dupaix.2@osu.edu

Steven B. BibykDepartment of Electrical & Computer Engineering

The Ohio State UniversityColumbus, Ohio 43210

Email: bibyk.1@osu.edu

Abstract—CMOS hardware development of a resettable 1 GHzintegrator circuit for basis projection or random demodulation inCompressive Sensing is described. To accomplish the projection,a wide bandwidth Integrate Amplify and Dump (IAD) circuitelement is combined with several mixers to provide integrationover the 1GHz bandwidth. The IAD block design in the IBM8RFprocess is summarized and test results for the constructed IADdevice are presented. Finally, a system design for a multi-channelcompressive sensing receiver is proposed.

I. INTRODUCTION

Modern communication systems convert digital signals toan analog form for transmission over a high frequency RFchannel. Key to the ability of these systems to communicatelarge amounts of information in a reliable way are the Shan-non sampling theorem and the analog to digital converter.The Shannon sampling theorem states that any bandlimitedcontinuous-time signal can be reconstructed if sampled at anyrate greater than twice the maximum reconstructed bandwidth.The analog to digital converter (ADC) provided a mechanismfor sampling the signal and performing the reconstructiondigitally. The combination of these two developments en-abled digital processing to efficiently extract informantionfrom continuous-time signals and remove unwanted artifacts.Recently, however, the drive to increase information rates andthe movement of the ADC close to the receiver antenna havecombined to make the bandwidth limitation of Shannon-typesampling difficult to meet with conventional ADCs.

As the information contained in a continuous-time signalrarely occupies an entire signal bandwidth, it was discoveredthat the Shannon sampling bandwith limitation may be relaxedwithout limiting information recovery as long as the signal hasan appropriate level of bandwidth sparsity. This realization hasled to the emerging theory of sampling sparse bandlimitedsignals, known as compressed sensing. Sampling a sparsesignal such as a narrow band tone in a wide bandwidth signal,requires information besides the maximum bandwidth. If thefrequency location of the tone is known, bandpass Nyquistsampling is used to recover the signal. However, if the locationis a random variable, the signal can be modulated with apseudo random square wave followed by an integrate anddump component to project the result onto a compressed basis[1], [2]. The integration is time limited due to the pseudo

random nature of the modulation function. Alternatively, abandwith can be covered by channelizing the waveform, alias-ing the higher frequencies into baseband, low-pass filtering,and sampling the resulting waveform [3]. Both approachesrequire significant digital processing to extract informationfrom the resulting samples.

In [2], the integrate/sampling function is treated as an idealcomponent. Using a real analog component, the integrationbandwidth and linearity of the integrator impose a hard lim-itation on the bandwidth covered by this approach. Also, thetime required to capture samples will add nonlinearities to therandom demodulation signal. The approach in [3] depends onthe orthogonality of brick-wall filters to separate the receivedsignal into sub-bands and precise mixers to frequency shift thesubbands into the conversion bandwidth handled by each A/D.Frequency overlap between filters and non ideal mixing of thereceived signal impair orthogonality and limit this approach.Also, the brick wall requirements for the analog filters in thisapproach are difficult to achieve in hardware.

When implementing these sampling approaches in hard-ware, the ADC rate, filter function type, component bandwidthand speed, and consistency over separate channels are allpotential issues. It is well known that slower rate analog-to-digital conversion yields more robust samples as sampleaccuracy degrades quickly as sampling rate increases [4], [5].Therefore implementing circuitry that provides for low rateconversion improves performance. Also, nonlinearities in thefilter function set the noise floor of the system and must beminimized. The use of high bandwidth circuits reduce thenumber of channels required to cover a given bandwidth, min-imizing the potential for mismatch between them. However,the precision of the output of an analog circuit depends onthe timeperiod they are allowed to settle requiring a tradeoffbetween bandwidth and settling time before sampling. Finallyinconsistency in amplitude, delay, or bandwidth between chan-nels create artifacts that degrades performance and requiresextensive digital post-processing to remove.

In this work, we discuss the implications of implementinga wide-bandwidth high dynamic range analog integrator foruse in Compressive Sensing (CS) systems. This discussion isused to develop an architecture for an integrator to mitigatesampling approach limitations while allowing implementation

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of the architecture in a modern CMOS process. We alsoprovide test results to demonstrate the viability of the IADportion of the architecture. Finally, we propose a system tocomplete coverage of a resettable integration that covers 1GHzof bandwidth.

II. 1GHZ BANDWIDTH INTEGRATOR ARCHITECTURE

An ideal integrator has a 1/s response with a 20dB/decadedrop in magnitude and a continuous 90 degree phase shift.Traditionally, integrators are formed by using the current froman opamp to charge a capacitor. This circuit forms a frequencypole and a 1/s system response.

Recovery of data using CS approaches depend on theRestricted Isometry Property (RIP) [6] described by

(1− δK) ‖u‖2 ≤ ‖Au‖2 ≤ (1 + δK) ‖u‖2 (1)

which is often solved by approximating the sparsest solu-tion using a the Basis Pursuit (BP) [7] convex optimizationalgorithm.

min‖x‖1subject to Ax = y (2)

The solution to this algorithm depends on computation ofthe l1 norm. As the magnitude of the l1 norm is directlyaffected by any distortion of magnitude or phase of the signal,deviations from the ideal integration response when usingintegration to project over bases directly affect the ability ofthe algorithm to extract information. This makes supportingan integration response over 1GHz of bandwidth difficult dueto the magnitude and phase requirements.

Figure 1: Integrator 1/s response, Magnitude and Phase

To implement the ideal and cover 1GHz of bandwidth (9decades), an integrator circuit would have to have dynamicrange equal to 180dB.

Also, any poles in the system generate phase shift. Phaseshift generated by a pole changes over two decades with halfof the phase shift occurring in the decade above the pole andhalf in the decade below. Thus for an ideal integrator to have aconstant 90 degree phase shift from 10Hz to 1GHz, the systemmust have a pole positioned at 0Hz and no additional polesuntil 10GHz.

To achieve this integration response with a traditional op-amp circuit, the op-amp would not only have to support 180dB

of dynamic range, both op-amp poles would have to resideabove 10GHz. This is difficult to accomplish with traditionalopamp circuits. Even if the initial pole is shifted to 10MHzand the dynamic range requirement is reduced to 100dB, therequirement for any additional poles to reside higher than10GHz remains.

(a) Frequency

(b) Time

Figure 2: Spreading Integration in (a) Frequency and (b) Time

A different approach is to spread the integration in time andfrequency. To spread the integration in frequency, the receivedsignal is separated into subbands and each subband is mixedto baseband for integration. Channelizing the response in fre-quency eases both the dynamic range (from the high-frequencyside) and relaxes the second pole position requirements for theintegrator. The result is a more hardware amenable circuit.

To spread the integration in time, each sub-band integra-tion is windowed in time. Spreading the integration in timeprovides several benefits. First, it further reduces the dynamicrange requirement for the integrator (from the low-frequencyside) as the integration results for frequencies below halfthe integration sampling rate can be reconstructed from theintegration samples. Second, it provides time for high preci-sion analog to digital conversion of the integration response.Finally, it allows fast variable amplification based on real-time

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data to maximize the effective resolution of the ADC for highpeak-to-average power signals.

III. CMOS INTEGRATE AMPLIFY DUMP BLOCK

To accomplish signal projection over wide bandwidths,a CMOS Integrate Amplify and Dump (IAD) block wasdeveloped in a 0.13µm process [8]. The IAD block integratesthe incoming baseband RF signal using a GM-C integrator,amplifies the result of integration, and holds the integratedand amplified value to allow A/D conversion to take place.The integration capacitor is then reset to initialize the circuitfor subsequent integration. The IAD uses four timeperiods:integration, amplification, conversion, and dump to providesignal projection onto a basis function (the filtering operation)while allowing a low-speed A/D to capture basis coefficientsor random demodulation outputs. The four timeperiods allowthe operation to be pipelined to provide a continuous time-windowed integrated output. The block was designed to mini-mize the accuracy requirement of the sampling A/D converterby providing adjustable gain while providing high enoughdynamic range to resolve an incoming signal.

In the initial design, a MB-OFDM UWB signal consistingof twenty-five 4MHz tones in 100MHz of bandwidth wasintegrated with 80dB of dynamic range to provide adequatesignal resolution for A/D conversion. This circuit was designedin a process that also facilitated the design of the other RFcomponents of the system including LNAs, mixers, and filters.

Figure 3: IAD Simulated Operation - 10MHz tone

A. IAD Test Platform

The IAD circuit requires digital logic for setup and pro-cessing. To test the device, a test platform was constructedusing a high-speed DAC for signal generation, an FPGA forconfiguration and control, and a high-sample rate ADC fordata processing.

B. Integration Functional Testing

A 10MHz, 20mV peak, 750mV offset sinusoid was appliedto the input of the IAD board and the output of the GM-Cwas monitored producing the waveform in Figure 5.

Figure 4: FPGA Based Test Platform

Figure 5: GMCout Oscilloscope Waveform

With the Charge timeperiod set to 20ns, integration of theinput sinusoid waveform was observed (the negative goingpeak in the oscilloscope image following the y-axis). Notethat the integration timeperiod starts shortly before the y-axis and continues through 3/5 of the first block. There isa significant amount of noise on the signal during the holdand dump timeperiods due to some oscilloscope probe noise.

C. IAD Functional Testing

After testing the result of integration, the pipelined IADoutput was monitored by attaching a 50Ω cable from the IADboard to the oscilloscope. This test provided a clear picture ofthe integrated, amplified, and held result as shown in Figure6.

The waveform in Figure 6 represents the pipelined output ofthe four amplify hold blocks in the implemented IAD circuit.The signal has discrete levels, a sinusoidal appearance, and a90 degree phase shift indicating that a stepwise integration hasoccurred. Note that the waveform in this image has reducedamplitude due to the 50Ω load of the cable.

IV. PROPOSED CHANNELIZED INTEGRATOR

To create an integration response that covers 1GHz ofbandwidth, facilitates sampling, and provides for high preci-sion analog to digital conversion, we propose the channelize

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Figure 6: INTout Oscilloscope Waveform (50Ωload)

architecture pictured in Figure 7. The key component in thisarchitecture is the mixing integrate and amplify block.

Figure 7: Multi-Channel Integrator Architecture

For the mixing function, a current driven passive mixer with25% duty cycle [9] is used to channelize in frequency. Then,integration and time spreading is performed using an IADblock [8]. The output of the IAD is then sampled by N low rateanalog to digital converters. Subsequent digital combinationcompletes the integration and allwos for digital processing toremove undesirable artifacts.

Based on the prior design work in [8] and the subsequentvalidation of the integrator architecture presented in SectionIII, we propose a 5 channel mixing-integrate-amplify systemto cover the 1GHz of integration bandwidth. To keep therequirements achievable in a 0.13µm process, each channelcovers 200MHz of bandwidth, requiring 80dB of integratordynamic range, integration second poles above 2GHz, and 5nsof settling time for the amplification and hold stage.

V. CONCLUSION

The architecture for a wide bandwidth integrator for Com-pressive Sensing and RF applications was explored. The goalof the architecture is to support a 1GHz integration bandwidth,leading to a 180dB dynamic range requirement for the 9

decades of bandwidth. In order to ease the dynamic rangerequirement, the integration is divided into continuous timeintegration periods followed by analog to digital conversion(ADC) and discrete digital integration. The architecture to ac-complish the hybrid continuous/discrete integration performsan Integrate-Amplify-Dump (IAD) sequence of operations.The architecture uses a pipelined IAD and ADC structurefollowed by a digital combiner. The pipeline functions in-corporate the four time periods of integration, amplification,conversion, and dump. A test platform for the integrate-amplify-dump portion of the architecture was developed anddemonstrated successful integration using a 20ns integrationperiod. Observed waveforms from 4 amplify hold blocks inthe IAD circuits demonstrated the correct combined outputto a 10MHz input sinusoid with 20mv peak, 750mV offset.The 750mV offset was used for the 1.5v supply, and 10MHzrepresented a signal in a 200MHz channel.

A proposed architecture integrator to cover 1GHz of band-width with signal projection capability was presented. Int thearchitecture, IAD modules are combined with mixer mod-ules to provide signal projection onto basis functions usedfor compressive sensing or RF bandwidth channelization. Tokeep the integration requirements achievable in a 0.13µmCMOS process, each integration channel covers 200MHz ofbandwidth, requiring 80dB of dynamic range, second polesabove 2GHz, and 5ns of settling time for the amplificationand hold stages. Integration channels are combined in parallelto achieve the final system bandwidth. Total integration isachieved through a combination of an analog continuous timesummation and post ADC conversion digital accumulation. In-tegration artifacts produced by this scheme would be removedin digital post-processing. The architecture naturally enablesthe projection to be accomplished in a hybrid (continuous time/ discrete time) fashion along with the hybrid integration.

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