IHI0048B Gic Architecture Specification

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<p>ARM Generic Interrupt Controller</p> <p>Architecture version 2.0</p> <p>Architecture Specification</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. ARM IHI 0048B (ID061411)</p> <p>ARM Generic Interrupt ControllerCopyright 2008, 2011 ARM Limited. All rights reserved.Release Information The following changes have been made to this document.Change History Date 23 September 2008 13 June 2011 Issue A B Confidentiality Non-Confidential Non-Confidential Change First release for version 1.0 First release for version 2.0</p> <p>Proprietary Notice Words and logos marked with or are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners. The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder. 1. Subject to the provisions of Clauses 2 and 3, ARM hereby grants to you a perpetual, non-exclusive, non-transferable, royalty free, worldwide licence to use and copy the ARM Generic Interrupt Controller (GIC) Architecture Specification (Specification) for the purpose of developing, having developed, manufacturing, having manufactured, offering to sell, selling, supplying or otherwise distributing products which comply with the Specification and which contain at least one processor core which has either been (i) developed by or for ARM or (ii) developed under licence from ARM. THE ARM GIC ARCHITECTURE SPECIFICATION IS PROVIDED AS IS WITH NO WARRANTIES EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE. No licence, express, implied or otherwise, is granted to you, under the provisions of Clause 1, to use the ARM tradename in connection with the ARM GIC Architecture Specification or any products based thereon. Nothing in Clause 1 shall be construed as authority for you to make any representations on behalf of ARM in respect of the ARM GIC Architecture Specification.</p> <p>2.</p> <p>3.</p> <p>Where the term ARM is used it means ARM or any of its subsidiaries as appropriate. Copyright 2008, 2011 ARM Limited 110 Fulbourn Road Cambridge, England CB1 9NJ Restricted Rights Legend: Use, duplication or disclosure by the United States Government is subject to the restrictions set forth in DFARS 252.227-7013 (c)(1)(ii) and FAR 52.227-19. This document is Non-Confidential. The right to use, copy and disclose this document is subject to the licence set out above. Unrestricted Access is an ARM internal classification.</p> <p>ii</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. Non-Confidential</p> <p>ARM IHI 0048B ID061411</p> <p>Contents ARM Generic Interrupt Controller Architecture Specification</p> <p>PrefaceAbout this specification ............................................................................................... vi Using this specification .............................................................................................. vii Conventions .............................................................................................................. viii Additional reading ....................................................................................................... ix Feedback ..................................................................................................................... x</p> <p>Chapter 1</p> <p>Introduction1.1 1.2 1.3 1.4 About the Generic Interrupt Controller architecture ............................................... Security Extensions support .................................................................................. Virtualization support ............................................................................................. Terminology ........................................................................................................... 1-12 1-14 1-15 1-16</p> <p>Chapter 2</p> <p>GIC Partitioning2.1 2.2 2.3 About GIC partitioning ............................................................................................ 2-20 The Distributor ....................................................................................................... 2-22 CPU interfaces ....................................................................................................... 2-24</p> <p>Chapter 3</p> <p>Interrupt Handling and Prioritization3.1 3.2 3.3 3.4 3.5 3.6 3.7 About interrupt handling and prioritization ............................................................. General handling of interrupts ................................................................................ Interrupt prioritization ............................................................................................. The effect of interrupt grouping on interrupt handling ............................................ Interrupt grouping and interrupt prioritization ......................................................... Additional features of the GIC Security Extensions ............................................... Pseudocode details of interrupt handling and prioritization ................................... 3-32 3-35 3-42 3-46 3-51 3-57 3-59</p> <p>ARM IHI 0048B ID061411</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. Non-Confidential</p> <p>iii</p> <p>Contents</p> <p>3.8 3.9</p> <p>The effect of the Virtualization Extensions on interrupt handling ........................... 3-65 Example GIC usage models ................................................................................... 3-66</p> <p>Chapter 4</p> <p>Programmers Model4.1 4.2 4.3 4.4 4.5 About the programmers model .............................................................................. 4-72 Effect of the GIC Security Extensions on the programmers model ....................... 4-78 Distributor register descriptions .............................................................................. 4-82 CPU interface register descriptions ...................................................................... 4-122 Preserving and restoring GIC state ...................................................................... 4-153</p> <p>Chapter 5</p> <p>GIC Support for Virtualization5.1 5.2 5.3 5.4 5.5 About implementing a GIC in a system with processor virtualization ................... 5-156 Managing the GIC virtual CPU interface .............................................................. 5-158 GIC virtual interface control registers ................................................................... 5-165 The virtual CPU interface ..................................................................................... 5-176 GIC virtual CPU interface registers ...................................................................... 5-177</p> <p>Appendix A Appendix B</p> <p>Pseudocode IndexA.1 Index of pseudocode functions ............................................................................ A-196</p> <p>Register NamesB.1 B.2 B.3 Alternative register names ................................................................................... B-200 Register name aliases ......................................................................................... B-201 Index of architectural names ............................................................................... B-202</p> <p>Appendix C</p> <p>Revisions Glossary</p> <p>iv</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. Non-Confidential</p> <p>ARM IHI 0048B ID061411</p> <p>Preface</p> <p>This preface introduces the ARM Generic Interrupt Controller Architecture Specification. It contains the following sections: About this specification on page vi Using this specification on page vii Conventions on page viii Additional reading on page ix Feedback on page x.</p> <p>ARM IHI 0048B ID061411</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. Non-Confidential</p> <p>v</p> <p>Preface About this specification</p> <p>About this specificationThis specification describes the ARM Generic Interrupt Controller (GIC) architecture. Throughout this document, references to the GIC or a GIC refer to a device that implements this GIC architecture. Unless the context makes it clear that a reference is to an IMPLEMENTATION DEFINED feature of the device, these references describe the requirements of this specification.</p> <p>Intended audienceThe specification is written for users that want to design, implement, or program the GIC in a range of ARM-compliant implementations from simple uniprocessor implementations to complex multiprocessor systems. The specification assumes that users have some experience of ARM products. It does not assume experience of the GIC.</p> <p>vi</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. Non-Confidential</p> <p>ARM IHI 0048B ID061411</p> <p>Preface Using this specification</p> <p>Using this specificationThis specification is organized into the following chapters: Chapter 1 Introduction Read this for an overview of the GIC, and information about the terminology used in this document. Chapter 2 GIC Partitioning Read this for a description of the major interfaces and components of the GIC. The chapter also introduces how they operate, in a simple implementation. Chapter 3 Interrupt Handling and Prioritization Read this for a description of the requirements for interrupt handling, and the interrupt priority scheme for a GIC. Chapter 4 Programmers Model Read this for a description of the Distributor and CPU interface registers. Chapter 5 GIC Support for Virtualization Read this for a description of how the GIC Virtualization Extensions support the implementation of a GIC in a multiprocessor system that supports processor virtualization.This chapter includes a description of the programmers model for the virtual interface control and virtual CPU interface registers. Appendix A Pseudocode Index Read this for an index to the pseudocode functions defined in this specification. Appendix B Register Names Read this for a description of the differences in the register names in earlier descriptions of the GIC architecture, and for an alphabetic index of the register names. Appendix C Revisions Read this for a description of the technical changes between released issues of this book. Glossary Read this for definitions of some terms used in this book.</p> <p>ARM IHI 0048B ID061411</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. Non-Confidential</p> <p>vii</p> <p>Preface Conventions</p> <p>ConventionsThe following sections describe conventions that this book can use: General typographic conventions Signals Numbers Pseudocode descriptions.</p> <p>General typographic conventionsThe typographical conventions are: italic boldmonospace</p> <p>Introduces special terminology, denotes internal cross-references and citations, or highlights an important note. Denotes signal names, and is used for terms in descriptive lists, where appropriate. Used for assembler syntax descriptions, pseudocode, and source code examples. Also used in the main text for instruction mnemonics and for references to other items appearing in assembler syntax descriptions, pseudocode, and source code examples.</p> <p>SMALL CAPITALS</p> <p>Used for a few terms that have specific technical meanings, and are included in the Glossary. Indicates a link. This can be: a URL, for example, http://infocenter.arm.com a cross-reference, that includes the page number of the referenced information if it is not on the current page, for example, Distributor Control Register, GICD_CTLR on page 4-83 a link, to a chapter or appendix, or to a glossary entry, or to the section of the document that defines the colored term, for example Banked register or GICD_CTLR.</p> <p>Colored text</p> <p>SignalsIn general this specification does not define processor signals, but it does include some signal examples and recommendations. The signal conventions are: Signal level The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means: HIGH for active-HIGH signals LOW for active-LOW signals. At the start or end of a signal name denotes an active-LOW signal.</p> <p>Lower-case n</p> <p>NumbersNumbers are normally written in decimal. Binary numbers are preceded by 0b, and hexadecimal numbers by 0x. In both cases, the prefix and the associated value are written in a monospace font, for example 0xFFFF0000.</p> <p>Pseudocode descriptionsThis specification uses a form of pseudocode to provide precise descriptions of the specified functionality. This pseudocode is written in a monospace font, and follows the conventions described in the ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition.</p> <p>viii</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. Non-Confidential</p> <p>ARM IHI 0048B ID061411</p> <p>Preface Additional reading</p> <p>Additional readingThis section lists relevant publications from ARM and third parties. See the Infocenter, http://infocenter.arm.com, for access to ARM documentation.</p> <p>ARM publications ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition (ARM DDI 0406), issue C or later.</p> <p>Other publicationsThe following books are referred to in this manual, or provide more information: JEDEC Solid State Technology Association, Standard Manufactures Identification Code, JEP106.</p> <p>ARM IHI 0048B ID061411</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. Non-Confidential</p> <p>ix</p> <p>Preface Feedback</p> <p>FeedbackARM welcomes feedback on its documentation.</p> <p>Feedback on this specificationIf you have comments on the content of this specification, send e-mail to errata@arm.com. Give: the title the number, ARM IHI 0048B the page numbers to which your comments apply a concise explanation of your comments. ARM also welcomes general suggestions for additions and improvements.</p> <p>x</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. Non-Confidential</p> <p>ARM IHI 0048B ID061411</p> <p>Chapter 1 Introduction</p> <p>This chapter gives an overview of the GIC and information about the terminology used in this document. It contains the following sections: About the Generic Interrupt Controller architecture on page 1-12 Security Extensions support on page 1-14 Virtualization support on page 1-15 Terminology on page 1-16.</p> <p>ARM IHI 0048B ID061411</p> <p>Copyright 2008, 2011 ARM Limited. All rights reserved. Non-Confidential</p> <p>1-11</p> <p>1 Introduction 1.1 About the Generic Interrupt Controller architecture</p> <p>1.1</p> <p>About the Generic Interrupt Controller architectureThe Generic Interrupt Controller (GIC) architecture defines: the architectural requirements for handling all interrupt sources for any processor connected to a GIC a common interrupt controller programming interface applicable to uniproce...</p>

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