ihp im technologiepark 25 15236 frankfurt (oder) germany ihp im technologiepark 25 15236 frankfurt...
TRANSCRIPT
IHPIm Technologiepark 2515236 Frankfurt (Oder)
Germany
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
A System-on-Chip Implementationof the IEEE 802.11a MAC Layer
Goran Panić, Daniel Dietterle
Zoran Stamenković, Klaus Tittelbach-Helmrich
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
Overview
• Introduction
• Protocol ImplementationHardware/Software Partitioning
• System ArchitectureComponents Description
• Synthesis Results
Estimated Area & Power
• Layout ResultsFinal Design Results
• Summary
2
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
Introduction
• Functionality of the MAC described in the IEEE 802.11a standard
• Wireless market
Atheros, Intersil, Cisco, TI, …
• Target: baseband, MAC and radio transcieving part integrated on a single chip
• IHP MAC - designed as a complete solution on chip
• Easy integration with the baseband
3
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
Design flow overview
Protocoldescription
Performanceinvestigation
Hw Acc design
Architecturedescription
Systemimplementation
SDL model
Simulations &Measurements
VHDLmodel
Logic and Layout Synthesis
Abstract and HDL level
Translation toC model
Hw/Swpartitioning
Systemconsideration
Datapreparation
4
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
Protocol Implementation
IEEE 802.11System Overview
SingleStation(LanSize)
Testbench
AirLink
RadioChannel
Distribution_system
Config_Generator
LLC_IFMLME_SAP
PLME_SAP
Single_Station
MAC
LLC_handler
OFDM_PHY
Distribution_Channel
Config_Distributor
LLC_IF
MLME_SAP
PHY_SAP
PLME_SAP
MAC_SAP
RadioChannel
SDL Model
• Abstract protocol model
• Generation of C model
• Performance estimation in order to perform Hw/Sw partitioning
5
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
Hardware Accelerator
CRC
Bus_Interface
Control
PHY_Interface
Tx
CRC
RC4
CRC
Channel_State
Timers MIB
Rx
Processor bus
On-chip RAM Baseband processor
• executes timing critical MAC functions
• Timers, CRC, RC4, address filter
• reduction of power consumption
• interface between baseband and CPU
• completely modeled in VHDL
• synthesized and simulated for 80MHz
• 5x512B single-port memory
• 2x256B dual-port memory
• soft resetable
6
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
System Architecture
MIPS 4KEpCore
Peripheral BusController
EC-to-X BusController
I2C
HwAcc
UART 0
SRAM FLASH
Serial 0
Serial 1
I2C
EPP
GPIO
EJTAG
UART 1
GPIO
• complete rtl description in VHDL/Verilog• verification environment and synthesis scripts
EC
X#0
X#1
7
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
System Architecture
MIPS 4KEpCore
Peripheral BusController
EC-to-X BusController
I2C
HwAcc
UART 0
Async RAM Async ROM
Serial 0
Serial 1
I2C
EPP
GPIO
EJTAG
UART 1
GPIO
• complete rtl description in VHDL/Verilog• verification environment and synthesis scripts
EC
X#0
X#1
Test program
TestEnvironment
Componentsverification
models
8
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
Synthesis Results
Design nameEstimatedarea (%)
Estimatedpower(%)
MIPS core 16.7 17
I 2C bus controller 0.3 0.4
UART x 2 3.5
EC-to-X bus controller 3.4 0.8
Peripheral buscontroller
0.8 1.6
Accelerator core 14.1 15.9
Single-port RAM 512B x 5 41.6 49.7
Dual-port RAM 256B x 2 19.4 9.5
GPIO 0.8 1.3
Glue logic 0.2 0.3
Chip 100 100
9
2.7
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
System Layout
Facts• Technology: IHP 0.25μm CMOS
• Area: ~ 30 mm2
• Number of gates: 420,000 NAND
• Number of pins: 140 sig + 16 pow
• Package: PQFP 208L 28*28*3.35P0.5 • Peak Power: ~1W at 80 MHz, 2.5V
• Chip testing:
Successful on Agilent 93000
10
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2003 - All rights reserved
Summary
Presented design flow provides:
• Efficient and flexible modeling and implementation of a MAC protocol
• Low power
• High performance
• Easy integration to a baseband processing unit
What can be done in the future:
• PCMCIA interface to TCP/IP layer (rev 1)
• Custom connection to the baseband (rev 1)
• Usage of high performance memory blocks (rev 1)
• Clock gating
• AMBA bus
11