DEVICE RESEARCH CONFERENCE 1201

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IIIa-4 A Charge Coupled Field-Effect Transistor-N. Bluzer and S. Hayek, Westinghouse Advanced Technology Laboratories, Baltimore, MD.

A metal-oxide-semiconductor structure called a “Charge Coupled Field Effect Transistor” (CCFET) has been fabricated. This new structure is uniquely suitable for appli- cation leading towards improved input and output structures of Charge Coupled Devices (CCD). Use of the CCFET with a passive feedback network for a CCD input structure should exhibit reduced threshold variations between different parallel CCD inputs and wider injection bandwidth when the CCD inputs are operated in the direct injection (current input) mode. Moreover, use of the CCFET structure as the CCD readout stage will provide lower noise and higher operating bandwidth for sensing the signal charge present in the CCD’s output well.

This novel metal-oxide-semiconductor structure con- sists of two charge coupled field effect transistors. The CCFET contains a surface p-channel enhancement mode MOSFET below which an n-channel depletion mode MOS- FET is located. Both the surface and buried channels are contained in an n-type, thin (3.5 pm) , high resistivity ( > l o 0 -cm) epi layer grown over a p-type (100) silicon sub- strate. A conventional MOS gate is located above the epi layer and the substrate-epi junction is used as a back gate. Electrical access to the surface and buried channels is achieved respectively with two p+ regions (source and drain) nested within two n+ regions (source and drain) all of which are ion implanted in the epitaxial layer.

Experiments show that an ac current flowing in the overlying p-channel will modulate the current flowing in the underlying n-channel even though the surface and back gates are at dc voltages. This modulation occurs because the sur- face current, flowing transverse to the surface gate’s field lines, screens the surface gate’s field lines thereby modulating the depletion region which controls the thickness of the underlying channel. Changing the dc reverse bias voltage between the epi and substrate varies the size of the modula- tion affected by the surface current on the underlying current. The theory and the application of this device in AGC circuits, CCD readout and MOS threshold cancellation in CCD input structures will be discussed.

IIIa-5 Monolithic Microwave Power Lumped Element Integrated Circuits*-A. L. Harrington and J. E. Steenber- gen, TRW Semiconductors, Lawndale, CA 90260.

High power monolithic microwave lumped element integrated circuits which will operate in the L-band range are being developed. A “V”-groove process on P-I-N epitaxy is presented that allows top contacting and isolation of the

* These developments are being partially supported by contract No. N000014-75-C-0405 with the Naval Research Laboratories, 1975-1977.

active regions from the surrounding area. Active capacitive and inductive elements can then be processed on a single monolithic silicon chip. Epitaxial P+/v/N +/N-layers and anisotropic etching of (100) oriented silicon is used to isolate and contact buried layers. Dielectric filling of “V”-groove moats provides inductor media and planarizes the structure. Resultant N-P-N transistor, inductor and capacitor combina- tions are equivalent to those of today’s hybrid microwave transistor. The “V”-grooved integrated structure offers batch processing, elimination of critical wire bonds, excellent thermal dissipation and simplified packaging.

Test results of a 30 watt @ 1.5 GHz device with 7 dB gain, and the co-processing technology for the combination of active and passive circuit matching elements on a single monolithic chip, will be discussed.

IIIa-6 SIT and SIT Thyristor-Jun-ichi Nishizawa, Research Institute of Electrical Communication, Tohoku University, Sendai, Japan.

A static induction transistor (SIT) which shows non- saturating and exponential I-V characteristics, is prepared in a new mesa type structure by a dry etching technology. This shows 1) a small negative feedback effect, 2) a small source- gate capacitance, 3) a small gate-drain capacitance, 4) a low gate series resistance, 5 ) a high source-gate break-down vol- tage, 6) a small thermal resistance, and 7) a high a cut-off frequency, and is the most promising for high frequency and high power operation-already 20 W output at 2 GHz, and expected more than 100 W in a few months. The fabrication process is a three mask process in which no phlotolithographic accuracy is required. Fabricated Si SIT has a gain of 11 dB at 900 MHz and its cut-off frequency exceeds 4 GHz, which can be also applied as a static induction thyristor, a new type of thyristor, which was also fabricated by a conventional tech- nology. This thyristor shows 1) a very short switching time, 2) a very small switching energy, 3) high efficiency and high speed dc switching, and 4) an ease in producing high power devices. A carrier injection from an anode makes up a gate potential to express a turn-on with a negative resistance, and a negative bias supply to the gate stops the carrier injection to show a turn-off even if a dc current flows. Less than 0.35 ps of turn-off time and more than 200 V of blocking voltage have been realized, and the current gain is about 10 even in the transient already and inverse voltage as high as several thousand volts are expected. And this is the most promising device in high-speed and high-power dc operation such as a dc power transmission.

IIIa-7 Experimental Determination of Carrier Velocities in Inversion Layers on Silicon*-R. W. Coen and R. S. Muller, Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of Cali- fornia, Berkeley, CA 94720.

In this paper we present velocity-field curves for sur- face free-carriers that have been obtained from measure- ments on resistive-gate 1GFET’s.l The measurements were performed by varying both transverse and longitudinal fields on n- and p-channel MOS transistors. The transistors were