image courtesy: intel welcome to cs250 vlsi …cs250/fa10/handouts/section1-web.pdfwelcome to cs250...
TRANSCRIPT
![Page 1: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/1.jpg)
Welcome to CS250 VLSI Systems Design9/2/10Yunsup Lee
Image Courtesy: Intel
![Page 2: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/2.jpg)
• Email: [email protected]
• Please add [CS250] in the subject
• Will try to get back in a day
• CS250 Newsgroup
• Post questions to the newsgroup so everyone else can read the answer as well
• Sections: Thursday, 5-6pm, 310 SODA
• I can’t make September 23’s section, can we do it on September 21?
• Office Hours: Tuesday, 10-11am, 711 SODA
YUNSUP LEE
![Page 3: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/3.jpg)
Remember!
• NEVER post materials online
• Tools
• Documents
• Technology files
• Methodology scripts
![Page 4: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/4.jpg)
Sorry,
• Only one machine on-line
• icom1.eecs.berkeley.edu
• Trying to get more machines now
• SVN server not on-line yet
• Will write a news flash to the newsgroup when I make more progress on infrastructure
![Page 5: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/5.jpg)
What is my job?
Execute SIM
VerilogSource(Behav)
BehavSim
VCS
VPD TestOutputs
DVE GUI
VerilogSource(RTL)
VCS Design Compiler
Formality
Design Vision GUI
IC Compiler (DP)
IC Compiler (P&R)
ConstraintsFile
VerificationResults
ConstraintsStd.Cell
Library
RTLSim Gate
LevelNetlist
TimingArea
DelayFile
TLU+Files
FloorPlan
ConstraintsFile
GateLevelNetlist
TimingArea Layout Parasitics
FileDelayFile
Execute SIM
GuidanceFile
VPD TestOutputs
DVE GUI
VCS
PostSynSim
Execute SIM
VPD TestOutputs
DVE GUI
VCS
PostP&RSim
Execute SIM
VPD TestOutputs
DVE GUI
IC Compiler GUI
PrimeTime
VCD
VPD2VCD
PowerEstimates
![Page 6: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/6.jpg)
How? Three labs + Project
• Lab 1: GCD: VLSI’s Hello World• 8/30 - 9/13 before class (2 weeks)
• Lab 2: Write and Synthesize a Two-Stage/Three-Stage Maven-v2 Processor• More about RTL implementation and synthesis
• 9/13 - 10/4 before class (3 weeks)
• Lab 3: ASIC Implementation of a Three-Stage Maven-v2 Processor with On-Chips Caches• More about using the SRAM/Cache compilers, Place+Route, Power
• 9/13 - 10/4 before class (3 weeks)
• Project• Give Maven-v3 as baseline
• Explore one or more micro-architectural variations to improve performance or energy efficiency
![Page 7: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/7.jpg)
• Greatest Common Divisor
• Things that are provided
• Test Harness
• Things that you need to do
• Write GCD RTL
• Push it through the tool flow
• Goal
• Recap Verilog Coding
• Get a feeling of all the tools
Lab 1: GCD
![Page 8: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/8.jpg)
Lab 2: Maven-v2 RTL Implementation + Synthesis
• Maven: Stands for Malleable Array of Vector-thread ENgines
• Things that are provided
• Test Harness (which loads programs)
• Maven-v1 RTL Implementation
• Maven ISA Simulator / Maven C/C++ Compiler
• Things that you need to do
• Write Maven-v2 RTL
• Synthesize processor / Formally Verify
• Goal
• Correct Execution
• Minimize Clock Frequency / Post Synthesis Area
![Page 9: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/9.jpg)
Maven-v1 vs. Maven-v2
• Maven-v1 (5 instructions) 1 stage pipeline
• LW, SW, ADDIU, BNE, MTC0
• Maven-v2 (33 instructions) 2 stage pipeline
• LW, SW
• ADDIU, SLTI, SLTIU, ANDI, ORI, XORI, LUI
• SLL, SRL, SRA, SLLV, SRLV, SRAV
• ADDU, SUBU, AND, OR, XOR, NOR, SLT, SLTU
• J, JAL, JR, JALR
• BEQ, BNE, BLEZ, BGTZ, BLTZ, BGEZ
• MFC0, MTC0
• No Branch Delay Slot!
![Page 10: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/10.jpg)
Lab 3: Maven-v2 Place and Route + Power
• Things that are provided
• Test Harness
• SRAM/Cache Compiler
• Things that you need to do
• Integrate Caches to your design (make it more realistic)
• Modify your RTL
• Synthesize Core
• Place and Route design
• Estimate Power / Make an analytic power/energy model
• Goal
• Correct Execution
• Minimize Area / Minimize Power
![Page 11: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/11.jpg)
Any Questions so far?
• CAD Tools generate a lot of data. You should be able to script. Python is strongly recommended.
• Mac Preview doesn’t copy&paste newlines. Use Adobe PDF Reader to copy&paste commands from the labs.
• Labs are 15% of your grade
• Each student gets a total of four late days
• Everything goes into the SVN repository
• Your writeup should only be in text or PDF
![Page 12: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/12.jpg)
Greatest Common Divisor
• Euclidean Algorithm
• START (A, B)
• if (A < B)
• SWAP (A, B)
• else if (B != 0)
• SUBTRACT (A-B, B)
• else
• DONE gcd=A
START (32, 48)A<B SWAP (48, 32)B!=0 SUBTRACT (16, 32)A<B SWAP (32, 16)B!=0 SUBTRACT (16, 16)B!=0 SUBTRACT (0, 16)A<B SWAP (16, 0)B=0 DONE GCD=16
![Page 13: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/13.jpg)
GCD Port Interface
operands_rdy
operands_val
operands_bits_A
operands_bits_B
result_bits_data
result_rdy
result_val
clk reset
![Page 14: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/14.jpg)
Let’s form groups
• Make 5 groups by doing
• group # = (Birth Month + Birth Day) MOD 5
• Will give you 5-10 minutes
![Page 15: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/15.jpg)
What should I do?
• Figure out what goes into the datapath, and control
• datapath: big functional units of your design
• control: signals which drive the datapath
• Figure out what states you need
• Figure out the transition between states
• Figure out the following signals for each state
• A_mux_sel, A_en, B_mux_sel, B_en
• operands_rdy, results_val
![Page 16: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/16.jpg)
Tick-tock!
B
A_lt_B B_zero
zero? lt
A
sub
A_mux_sel
A_en
B_mux_sel
B_en
operands_val
operands_rdy
result_val
result_rdy
operands_A
operands_B
result
WAIT
CALC
DONE
Waiting for new input operands
Swapping and subtracting
Waiting for consumer to take the result
reset
![Page 17: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/17.jpg)
Now we’ve wrote some RTL ...
• Simulate your RTL until it works.
• Synopsys VCS (vcs-sim-rtl)
• Now give me some hardware (gate-level netlist), aka Synthesize.
• Synopsys Design Compiler (dc-syn)
• Is my hardware correct? Simulate your gate-level netlist.
• Synopsys VCS (vcs-sim-gl-syn)
• I want a piece of silicon, aka Place and Route.
• Synopsys IC Compiler (icc-par)
• Is my piece of silicon correct? Simulate your place-and-routed gate-level netlist. You also need to record bit flipping information by doing this.
• Synopsys VCS (vcs-sim-gl-par)
• How much power does my circuit burn?
• Synopsys PrimeTime (pt-pwr)
![Page 18: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/18.jpg)
Process Technology
• Synopsys 90nm Educational Library
• You can use this library without NDA
• Be careful not to put stuff google accessible
• 1 POLY + 9 METAL
• Standard Cells + SRAM Cells
• No Memory Compiler, but we built one for you
• OpenSparc MegaCells
• I/O Pads
![Page 19: Image Courtesy: Intel Welcome to CS250 VLSI …cs250/fa10/handouts/section1-web.pdfWelcome to CS250 VLSI Systems Design 9/2/10 Yunsup Lee Image Courtesy: Intel](https://reader034.vdocuments.net/reader034/viewer/2022051602/5aef02a77f8b9aa9168bf9ad/html5/thumbnails/19.jpg)
Any Questions?