image “padding” in limited-memory fpga systems

18
1 Turri MAPLD 2005/P160 mage “Padding” In Limited-Memor FPGA Systems liam Turri ([email protected]) Simone ([email protected]) tran Federal Corp. 7 Colonel Glenn Highway, Suite 210 ton, OH 45431-1672 -429-9008 x104 MAPLD 2005 Conference Presentation

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Image “Padding” In Limited-Memory FPGA Systems. MAPLD 2005 Conference Presentation. William Turri ([email protected]) Ken Simone ([email protected]) Systran Federal Corp. 4027 Colonel Glenn Highway, Suite 210 Dayton, OH 45431-1672 937-429-9008 x104. Research Requirements. - PowerPoint PPT Presentation

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Page 1: Image “Padding” In Limited-Memory FPGA Systems

1Turri MAPLD 2005/P160

Image “Padding” In Limited-MemoryFPGA Systems

William Turri ([email protected])Ken Simone ([email protected])Systran Federal Corp.4027 Colonel Glenn Highway, Suite 210Dayton, OH 45431-1672937-429-9008 x104

MAPLD 2005 Conference Presentation

Page 2: Image “Padding” In Limited-Memory FPGA Systems

2Turri MAPLD 2005/P160

Research Requirements

• Develop an efficient means of managing large (512 MB to 1 GB) raw SAR images in memory, for wavelet-based compression on an FPGA

• Minimize the number of read/write operations required to perform a wavelet transform

• Preserve quality and avoid creating artifacts

Page 3: Image “Padding” In Limited-Memory FPGA Systems

3Turri MAPLD 2005/P160

SAR Compression Background• What are we compressing?

– Collections of SAR data in a raw, unprocessed format, collected by a sensor and stored in contiguous memory

• Why are we compressing it?– Raw SAR images can be up to 1 GB in size, and must be

compressed to facillitate transmission to airborne platforms to ground-based processing stations

• How are we compressing it?– Wavelet transforms have proven effective for compressing

many kinds of images, including SAR. Research has identified the 5/3 Wavelet Transform as well-suited to raw SAR data

Page 4: Image “Padding” In Limited-Memory FPGA Systems

4Turri MAPLD 2005/P160

Wavelet Transform BackgroundOriginal Image Row Transformed Image

0 n-1… 0 n-1(n/2)

k

k+(n/2)

Page 5: Image “Padding” In Limited-Memory FPGA Systems

5Turri MAPLD 2005/P160

5/3 Wavelet Filters

Low pass filter uses 5 taps

High pass filter uses 3 taps

Page 6: Image “Padding” In Limited-Memory FPGA Systems

6Turri MAPLD 2005/P160

Filter Equations• The preceding transform may be represented by the

following algorithms, and we may identify the data points (k indices) required to perform a computation (assume N = 32 and k ranges from 0 to 15)

)12(2

)22()2(0

001

krkrkr

Intkd

High-Pass

4

)()1()2()( 11

01

kdkdIntkrkr

d1(k) needs [2k, 2k+2, 2k+1]k = 0 => [0, 1, 2]k = 15 => [30, 31, 32]

r1(k) needs [2k-2, 2k-1, 2k, 2k+1, 2k+2]k = 0 => [-2, -1, 0, 1, 2] k = 15 => [28, 29, 30, 31, 32]

Indices lie beyond the lowerand upper bounds of N

Low-Pass

Index lies beyond the upperbound of N

Page 7: Image “Padding” In Limited-Memory FPGA Systems

7Turri MAPLD 2005/P160

Need for “Extension”

These values must be supplied throughsome form of extension…

…and so mustthis value.

Extension minimizesthe degradationalong the image borders, resulting from the wavelettransform beingused.

Page 8: Image “Padding” In Limited-Memory FPGA Systems

8Turri MAPLD 2005/P160

Extension Options

a b c … x y zbc y x

Odd-Symmetric

a b c … x y zab z y

Even-Symmetric

a b c … x y zyx a b

Periodic

For the integer 5/3 transform, Odd-Symmetric extension gives the best numerical results

Page 9: Image “Padding” In Limited-Memory FPGA Systems

9Turri MAPLD 2005/P160

Values Needed for Odd-Symmetric Extension

These values must be supplied throughsome form of extension…

…and so mustthis value.

a b cbc w x y z y

Page 10: Image “Padding” In Limited-Memory FPGA Systems

10Turri MAPLD 2005/P160

Possible Odd-Symmetric Approaches• Extended pixels could be added to the image array in memory

and fetched normally– Fetching extended values through additional memory read operations will

result in unnecessary delays in processing– Storing additional values will unnecessarily consume available memory

• The extended values could be “fetched” by reading the same value twice when processing boundary coefficients– This presents the same problem of creating unnecessary delays by

introducing additional memory read operations• Additional logic dedicated to processing the boundary

coefficients could be added to the hardware– Must consume minimal resources and not slow the system when

processing non-boundary coefficients– Should account for the extended coefficients based on mathematical

operations, if possible, rather than having to create additional stored values

Page 11: Image “Padding” In Limited-Memory FPGA Systems

11Turri MAPLD 2005/P160

Left-Side Extension for r1

)12(2

)22()2(0

001

krkrkr

Intkd

4

)()1()2()( 11

01

kdkdIntkrkr

4

)12(2

)22()2()12(

2)2()22(

)2(0

000

00

0

krkrkr

krkrkr

Intkr

For k = 0, these values must be generated through extension, giving…

4

)12(2

)22()2()12(

2

)2()22(

)2(0

000

00

0

krkrkr

krkrkr

Intkr

4

)()()2( 11

0

kdkdIntkr

4

)(2)2( 1

0

kdIntkr

2

)()2( 1

0

kdIntkr

Page 12: Image “Padding” In Limited-Memory FPGA Systems

12Turri MAPLD 2005/P160

Right-Side Extension for d1

For we get: 12

N

k

1)12

(22

1)12

(2)12

(2

)12

( 0

00

1

Nr

Nr

Nr

IntN

d

)1(

2

)()2(0

00 NrNrNr

Int

This value must be generated through extension, giving…

)1(

2

)2()2(0

00 NrNrNr

Int

)1(

2

)2(20

0 NrNr

Int

)1()2( 00 NrNrInt

)12(2

)22()2(0

001

krkrkr

Intkd

)12(

2

)2(20

0 krkr

Intgeneralized

Page 13: Image “Padding” In Limited-Memory FPGA Systems

13Turri MAPLD 2005/P160

Final EquationsFor k = 0:

)12(2

)22()2(0

001

krkrkr

Intkd

4

)(2)2()( 1

01

kdIntkrkr

For k = 1 to (N/2 – 2): )12(

2

)22()2(0

001

krkrkr

Intkd

4

)()1()2()( 11

01

kdkdIntkrkr

For k = (N/2 – 1):

4

)()1()2()( 11

01

kdkdIntkrkr

These rational forms of the equations were chosen because

they best suit our hardware design

)12(

2

)2(2)( 0

01 kr

krIntkd

Page 14: Image “Padding” In Limited-Memory FPGA Systems

14Turri MAPLD 2005/P160

Top-Level Hardwared1(k)

d1(k-1)(registered)

Hard-wired right shift by 1(divide by 2)

Hard-wired right shift by 2(divide by 4)

Page 15: Image “Padding” In Limited-Memory FPGA Systems

15Turri MAPLD 2005/P160

r1 Hardware

d1(k)

d1(k-1)

When k = 0, MUX passes d1(k)to the ADD8, givingand performing extension.

Otherwise, MUX passes d1(k-1)to the ADD8, giving

4

)(2 1 kd

4

)()1( 11 kdkd

Page 16: Image “Padding” In Limited-Memory FPGA Systems

16Turri MAPLD 2005/P160

d1 Hardwarer0(2k)

r0(2k+2)

When k = (N/2-1), lower MUX passes r0(2k) to the ADD8, givingand performing extension.

Otherwise, lower MUX passes r0(2k+2)to the ADD8, giving

2

)2(2 0 kr

2

)22()2( 00 krkr

Page 17: Image “Padding” In Limited-Memory FPGA Systems

17Turri MAPLD 2005/P160

Results of Extension

• Incorporating odd-periodic extension into the hardware involved only two minor changes from a system that does not incorporate extension– Increase from a 3-to-1 MUX to a 4-to-1 MUX to

accommodate d1 extension

– Addition of a 2-to-1 MUX to accommodate r1 extension

– Impact on resource consumption and timing characteristics is minimal

Page 18: Image “Padding” In Limited-Memory FPGA Systems

18Turri MAPLD 2005/P160

Summary and Suggestions

• Adding odd-symmetric extension through dedicated hardware effectively met our research goal with minimal impact on performance

• Similar approach could be used with other wavelet transforms, with similar anticipated results

• Similar approach could be used with the other forms of extension (even-symmetric and periodic)