images courtesy of addison wesley longman, inc. copyright © 2001 chapter 10 input/output...

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Chapter 10Chapter 10Input/Output OrganizationInput/Output Organization


Chapter OutlineChapter Outline

• Asynchronous data transfersAsynchronous data transfers

• Programmed I/OProgrammed I/O

• InterruptsInterrupts

• Direct Memory AccessDirect Memory Access

• I/O ProcessorsI/O Processors

• Serial CommunicationSerial Communication

• Serial Communication StandardsSerial Communication Standards


Asynchronous Data TransfersAsynchronous Data Transfers


Source-initiated Data TransferSource-initiated Data Transfer


Destination-initiated Data Destination-initiated Data TransferTransfer


Source-initiated Data Transfer Source-initiated Data Transfer with Handshakingwith Handshaking


Destination-initiated Data Destination-initiated Data Transfer with HandshakingTransfer with Handshaking


Programmed I/OProgrammed I/O


ExampleExample


New InstructionsNew Instructions


New Control SignalsNew Control Signals

• IO differentiates I/O and memory IO differentiates I/O and memory accessesaccesses– IO = 1 for I/O accessIO = 1 for I/O access– IO = 0 for memory accessIO = 0 for memory access


New States and RTL CodeNew States and RTL Code


CPU ModificationsCPU Modifications

• Modify register sectionModify register section




• Modify ALUModify ALU





• Modify control unit (hard-wired)Modify control unit (hard-wired)






• Register and ALU sections unchangedRegister and ALU sections unchanged






• Register and ALU sections unchangedRegister and ALU sections unchanged

• One new micro-operation: DR One new micro-operation: DR Input Input PortPort


Control Unit ChangesControl Unit Changes


Control Unit Changes - INC Control Unit Changes - INC and CLR signalsand CLR signals


Control Unit Changes - Control Unit Changes - Memory Read SignalMemory Read Signal

• Memory Read = READ ^ Memory Read = READ ^ IOIO’’


InterruptsInterrupts

• PollingPolling


InterruptsInterrupts

• IRQ - Interrupt RequestIRQ - Interrupt Request

• IACK - Interrupt AcknowledgeIACK - Interrupt Acknowledge


Types of InterruptsTypes of Interrupts

• ExternalExternal




• InternalInternal




• InternalInternal

• SoftwareSoftware


Processing InterruptsProcessing Interrupts

• Do nothing (until the current instruction Do nothing (until the current instruction has been executed)has been executed)




• Get handler address (vectored)Get handler address (vectored)




• Get handler address (vectored)Get handler address (vectored)

• Invoke handler routineInvoke handler routine


Vectored Interrupt HardwareVectored Interrupt Hardware


Non-vectored Interrupt Non-vectored Interrupt HardwareHardware


Multiple Non-vectored Multiple Non-vectored InterruptsInterrupts


Daisy ChainingDaisy Chaining


IACKIACKinin and IACK and IACKoutout


Parallel Priority InterruptsParallel Priority Interrupts


Interrupt StatesInterrupt States


Direct Memory AccessDirect Memory Access


DMA ControllerDMA Controller


DMA Transfer ModesDMA Transfer Modes

• Block/Burst ModeBlock/Burst Mode




• Cycle Stealing ModeCycle Stealing Mode




• Cycle Stealing ModeCycle Stealing Mode

• Transparent ModeTransparent Mode


CPU Modifications - Micro-CPU Modifications - Micro-operationsoperations


I/O ProcessorsI/O Processors


I/O Processors - operationsI/O Processors - operations

• Block transfer commandsBlock transfer commands




• ALU operationsALU operations




• ALU operationsALU operations

• Control commandsControl commands


Asynchronous Serial Asynchronous Serial CommunicationCommunication

• bps - Bits Per Second (baud rate)bps - Bits Per Second (baud rate)




• start bitstart bit





• parity bitparity bit






• stop bit(s)stop bit(s)






• stop bit(s)stop bit(s)

• bit timebit time


Synchronous Serial Synchronous Serial Communication - HDLCCommunication - HDLC


Universal Asynchronous Universal Asynchronous Receiver/TransmittersReceiver/Transmitters


UART Internal ConfigurationUART Internal Configuration


• Request To SendRequest To Send• Clear To SendClear To Send• Transmission DataTransmission Data• Data Terminal ReadyData Terminal Ready• Data Set ReadyData Set Ready• Received DataReceived Data• Data Carrier DetectData Carrier Detect• Ring IndicatorRing Indicator• GroundGround

RS 232C Standard - SignalsRS 232C Standard - Signals


RS 232C Standard - RS 232C Standard - ConnectionConnection

• Use RTS, CTS, DTR, and DSR to verify Use RTS, CTS, DTR, and DSR to verify that both devices are activethat both devices are active




• Use RI to indicate call statusUse RI to indicate call status





• Use DCD to establish connectivityUse DCD to establish connectivity





• Use DCD to establish connectivityUse DCD to establish connectivity

• Use TD and RD to transfer data, and Use TD and RD to transfer data, and RTS and CTS to coordinate transfersRTS and CTS to coordinate transfers


RS 422 Standard - SignalsRS 422 Standard - Signals


Universal Serial Bus StandardUniversal Serial Bus Standard

• Connects one port to several devicesConnects one port to several devices


Universal Serial Bus StandardUniversal Serial Bus Standard

• Connects one port to several devicesConnects one port to several devices

• Transfers data in packetsTransfers data in packets– Token packetsToken packets– Data packetsData packets– Handshake packetsHandshake packets– Special PacketsSpecial Packets


USB Packet FormatsUSB Packet Formats


SummarySummary

• Asynchronous data transfersAsynchronous data transfers

• Programmed I/OProgrammed I/O

• InterruptsInterrupts

• Direct Memory AccessDirect Memory Access

• I/O ProcessorsI/O Processors

• Serial CommunicationSerial Communication

• Serial Communication StandardsSerial Communication Standards

images courtesy of addison wesley longman, inc. copyright © 2001 chapter 10 input/output...

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