Implement a 2x2 MIMO OFDM-based channel measurement system (no data yet) at 2.4 GHz

Perform baseband processing and digital up and down conversion on Nallatech Xtreme DSP Kits using System Generator tools

Integrate DSP Kits with National Instruments radios for amplification and analog up and down conversion

Download large amounts of received data to a PC over PCI interface in practical amount of time

Have a fully operational system by September 2004

IFFTCyclicSuffix

Upconvertto IF

Upconvert to 2.4 GHz

(using NI radios)

Low PassFilter

Symbol

IFFTCyclicSuffix

Upconvertto IF

Upconvert to 2.4 GHz(using NI radios)

Low PassFilter

Symbol

64 pointstreamin

g IFFT

Adjustable

lengthfrom 0-

64

802.11 compliant 60 tap root

raised cosine with 5x

oversampling

Upconvert to 25 MHz

carrier

Analog upconversion

performed in NI Radios

Coarse Sync.

Symbol timing Fine timing

PLL

Low PassFilter

DownconvertTo Baseband

FFT De-Suffix

Estimate Channel

Coarse Sync.

Symbol timing Fine timing

PLL

Low PassFilter

DownconvertTo Baseband

FFT De-Suffix

Estimate Channel

Length 48 correlator

implemented as FIR

Tracks phase of 15 MHz

carrier tone, using FIR loop

filter

Downconvert from 15 MHz

carrier

60 tap root raised

cosine FIR

Discard cyclic suffix

samples

Length 64 streaming

FFT

Filter – Root raised cosine filter, FCC compliant– Found proper filter order– Performed sufficient oversampling to smooth DAC output.

Cyclic suffix– Able to add cyclic suffix of adjustable length– Synchronized with IFFT to allow for unequal samples in, samples out

Associate FPGA clock with correct carrier frequency (IF)– Clock the FPGA at 100 MHz– Upconvert 20 MHz (RF BW) wide baseband signal to 25 MHz (IF)

Connection between the FPGA and the radio– Connected D/A converter to NI radios– Successful tests verified on spectrum analyzer + Oscilloscope

2 antennas need 2 different preambles for individual synchronization– Current implementation only accounts for single transmit antenna– Transmitters are timing synchronized but have nondeterministic phase– We require orthogonal pilot tones– Also require orthogonal short sequences with good correlation properties

Generating frames containing both preamble and measurement signals– Currently beginning integration– Must be able to accommodate long preamble to insure packet detection and

synchronization in measurements– Must be able to adjust cyclic suffix length according to symbol and channel type

Packet detection: detect the presence of a packet by correlating short training symbols

The coarse frequency estimation: use the spacing between correlation peaks to provide a rough carrier estimate to PLL

Design of Phase Locked Loop: robust to 16 kHz offset in 15 MHz carrier and integrated with coarse frequency estimator

FPGA clock: run the FPGA at 60 MHz for 20 MHz wide signal arriving at 15 MHz center frequency

Symbol timing recovery and sampling frequency mismatches– Must be able to advance/retreat periodically in order to match transmitter and receiver

sample times to symbol lengths– Good symbol timing is essential to FFT performance

Complex channel estimation: On chip or off?– Complex algorithms on chip allow us to download less data– Performing channel estimation offline allows more thorough analysis

Integrate synchronization with signal processing– Demodulate using PLL output– Estimate symbol timing using short symbol correlation– Estimate Tx sample times from PLL and correlation

Transmitter– able to transmit single channel input– still need to implement multiple channel inputs– still need to develop measurement signal input

Receiver– still need to integrate coarse synchronization, PLL, and down-stream processor to have a

fully functional receiver– still need to tune the parameters of the synchronization block for packet detection and PLL

convergence– still need to implement multiple channel outputs