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ImplementationandSynthesisofReversibleLogicusingMZIswitch

THESIS·APRIL2015

DOI:10.13140/RG.2.1.2126.1843

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PratikDutta

IndianInstituteofTechnologyPatna

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Implementation and Synthesis of Reversible Logic

using MZI switches

Submitted By

Pratik Dutta

A thesis in partial fulfillment for the degree of

Master of Engineering in

Information and Communication Engineering

Under the supervision of

Dr. Hafizur Rahaman Professor

Dept. of Information Technology Indian Institute of Engineering Science and Technology, Shibpur

Department of Information Technology Indian Institute of Engineering Science and Technology, Shibpur

West Bengal, India – 711103

April, 2015

Department of Information Technology

Indian Institute of Engineering Science and Technology, Shibpur

P.O:- Botanic Garden, Howrah–711 103

CERTIFICATE OF APPROVAL

It is certified that the entitled Implementation and Synthesis of Reversible

Logic Implementation using MZI switches is a record of bonafide work

carried out by Pratik Dutta under my supervision and guidance.

In my opinion, the work is satisfactory and has reached the standard

necessary for the submission in the final semester of Master of Engineering

in Information and Communication Engineering of the Indian Institute of

Engineering Science and Technology, Shibpur

(Dr. Hafizur Rahaman)

Professor

Department of Information Technology

Indian Institute of Engineering Science and Technology, Shibpur

Counter signed by:

(Dr. Arindam Biswas )

Associate Professor and Head

Department of Information Technology

Indian Institute of Engineering Science and Technology, Shibpur

(Dr. Amit Kumar Das)

Professor and Dean (FEAT)

Indian Institute of Engineering Science and Technology, Shibpur

Acknowledgment

I would hereby like to avail this opportunity to extend my heartfelt

gratitude to my project guide Dr. Hafizur Rahaman, Professor,

Department of Information Technology, Indian Institute of Engineering

Science and Technology, Shibpur, for his incessant encouragement,

sincere supervision, valuable advice and perfect guidance without which it

would not have been possible to complete the portion of the project

scheduled for the semester and the thesis in time.

I would also like to thank Dr. Arindam Biswas, Professor and Head

of the Department, Department of Information Technology, Indian

Institute of Engineering Science and Technology, Shibpur, as also other

faculty members and staff members who were always available for help,

as and when required.

Dated: April, 2015

Indian Institute of Engineering Science and Technology, Shibpur

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

.

Pratik Dutta [Reg. No: 210813009]

[Roll No: 161308007]

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Table of Contents Abstract ................................................................................................................................................. 5

Introduction ......................................................................................................................................... 6

1.1. Introduction ............................................................................................................................... 6

1.2. Scope and Organization of the Thesis ..................................................................................... 8

1.2.1 Preliminaries on Reversible Family ............................................................................. 8

1.2.2 Literature Survey ........................................................................................................... 8

1.2.3 Design and Implementaion of Reversible Logic Circuits ........................................... 8

Preliminaries: ..................................................................................................................................... 10

2.1. Reversibility ............................................................................................................................. 10

2.2. Semiconductor Optical Amplifier .......................................................................................... 10

2.3. MZI Architecture .................................................................................................................... 11

2.3.1. Optical cost and delay ................................................................................................. 12

2.3.2. Beam Combiner(BC) and Beam Splitter(BS) .............................................................. 12

2.3.3. Ancilla Lines ................................................................................................................ 12

2.4. Design of Reversible Gates with MZI .................................................................................... 13

Review on Reversible Logic Synthesis ........................................................................................... 14

All Optical Implementation of Mach-Zehnder Interferometer based Reversible CLA circuit 18

MZI-based All Optical Reversible CLA Circuit ............................................................................ 19

4.1. Introduction ............................................................................................................................. 19

4.2. Proposed Technique ............................................................................................................... 19

4.3. Hierarchical Design of 2n –bit CLA ........................................................................................ 20

4.3.1. Optimized 4-bit CLA Design with MZI ..................................................................... 20

4.3.2. Optimized 2n –bit CLA Design with MZI .................................................................. 21

4.4. Improved Staircase Design of n–bit CLA .............................................................................. 23

4.4.1. Calculation of Optical Cost ......................................................................................... 23

4.4.2. Calculation of Optical Delay ....................................................................................... 24

4.5. Conclusion ............................................................................................................................... 25

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All Optical Implementation of Different Sequential Elements using MZI Switches .............. 26

All Optical Implementation of Mach-Zehnder Interferometer based Reversible Flip-Flop ... 27

5.1. Introduction ............................................................................................................................. 27

5.2. Proposed Method .................................................................................................................... 27

5.2.1. RS Flip-flop .................................................................................................................. 28

5.2.2. D Flip-flop .................................................................................................................... 29

5.2.3. JK Flip-flop ................................................................................................................... 29

5.2.4. T Flip-flop ..................................................................................................................... 31

5.2.5. Master Slave Flip-flop ................................................................................................. 32

5.3. Conclusion ............................................................................................................................... 33

All Optical Implementation of Mach-Zehnder Interferometer based Reversible Sequential

Counters .............................................................................................................................................. 34

6.1. Introduction ............................................................................................................................. 34

6.2. Proposed Work ....................................................................................................................... 34

6.2.1. Asynchronous Counter ............................................................................................... 34

6.2.1.1. Design of 2-bit positive edge triggered down counter..................................... 34

6.2.1.2. Operational principle of 2-bit positive edge triggered down counter ............. 35

6.2.1.3. Theoritical model of Simulation ......................................................................... 38

6.2.2. Synchronous Counter .................................................................................................. 39

6.3. Conclusion ............................................................................................................................... 40

All Optical Implementation of Universal Shift-Register Using MZI Switches. ....................... 41

7.1. Introduction ............................................................................................................................. 41

7.2. Proposed Work ....................................................................................................................... 41

7.2.1. All-optical design of 4-bit universal shift register ..................................................... 42

7.2.2. Operational Principle of 4-bit universal Shift Register ............................................. 42

7.3. Conclusion ............................................................................................................................... 45

Conclusion and Future work ............................................................................................................ 46

Bibliography ...................................................................................................................................... 47

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List of Tables

Table I : Optical Cost and Delay of Reversible Gates ........................................................................... 13

Table II: Optical cost and Optical delay comparison ........................................................................... 25

Table III: Truth Table of RS Flip-Flop ................................................................................................... 28

Table IV: Truth Table of D Flip-Flop .................................................................................................... 29

Table V: Truth Table of JK Flip-Flop .................................................................................................... 30

Table VI: Truth Table of T Flip-Flop .................................................................................................... 31

Table VII: Relative Comparison table of Flip-Flops ............................................................................. 33

Table VIII: Different States of Asynchronous Positive Edge-triggered Down Counter....................... 36

Table IX: Analysis on design complexities of all optical reversible counters ..................................... 40

Table X: Different States of Universal Shift Register ........................................................................... 45

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List of Figures

Figure 2(a) : Schematic Diagram of SOA.............................................................................................. 10

Figure 2(b): Semiconductor Optical Amplifier based MZI Switch ...................................................... 12

Figure 2(c): MZI based optical implementation of Feynman gate ...................................................... 13

Figure 2(d) : MZI based optical implementation of Toffoli gate ......................................................... 13

Figure 4(a): Full adder circuit using MZI Switches ............................................................................ 20

Figure 4(b): 4-bit Optical Reversible Full Adder Circuit ..................................................................... 20

Figure 4(c): 4-bit CLA circuit with Group Generates and Group Propagates values. ......................... 22

Figure 4(d): Improved staircase structured n-bit CLA circuit ............................................................ 24

Figure 5(a): Classical design of RS Flip-Flop ....................................................................................... 28

Figure 5(b): RS Flip-Flop (NOR gate) implemented by MZI switch .................................................... 28

Figure 5(c): Classical design of D Flip-Flop ......................................................................................... 29

Figure 5(d): RS Flip-Flop (NOR gate) implemented by MZI switch .................................................... 29

Figure 5(e): Classical design of JK Flip-Flop ........................................................................................ 30

Figure 5(f): JK Flip-Flop implemented by MZI switch ........................................................................ 30

Figure 5(g): Classical design of T Flip-Flop ......................................................................................... 31

Figure 5(h): T Flip-Flop implemented by MZI switch ......................................................................... 31

Figure 5(i): Master-Slave RS Flip-Flop implemented by MZI switch .................................................. 32

Figure 5(j): Master Slave D Flip-Flop implemented by MZI switch .................................................... 32

Figure 5(k): Master Slave JK Flip-Flop implemented by MZI switch .................................................. 33

Figure 6.(d): Design of all optical reversible Asynchronous Negative Edge-triggered Up Counter ... 37

Figure 6.(e): Control flow analysis of Asynchronous Positive edge-triggered down counter. ........... 38

Figure 6.(f): Synchronous Negative edge-triggered up counter implemented by MZI switch ........... 39

Figure 6.(g): Synchronous Positive edge-triggered down counter implemented by MZI switch ....... 39

Figure 7.(a): 4-bit all Optical Universal Shift Register using MZI Switches ....................................... 44

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Abstract

Reversible circuits are of great importance in many applications involving low power design.

One of the main areas where reversible circuits play vital role is in optical computing. Reversible

logic has many other applications in several technologies such as quantum computation, digital

signal processing, cryptography, ultra low power CMOS design, nanotechnology,

thermodynamics and bioinformatics. Most of them are under research. In present days VLSI

technology is facing a real challenge with the exponential growth of packing density in VLSI

chip and CMOS technologies are reaching to a limit. So some alternative technology is required

to overcome from this stagnancy. Energy losses inform of heat generation in VLSI chip is a real

hurdle that is facing traditional CMOS technologies. Problem due to irreversibility of logic leads

to loss of energy, generation of heat, loss of information, slow computation.

Reversible logic may provide a potential solution of such problems. Among various reversible

approaches, optical computing has proved to be very significant in achieving high speed since it

uses photons in light which have unmatched speed. In the optical computer of the future, the

electronic circuits and wires will be replaced by a few optical fibers and films, making the

systems more efficient with no interference, more cost effective, lighter and more compact.

Based on optical computing, several optical switches have been proposed which have been

designed for future applications. One among them is MACH-ZEHNDER INTERFEROMETER

(MZI). In this thesis, we have studied behavior of MZI based switch and developed novel

approaches for implementation of reversible logic circuits.

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Chapter 1

Introduction

1.1. Introduction

The ultimate goal in present age of Information Technology is information generation

and dissemination by anybody, anything and anywhere. Very Large Scale Integration (VLSI)

technology has revolutionized the electronics industry and established the 20th

century as the

computer age. But, it is approaching its fundamental limits in the sub-micron miniaturization

process. The problems with traditional logic circuit has been highlighted by Ralph Merkle from

Xerox PARC, who experimented [1] on 1GHz computer processor packed with 1018

traditional

logic gates in a volume of 1 cm3operating at a room temperature and found that a huge amount of

power nearly 3MW releases from the surface area of that processor. If IC technology continues

to follow the pattern predicted by the Moore’s Law [2] , it is also estimated that the number of

transistor switches that can be put onto a chip doubles every 18 months. Again energy loss is an

important issue in digital logic design. Loss of energy is due to dissipation of heat from logic

circuit. According to Landauer’s principle [3] [4], a certain amount of energy (KT

Joules/bit) is dissipated in traditional logic computation as heat due to the loss of every bit

of information during the computing process. To encounter these problems, an alternate

technology is needed to design information lossless circuits, which is called is “Reversible logic”

[5]. Bennet postulated [6] [7] that the zero energy dissipation is only possible if the computation

process is reversible under ideal condition. So, it is seen that if a logic circuit can be made

reversible, then it ensures zero heat dissipation [4] and no loss of information characteristics.

Reversible logic has applications in the several emerging technologies like ultra low power

CMOS design, optical computing [8] , nanotechnology [1] and DNA computing [3]. Design of

the reversible carry-look-ahead adder using control gate and its physical implementation have

been first reported in [9] where the circuit is powered by their input signals only and does not

need any additional power supplies.

Recently, the researchers are aiming at the development of the optical digital computer

system for processing binary data using optical computation. Photons are the source of optical

technology. This photonic particle provides unmatched speed with information as it has the

speed of light. The installation of optical components in the electronic computer system produces

optical-electronic hybrid network. The researchers are trying to combine the optical

interconnects with the electronic computing devices.

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The implementation of reversible logic circuits with optical technology can be performed

using Semiconductor Optical Amplifier (SOA) based Mach-Zehnder Interferometer (MZI)

switches which has significant advantages of the high speed, low power, fast switching time and

ease of fabrication [10] [11].Research into this field has also explored new concept and ideas.

Various architectures, algorithms, logical and arithmetic operations have been proposed in the

field of optical/ optoelectronic computing and parallel processing in last few decades. Most of

the all-optical circuits largely depend on digital logic operations as well as switching operations.

Another important issue in reversible logic synthesis is use of ancilla(garbage) [12] lines.

Garbage lines are the extra lines that are needed to realize the given reversible function.

Basically we do not need the garbage information but to achieve reversibility we use the garbage

lines value. Synthesis of reversible logic with minimum number of garbage outputs is an

interesting research problem, which has been studied by many researchers.

The reversible garbage free arithmetic logic unit implementing combined quantum

arithmetic and logical operation in a single unit is presented in [13]. Design of single ancillary

qubit based linear-depth quantum adder circuit that performs ripple-carry addition is presented in

[14]. An optimized architecture of reversible BCD adder is demonstrated in [15]. In this design,

minimum number of ancilla inputs and garbage output lines has been used to design the adder.

The optical computing concept in design and synthesis of reversible logic circuit has first been

introduced in [16]. Generalized implementation of reversible gate like Toffoli, Fredkin, and

CNOT using optical technology has been reported in [12], where Mach–Zehnder interferometer

(MZI) is used to implement all-optical reversible logic gates. Reversible implementation of NOR

gate using SOA based MZI switches is realized in [10]. The optical implementation of

functionally reversible Mach-Zehnder Interferometer based binary adder has been proposed in

[16], where two new optical reversible gates ORG-I and ORG-II have been proposed in addition

to existing Feynman gate to implement the architecture. The implementation of All-optical XOR

gate using SOA-based MZI and micro resonators has been reported in [17] and [18],

respectively. Apart from use of MZI to design reversible gates, TOAD (terahertz optical

asymmetric de-multiplexer)-based and all-optical fiber-based implementation of Fredkin gate is

presented in [19] and [20], respectively.

In the initial phase of the reversible logic circuit design, the researchers have primarily

focused on the design and implementation of the reversible combinational circuits because the

researchers have predicted that the feedback is not allowed in reversible computing. However,

based on his fundamental work reported in [5], Toffoli argued that “a sequential network is

reversible if its combinational part (i.e., the combinational network obtained by deleting the

delay elements) is reversible” i.e. feedback can be allowed in the reversible computing. The first

design of the reversible sequential circuit with JK latch having the feedback loop from the output

has been presented by Fredkin in [21]. Further, Rice has also proved in [22] that the sequential

reversible networks are also reversible in nature.

The necessity for the sequential reversible logic is discussed by Toffoli [5] and Frank

[23], but any structure for its realization has not been presented. The first realization of

sequential element in the form of a JK flip-flop using conservative logic has been proposed by

Fredkin and Toffoli [21]. Picton has presented a reversible RS-latch in [24]. But Picton's model

8 | P a g e

faces one problem that this model cannot avoid fan-out problem which is essential property of

the reversibility.

This fan-out problem of Picton's model [24] has been solved by Rice [22] in 2006. In

[22], Rice has implemented reversible RS latch. Recently, Rice [25] has analyzed the design of

the reversible RS latch in details. The work proposed in [26] has shown that how transistor can

be used to design reversible sequential circuit from the physical implementation point of view.

1.2. Scope and Organization of the Thesis

We address implementation and synthesis of reversible logic using MZI switches. The

contents of the remaining chapters are summarized below. In chapter 2 we have given a brief

introduction on reversible logic that contains semiconductor based amplifier based(SOA-based)

MZI architecture, beam splitter(BS) and beam combiner(BC), metrics to calculate optimization

that is optical delay and optical cost and design of reversible gate using MZI switch. A brief

review of the design and implementation of circuits in optical domain has been presented in

chapter 3. Chapter 4 deals with design and implementation of all optical reversible CLA using

MZI switches. Chapter 5, chapter 6 and chapter 7 present designing of various sequential

elements in optical domain using MZI switches. A glimpse on future work and conclusion has

been presented in chapter 8. 1.2.1 Preliminaries on Reversible Family

Chapter 2 presents the basic definitions of the thesis. In this chapter, the definitions of

reversible logic circuit, reversible gates, metrics to calculate optimization that is optical delay

and optical cost are introduced.

1.2.2 Literature Survey

Chapter 3 presents literature overview of the thesis. In this chapter we described different

ways of designing and implementing of optical circuits with the help of functionally reversible

Mach-Zehnder Interferometer. Here we discussed various design of different adders in quantum

and optical domain. Then various approaches have discussed to make these circuits in reversible

domain. Thereafter designing and implementing of different memory elements (sequential

elements) in optical domain and their improvements in many aspects by various researchers is

described.

1.2.3 Design and Implementaion of Reversible Logic Circuits

In chapter 4 an efficient reversible implementation of Carry-Lookahead Adder (CLA) in

all-optical domain using MZI switches is presented. To approaches (hierarchical approach and

non-modular staircase approach) are proposed for designing the CLA circuit. Experimental result

shows that the optical cost and delay incurred in staircase structured reversible implementation

of CLA are much less than those proposed in the recently reported works.

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In chapter 5, a reversible implementation of all optical based Flip-Flops using Mach-

Zehnder Interferometer (MZI) switches is described. Flip-Flops acts as an important element for

reversible sequential circuit design. The Flip-Flops that are designed using Mach-Zehnder

Interferometer (MZI) switches are RS Flip-Flop, D Flip-Flop, JK Flip-Flop, T Flip-Flop and

Master-Slave Flip-Flop.

In chapter 6 all optical reversible implementation of sequential counters using

semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) switches is

described. All the designs are implemented using minimum number of MZI switches and

garbage outputs. This proposed design can be generalized for n-bit counter also.

In chapter 7 optical implementation of universal shift register using Mach-Zehnder

interferometers (MZIs) is presented. In this design four typical shift registers is used to construct

this shift register. To reduce the design complexity, we have used minimum numbers of MZIs,

beam combiners and beam splitters and also our design confirms zero overhead in terms of

number of ancilla inputs and garbage outputs.

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Chapter 2

Preliminaries:

2.1. Reversibility

A fan-out free circuit (Cnf) with circuit depth (d) over the set of input lines X ={ x1, x2,

…,xn} is said to be reversible (Rc) if the mapping from input to output is bijective (f : Bm→ B

n)

and the number of inputs (m) is equal to number of outputs (n) i.e m = n and also the circuit

consists of reversible gates (gi) only i.e. Cnf = g0 .g1.g2 . … .g(d-1), where gi represents ith

reversible

gate of the circuit.

2.2. Semiconductor Optical Amplifier

Semiconductor optical amplifiers (SOA) are amplifiers which use a semiconductor to

provide the gain medium. SOA is basically a laser diode (LD). The incident light is amplified

through stimulated emission. Mirrors are absent so no feedback from its input and output. The

schematic diagram of SOA is shown in figure below.

The input signal comes from either fiber then passed through the active region which is

pumped by external current injection and then transmits through the fiber. Only to get the

Figure 2(a) : Schematic Diagram of SOA

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amplification function the device must be protected from the self oscillations generating the laser

effect. In1-xGaxAsyP1-y/InP quaternary alloys emitting in the near infrared spectral region acts as

active layers in semiconductor laser diodes, photo detectors, optical amplifiers and modulators

for telecommunication applications. Semiconductor optical amplifiers have five basic

parameters. These are i) Gain (Gs), ii) Gain Bandwidth, iii) High saturation output power (Psat),

v) Noise figure (NF), v) Polarization dependent gain (PDG). It should have highest gain because

it amplifies input light through stimulated emission. The optical gain depends on the frequency

or wavelength of incident signal. Effective amplifier has an additional dependency on the

intensity of local beam at any point inside the amplifier. High optical non-linearity makes

semiconductor attractive for all optical signal processing (all optical switching, wave conversion)

so, very high saturation output power is required to achieve linearity. This is an important

criterion of an ideal SOA. Amplifier noise figure is a key consideration for amplification

application. For optical communication system, an optical amplifier should have amplifier noise

figure as low as possible. It is depends on operating wavelength, operating current and input

signal power range (6-10 dB). Gain of an SOA is dependent on the polarization of input light

which is dependent on the local temperature and stress on the fiber. It should be very low

polarization sensitivity to minimize the gain difference between the transverse electric mode

(TE, i.e. light passing with polarization parallel to the junction plane) and Transverse magnetic

mode (TM, i.e. light passing with polarization perpendicular to the junction plane). In optical

networking system the SOA is recommended as an important technology for amplification,

wavelength conversion, switching and all optical regeneration of signals. The wavelength

conversion can be accomplished by either Cross Gain Modulation (XGM) or Cross Phase

Modulation (XPM) or by Four Wave Mixing (FWM). All the process can be exploited with the

application of SOA due to its high speed, high extinction ratio and also high integration

potential. Optical switches can be constructed using SOA. The advantage of SOA gate is that

they can be integrated monolithically on a substrate to form gate arrays. Injected current will

control the SOA gate. When injected current is high, SOA allows signal light with some

amplification but when the injected current is near to zero the device blocks the signal.

Therefore, SOA can be used as an optical switch.

A semiconductor optical amplifier (SOA) is also an attractive switching device because

of its compactness, high stability, and low switching power. One difficulty with SOA is the

operating speed, which is limited by the slow gain recovery time of about 100 ps. It has been

found that the SOA response can be improved by installing a detuned optical filter at the SOA

output so that the slow gain recovery components can be removed. This scheme has been applied

to 640 to 40 Gbit/s demultiplexing. However, the switching performance includes a large penalty

because of the distortions in the switching gate induced by residual slow recovery components

and the excessive loss caused by the optical filtering.

2.3. MZI Architecture

Design of reversible logic gates like NOT, k-CNOT, Toffoli, Fredkin, Peres gates is

possible in many ways. Among them, the quantum and optical technology are two very

prominent implementation mediums. From the quantum technology point of view, the basic

quantum gates such as NOT, CNOT, V and V+ are used to design reversible gates. In optical

technology, MZI based optical switches are used to implement reversible gates. An optical MZI

12 | P a g e

switch can be designed [17] using two Semiconductor Optical Amplifiers (SOA-1, SOA-2) and

two couplers (C-1, C-2) as shown in Figure 2(b). MZI switch has two inputs ports namely, A and

B and two output ports called as bar port and cross port, respectively. The optical signals coming

at port B and port A at the input side are control signal (λ2), and incoming signal (λ1),

respectively. The working principle of a MZI is explained as follows:

When there is a presence of incoming signal at port A and control signal at port B, then a

light would appear at the output bar port and no light would appear at the output cross port.

Again on absence of control signal at input port B and presence of incoming signal at input port

A, the light would appear at the output cross port and no light would appear at the output bar

port.

The logic value of the absence of light and presence of light is denoted by 0 and 1,

respectively. From the point of view of boolean function, the above behavior of MZI switch can

be written as P (Bar Port) =A.B and Q (Cross Port) =A .

2.3.1. Optical cost and delay

As the optical cost of BS and BC are relatively small, the optical cost of a given circuit is

the number of MZI switches required to design the realization. The optical delay is estimated as

the number of stages of MZI switches multiplied by a unit Δ.

2.3.2. Beam Combiner(BC) and Beam Splitter(BS)

Beam combiner (BC) simply combines the optical beams while the beam splitter (BS)

splits the beams into two optical beams. The optical cost and the delay of beam combiner and

beam splitter are negligible [10] [15] and while calculating optical cost of a circuit, it may be

assumed as zero.

In the schematic diagram of various circuits in section 3, the beam combiner (BC) and

beam splitter (BS) are represented by hollow bubble () and solid bubble () respectively.

2.3.3. Ancilla Lines

There are !distinct reversible functions on n variables which are permutations for

elements. However,

irreversible multiple-output (from 1 to n) functions exist.

To make the specification reversible, input/output should be added. The added lines are called

ancillae and typically start out with the 0 or 1 constant. An ancilla line whose value is not reset

to a constant at the end of the computation is called a garbage line.

SOA-1

SOA-2

C-2 C-1

Incoming Signal (λ1)

Control Signal (λ2)

Bar Port (P) =A.B

Cross Port (P) = A

A

B

Figure 2(b): Semiconductor Optical Amplifier based MZI Switch

13 | P a g e

2.4. Design of Reversible Gates with MZI

The Feynman gate (FG) is a 2 inputs and 2 outputs reversible gate where the light from input A

is incident on beam splitter (BS) and is split into two parts as shown in Fig. 2(a). One part enters

into MZI-1 and acts as control signal; where as other light beam is incident on MZI-2 and acts as

incoming signal. In the similar way, the light signal from input B is connected to MZI-1 and

MZI-2 as shown in Fig. 2(a). The light from bar port of MZI-1 (B1), MZI-2 (B2) and a part of

light from the cross port of MZI-2 (C2) are combined by BC-1 to get the final output P. The light

from cross port of MZI-1 (C1) and MZI-2 (C2) are combined by BC-2 to get the final output Q

that complements the value appeared at port B only when the input signal A=1. MZI-based

optical design of reversible Toffoli gate is depicted in Fig. 2(d). Standard optical costs and delay

ratings [15] of few reversible gates benchmarks are presented in Table-I

Table I : Optical Cost and Delay of Reversible Gates [15]

No. of

MZI

No. of BS No. of

BC

Optical

Cost

Delay

Feynman gate 2 3 2 2 Δ

Peres gate 4 5 3 4 2Δ

Fredkin gate 2 1 2 2 Δ

Toffoli gate 3 4 1 3 2Δ

n-controlled Toffoli

gate

n+1 n+2 1 n+1

(

Δ

Reversible

Gates

Cost Metrics

Figure 2(d) : MZI based optical implementation of Toffoli gate

M

Z

I

M

Z

I

M

Z

I B

C

BS1

BS2

BS4

BS3

A

B

P=A

Q= B

R=AB⨁C

C

BS3

M

Z

I

M

Z

I

B

C

B

C

BS1

BS2

P=A

Q=A⨁B

A

B

MZI-1

MZI-2

B2

B1

C2

C1

Figure 2(c): MZI based optical implementation of Feynman gate

14 | P a g e

Chapter 3

Review on Reversible Logic Synthesis In reversible circuits there exist a one-to-one mapping between the inputs and the outputs

resulting in no loss of information. In recent years, reversible logic has emerged as a promising

computing paradigm having application in low-power CMOS, quantum computing,

nanotechnology and optical computing. Researchers have implemented reversible logic gates in

optical computing domain as it can provide high speed and low energy requirement along with

easy fabrication at the chip level. The all optical implementation of reversible gates are based on

semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) due to its

significant advantages such as high speed, low power, fast switching time and ease in

fabrication. Optical logic gates have the potential to work at macroscopic (light pulses carry

information), or quantum (single photons carry information) levels with great efficiency.

However, relatively little has been published on designing reversible logic circuits in all-optical

domain.

The sequential circuit is one of the most important components of the computer system

and the efficient of the memory element is a primary concern in this circuit. As the reversible

circuit promises information lossless and no heat generation property, an intensive research is

going on design and implementation of the sequential circuit using reversible technology.

In the initial phase of the reversible logic circuit design, the researchers have primarily

focused on the design and implementation of the reversible combinational circuits because the

researchers have predicted that the feedback is not allowed in reversible computing. However,

based on his fundamental work reported in [5], Toffoli argued that feedback can be allowed in

the reversible computing.

Thomsen et al. [13] presents the complete design of a reversible arithmetic logic unit

(ALU) that can be part of a programmable reversible computing device such as a

quantum computer. The presented ALU is garbage free and uses reversible updates to

combine the standard reversible arithmetic and logical operations in one unit. Combined

with a suitable control unit, the ALU permits the construction of an r-Turing complete

computing device. The garbage-free ALU developed in this communication requires only

6n elementary reversible gates for five basic arithmetic–logical operations on two n-bit

15 | P a g e

operands and does not use ancillae. This remarkable low resource consumption was

achieved by generalizing the V-shape design first introduced for quantum ripple-carry

adders and nesting multiple V-shapes in a novel integrated design. This communication

shows that the realization of an efficient reversible ALU for a programmable computing

device is possible and that the V-shape design is a very versatile approach to the design

of quantum networks.

The all optical implementation of an n bit reversible ripple carry adder proposed by

Kotiyal et al. [16]. The all optical reversible adder design is based on two new optical

reversible gates referred as optical reversible gate I (ORG-I) and optical reversible gate II

(ORG-II) and the existing all optical Feynman gate. The two new reversible gates ORG-I

and ORGII are proposed as they can implement a reversible adder with reduced optical

cost which is the measure of number of MZIs switches and the propagation delay, and

with zero overhead in terms of number of ancilla inputs and the garbage outputs. The

proposed all optical reversible ripple carry adder will be a key component of an all

optical reversible ALU that can be applied in a wide variety of optical signal processing

applications.

Thapiyal et al. [15] presented a new design of the reversible BCD adder that has been

primarily optimized for the number of ancilla input bits and the number of garbage

outputs. The number of ancilla input bits and the garbage outputs is primarily considered

as an optimization criteria as it is extremely difficult to realize a quantum computer with

many qubits. Firstly, we propose a new design of the reversible ripple carry adder having

the input carry C0 and is designed with no ancilla input bits. The proposed reversible

ripple carry adder design with no ancilla input bits has less quantum cost and the logic

depth (delay) compared to its existing counterparts. The existing reversible Peres gate

and a new reversible gate called the TR gate is efficiently utilized to improve the

quantum cost and the delay of the reversible ripple carry adder. The improved quantum

design of the TR gate is also illustrated. Finally, the reversible design of the BCD adder is

presented which is based on a 4 bit reversible binary adder to add the BCD number, and

finally the conversion of the binary result to the BCD format using a reversible binary to

BCD converter.

Taraphdara et. al. [10] proposed and designed a novel scheme of Toffoli and Feynman

gates in all-optical domain. Authors described their principle of operations and used a

theoretical model to assist this task, finally confirming through numerical simulations.

Semiconductor optical amplifier (SOA)-based Mach–Zehnder interferometer (MZI) can

play a significant role in this field of ultra-fast all-optical signal processing. The all-

optical reversible circuits presented in this paper will be useful to perform different

arithmetic (full adder, BCD adder) and logical (realization of Boolean function)

operations in the domain of reversible logic-based information processing.

Poustite et. al. [19] demonstrate experimentally an all-optical Fredkin gate that allows

the implementation of reversible optical logic. An actual experimental implementation of

a digital all-optical Fredkin gate is described. The gate is based on the terahertz optical

asymmetric demultiplexer (TOAD) that comprises a nonlinear loop mirror with a

semiconductor optical amplifier (SOA) as the nonlinear element. The SOA is temporally

16 | P a g e

displaced from the loop centre to create a switching window in time in which a control

pulse (via port C) can reduce the gain of the SOA.

Zhang et. al. [17] proposed the performance of ultra-fast all-optical XOR gate using two

types semiconductor optical amplifier-based Mach–Zehnder interferometers (SOA-

MZIs). Key parameters are optimized through numerical simulations. With properly

designed parameters, 40 Gb/s all-optical XOR gate using SOA-MZI can be realized with

fairly high performance. The results are helpful for parameter design of SOA-MZI-based

XOR gate.

Rice [22] has introduced an analysis of a basic memory element, the RS-latch, and a

number of possible implementations. Although many researchers are investigating

techniques to synthesize reversible combinational logic, there is little work in the area of

sequential reversible logic. Here four reversible flip-flops has designed based on the

reversible RS-latch implementation.

Picton [24] shows how Fredkin gates can be used to construct latches and flip-flops for

conventional Boolean logic and then extends the ideas to multivalued logic. Recent

research has shown that a modified form of Fredkin gate can be used to design any multi-

valued combinational logic system. In order to be of more general use, it should also be

able to implement sequential logic systems.

Rice [25] introduces the details behind two proposed reversible SR latch designs: one

design based on the Fredkin gate and one design based on the Toffoli gate. A novel idea

of designing circuits that can be operated or driven, both forwards and in reverse is

introduced, AND that can compute different functions in each of these directions. In

relation to this idea the reverse behaviour of the Toffoli and Fredkin SR latch designs are

characterized. One of designed structures has similar behaviour to that of a D latch when

driven in reverse. This opens up the possibility of designing a circuit that can carry out

two separate actions: one action to be performed when the circuit is driven forward, and a

different action to be performed when the circuit is driven in reverse.

Toffoli [5] has first proposed that it is ideally possible to build sequential circuits with

zero internal power dissipation. Even when these circuits are interfaced with conventional

ones, power dissipation at the interface would be at most propositional to the number of

input/output lines, rather the number of logic gates as in conventional logic. The theory of

reversible computing is based on invertible primitives and composition rules that

preserve invertibility. With these constraints, one can still satisfactorily deal with both

functional and structural aspects of computing processes; at the same time, one attains a

closer correspondence between the behavior of abstract computing systems and the

microscopic physical laws (which are presumed to be strictly reversible) that underlie any

concrete implementation of such systems.

Frank [23] has reviewed the physical and architectural requirements that must be met if

real machines are to break through the barriers preventing further progress, and approach

the true fundamental physical limits to computing. As logic device sizes shrink towards

the nanometer scale, a number of important physical limits threaten to soon halt further

17 | P a g e

improvements in computer performance per unit cost. However, the near-term limits are

not truly fundamental, and may be avoided by making radical changes to the physical and

logical architecture of computers. In particular, certain assumed limits to the energy

efficiency of computers have never been rigorously proven, and may be circumvented

using physical mechanisms that recover and reuse signal energies with efficiency

approaching 100%.

18 | P a g e

All Optical Implementation of Mach-Zehnder Interferometer based Reversible CLA circuit

19 | P a g e

Chapter 4

MZI-based All Optical Reversible CLA Circuit

4.1. Introduction

In this work, we present an efficient reversible implementation of Carry-Lookahead

Adder (CLA) in all-optical domain. Now-a-days, semiconductor optical amplifier (SOA)-based

Mach–Zehnder interferometer (MZI) plays a vital role in the field of ultra-fast all-optical signal

processing. We have used all optical based Mach-Zehnder Interferometer (MZI) switches to

design the CLA circuit implementing reversible functionality. Two approaches are proposed for

designing the CLA circuit. First, we propose a hierarchical approach for implementation of 2n-

bit reversible CLA. In the second approach, we remove the drawback of hierarchical CLA and

improve the design by implementing non-modular staircase structure of n-bit reversible CLA.

The design complexities of both the approaches are computed. Experimental result shows that

the optical cost and delay incurred in staircase structured reversible implementation of CLA are

much less than those proposed in the recently reported works.

4.2. Proposed Technique

We present all optical reversible implementation of carry look-ahead adder with the

property of functional reversibility using Mach-Zehnder Interferometer (MZI) switches. We have

proposed two design techniques of CLA: - one is hierarchical implementation and another is non

modular staircase structured implementation. In hierarchical implementation, a generalised

design of all optical reversible CLA using SOA-based MZI switches is presented. Improve

design of reversible CLA is introduced in staircase structured implementation. These techniques

are discussed here in details.

20 | P a g e

4.3. Hierarchical Design of 2n –bit CLA

This design is divided in two phases. In initial phase, we design an optimized 4-bit CLA

circuit and consider this 4-bit design as basic building block. Integrating several small 4-bit CLA

blocks in a hierarchical way, a 2n-bit CLA circuit is constructed.

4.3.1. Optimized 4-bit CLA Design with MZI

A reversible full adder circuit implemented with 4 MZI switches, 4 beam splitters (BS)

and 3 beam combiners (BC) as shown in Fig. 3(a). In this figure, apart from sum (S0) and carry

(C1), we define two extra variables: - carry generator (Gi) and carry propagator (Pi), where Gi =

ai.bi and Pi =ai bi. The carry generator (Gi) generates output carry when the bit values of both

the input namely, ai and bi are set to one, where the carry propagator (Pi) helps to propagate the

carry from Ci to Ci+1. The output sum (S0) and carry (C1) are expressed as Si = Pi Ci and Ci+1 =

Gi + PiCi.

The optimized design of 4-bit CLA circuit using MZI switches is shown in Fig. 3(b). This

circuit consists of four full adder circuits shown by the dotted box [Fig. 3(b)]. In Carry Look-

ahead adder, there are two blocks: - one is carry generator block, and another is carry

propagator block. The inputs to the 4 bit CLA are A (a3a2a1a0), B (b3b2b1b0) and the input signal

(c0) that acts as input carry. This 4 bit CLA performs addition of two four bit binary numbers.

Outputs from the CLA are sum (S) and carry (C).

We deduce the following relations.

S0 = P0 C0, where P0 =a0 b0 and C0=c0

c0

c0

b0

b0

a0

a0

c0

c0

S0

S0

C0

C0

G0

G0

P0

P0

MZI

MZI

MZI

MZI

MZI

MZI

MZI

MZI

Figure 4(b): 4-bit Optical Reversible Full Adder Circuit

Figure 4(a): Full adder circuit using MZI Switches

a1

a1

a2

a2

b2

b2

G3

G4

Full

Adder

Full

Adder

S0

S0

c0

c0

G0

G0

P0

P0

MZI

MZI

MZI

MZI

a0

a0

b0

b0

MZI

MZI

MZI

MZI

c0

c0

C1

C1

C1

C1

C4

C3

S3

S3

P3

P3

C3

C3

a3

a3

b3

b3

MZI

MZI

MZI

MZI

C3

C3

P1

P1

G1

G1

S2

S2

P2

P2

G2

G2

C2

C2

MZI

MZI

MZI

MZI

C2

C2

S1

S0

b1

b1

MZI

MZI

MZI

MZI

MZI

MZI

MZI

MZI

MZI

MZI

MZI

MZI

MZI

MZI

MZI

MZI

21 | P a g e

S1 = P1 C1, where P1 =a1 b1 and C1 = G0 + P0C0

S2 = P2 C2, where P2 =a2 b2 and C2 = G1 + P1C1

S3 = P3 C3, where P3 =a3 b3 and C3 = G2 + P2C2 .

4.3.2. Optimized 2n –bit CLA Design with MZI

We integrate several 4-bit CLA in a hierarchical way to design a 2n-bit CLA circuit. In

this hierarchical structure, we use two parameters namely, group generate and group propagate

functions. For example, a 16-bit carry look-ahead adder requires four 4-bit CLA modules and

one additional 4-bit look-ahead block. The additional look-ahead block compute carry bits based

on received group generate and group propagate values. Among the five 4-bit CLA modules,

four CLA blocks are identical in the sense that they compute group generate and group

propagate values but the fifth one does not. For a 4-bit CLA block, the group generate and

group propagate functions are labelled as G0-3 and P0-3, respectively. The group generate and

group propagate functions are defined as:-

G0-3= G3+G2P3+G1P2P3+G0P1P2P3

P0-3 = P0P1P2P3.

The 16-bit CLA is designed using 4-bit CLA module in hierarchical manner. In this way,

we can construct higher order 2n-bit CLA circuit using multiple 4-bit look-ahead blocks.

Example, 64-bit CLA is constructed by four 16-bit CLA and a 4-bit look-ahead block i.e. twenty-

one 4-bit look-ahead block is required. Mathematically, we compute the expression for number

of 4-bit look-ahead blocks required to design 2n-bit CLA as follows.

Number of 4-bit CLA Blocks = (2n/4 no. of 4-bit blocks) + (no. of 4-bit look-ahead

blocks to design 2n-2-bit CLA).

Case 1: Number of MZI switches to design 4-bit CLA

16 number of MZI switches is required to design a 4 bit CLA is shown in Fig. 3(b).

Hence, the optical cost of 4 bit CLA is 16.

Case 2: Number of MZI switches to design 4i+1-bit CLA

To design a 2n-bit CLA circuit, where i ≥ 1 and 2

n = 4

i+1, total number of MZI is

computed as follows.

Total number of MZI switches= Optical Cost= (4*(Number of MZI required for 4i-bit CLA circuit) + 18i +3) where n represents number of bits and i is a positive integer indicating order index value.

Example 1: Calculate the total number of required MZI to implement 16-bit (2n = 16) CLA

circuit. First we compute the order index value i as given below.

4i+1

=16, as 2

n =4

i+1

=>4i+1

=42

=>i+1=2

=>i=1

22 | P a g e

Hence, the order index’s value i for 16-bit CLA is 1. So, number of MZI required in 16-bit CLA

circuit in hierarchical design =(4*(No. of MZI for 4i-bit CLA circuit) + 18i +3)

= (4*(Number of MZI required to design 41 -bit CLA circuit) + 18*1 +3)

= (4*(Number of MZI required to design 4 -bit CLA circuit) + 21)

= ((4* 16) +21)= 85

We have already calculated the required number of MZI to design hierarchical m-bit

CLA circuit, where m is the order of 4. But when we are designing an m-bit CLA circuit, where

m ∈ {{2j}-{ 2/

4j }} or say m ∈ 2

j but m 2/

4j and j ≥2 (like m=8 or 32), then we will compute

the required no. of MZI as well as optical cost for m-bit CLA circuit using the following formula.

For a hierarchical design of 2*4i-bit CLA circuit, the required no. of MZI = (2*(Number of MZI

required designing a 4i-bit CLA circuit) + 6i +3).

Addition of extra six

MZI switch to

generate group

generate and group

propagate values

C1

C2

C3

C4 S0 S1 S2 S3

P0-3 G0-3

G0 P1

G2 P2 P3 G3 P3 G2 G1 G0

P3 P2 P1 P0

P1P2P3 P2P3

c0

MZI

MZI

MZI

C3

MZI

MZI

MZI

MZI

MZI MZI

MZI

MZI

C1 C2 c0

MZI

MZI

MZI

a0 b0 a1 b1 a2 b2 a3 b3

MZI

MZI MZI

MZI MZI

MZI MZI

MZI

Figure 4(c): 4-bit CLA circuit with Group Generates and Group Propagates values.

23 | P a g e

Though we have seen two different expressions for calculating optical cost (no. of MZI)

of a 2n-bit CLA, but the optical delay is constant for the 2

n-bit CLA, that is (2

n +1) Δ.

But there are some limitations in this hierarchical design. When the number of bits to be

added are very large (2n>64) then the design requires more number of MZI than the earlier

reported designs as shown in the Table-I. The numbers of MZI increases due to the propagation

of group generate and group propagate values in circuit. To generate one group generate and

one group propagate value, we require 6 extra MZI switches as shown Fig. 3(d) marked by

dotted box. In a 16-bit CLA circuit, we have required three group generate(G0-3,G4-7,G8-11) and

three group propagate values(P0-3,P4-7,P8-11). Hence to implement 16-bit CLA circuit in

hierarchical manner, additional (3*6) or 18 MZI switches are required. Again, when we

implement higher order (2n bit, where n>=7) CLA circuit, then the requirement of number of

MZI switches is more than the desired requirement as mentioned in Table-I. This problem is

overcome by an improved design of CLA, which is described in next section.

4.4. Improved Staircase Design of n–bit CLA

In the hierarchical method, the number of MZI switches increases due to the presence of

group generates and group propagate functions. To overcome this, we propose an improved n-

bit CLA circuit that ensures use of minimum number MZI along with optimized delay. In this

approach, we remove the concept of group generate and group propagate function and presents

a staircase structure of n-bit CLA circuit.

We consider two n-bit binary numbers, A(an-1an-2...a2a1a0) and B(bn-1bn-2...b2b1b0) to be

added using a n-bit improved carry look ahead adder, where Si and Ci are the output sum and

carry of ith input bits, respectively. Then, S0 = P0C0, where P0 =a0b0 as C0=c0=0.

Hence the modified value of S0 is:

S0= P00= P0 S1 = P1C1, where P1 =a1b1 and C1 = G0 + P0C0.

As C0=c0=0, hence the modified value of C1 is: C1 = G0 +0 =G0

S2 = P2C2, where P2 =a2b2 and C2 = G1 + P1C1 ... ... ... Sn-2=Pn-2Cn-2, where Pn-2 =an-2bn-2 and Cn-2=Gn-3 + Pn-3Cn-3

Sn-1=Pn-1Cn-1, where Pn-1 =an-1bn-1 and Cn-1=Gn-2 + Pn-2Cn-2

The improved design of n-bit CLA circuit is depicted in Fig. 4(d).

4.4.1. Calculation of Optical Cost

To add two single bit numbers using improved staircase design of CLA circuit, 2 MZI

switches are required to generate Gi and Pi as shown in Fig. 4. To add two n-bit numbers, n

number of Gi and Pi is required. Therefore to generate n number of Gi and Pi, total 2n number of

MZI switches is required. Again additional (n-1) carry bits are required to add two n-bit

24 | P a g e

numbers and for each carry bit, 2 MZI switches are required. The required total number of MZI

switches for (n-1) carry bits are (2*(n-1)). Therefore, total (2n + (2*(n-1))) or (4n-2) number of

MZI switches are required to implement an n-bit CLA circuit. Hence the optical cost of an

improved n-bit CLA circuit is (4n-2).

4.4.2. Calculation of Optical Delay

In an improved staircase structured n-bit CLA circuit, n number of Gi , Pi and (n-1)

number of carry bits {C1, C2, C3 ….Cn-1} are generated, where i∈ {0, 1, 2,…, n-1}. The values

of Gi and Pi depend only on the values of input bits to be added, as Gi = ai.bi and Pi =ai ⨁ bi,

where ai and bi are the input bits. As we get all the input bits at the same time, hence all the

values of Gi and Pi are calculated

A comparison of optical cost and delay of improved staircase structured n-bit CLA circuit with

earlier recent works on adder circuits is presented in Table-II. Experimental result shows that our

design of improved CLA circuit is much more efficient than the adders presented in [13], [14],

[15], [16]. This design is efficient not only in terms of optical cost but also in terms of optical

delay.

S0

Total no. of MZI = 2xn + (n-1)x2

= 4n-2

Total optical delay = 1Δ+(n-1)Δ

= nΔ

Optical

Delay

1Δ

1Δ

1Δ

1Δ

1Δ

No. of

MZI

(2xn)

2

2

2

(n-1)

terms

2

P0 G1 P1 G2 P2

C2

Pn-2 Gn-2

Cn-2

Cn-1

Gn-1 Pn-1

S1 S2 Sn-2 Sn-1

MZI MZI

MZI MZI

a0 b0

MZI MZI

a1 b1

MZI MZI

a2 b2

MZI MZI

MZI MZI

an-2

n-2

bn-2

MZI MZI

MZI MZI

an-1 bn-1

MZI MZI

G0

C1 C2 C3 Cn-1 Cn

Figure 4(d): Improved staircase structured n-bit CLA circuit

25 | P a g e

Table II: Optical cost and Optical delay comparison

4.5. Conclusion

In this work, we have presented an efficient all optical implementation of reversible CLA

using semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI)

switches. The proposed design has zero overhead in terms of number of ancilla inputs and

garbage outputs. Design complexities presented ensure improved optical costs and minimum

delay in optical reversible adder circuit realization. Our design technique has been compared

with recently reported design techniques. Experimental result shows that our proposed design

gives better performance compared to all other approaches in terms of optical costs and delay.

Thomsen

et al. [13]

Cuccaro

et al.

design 1

[14]

Cuccaro

et al.

design2

[14]

Thalpiyal et

al. [15]

Kotiyal et

al. [16]

Proposed design

of CLA circuit

Improved

staircase structure

Ancilla

input

0 0 0 0 0 0

Garbage

output

0 0 0 0 0 0

Optical

cost

8n-8 18n-19 18n-8 19n-5 6n+2 4n-2

Delay Δ 3n+2 4n+5 4n+1 4n+4 3n+1 n

26 | P a g e

All Optical Implementation of Different Sequential

Elements using MZI Switches

27 | P a g e

Chapter 5

All Optical Implementation of Mach-Zehnder Interferometer based Reversible Flip-Flop

5.1. Introduction

In this work, we present all optical reversible implementation of Flip-Flops using semiconductor

optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) switches. Improved design of

MZI-based functionally reversible RS, D, JK, T and three different implementations of all optical

functionally reversible MZI-based Master-Slave Flip-Flop using RS, D and JK Flip-Flop are

presented. Detailed analysis and design complexities of all the functionally reversible optical

Flip-Flops with improved optical costs have been reported.

5.2. Proposed Method

In this section, we present all optical design of Flip-Flops with the property of functional

reversibility. We have used Semiconductor Optical Amplifier (SOA) based Mach-Zehnder

Interferometer (MZI) switches to design the sequential circuits. Reversible implementation of

Flip-Flops by keeping minimum number of garbage outputs and MZI switches is our main

motivation. All optical design of MZI-based RS Flip-Flop, D Flip-Flop, JK Flip-Flop and T Flip-

Flop has been presented. Three distinct designs of MZI-based reversible Master-Slave Flip-Flop

using RS, D and JK Flip-Flop are presented. Architecture of all the Flip-Flops and detailed

analysis for its design complexities have been illustrated below.

A comparison summary of design complexities of all the Flip-Flops has been presented in

Table-VII. The comparison metrics are the number of MZI switch, number of beam splitter and

number of beam combiner, garbage outputs and optical cost.

28 | P a g e

5.2.1. RS Flip-flop

In this section we propose all optical based reversible circuit design of RS flip flop using Mach-

Zehnder Interferometer (MZI) switches. The conventional circuit design of RS flip flop using

NOR and AND gates is shown in figure 5(a). In our proposed technique, each NOR and AND

gate is replaced with MZI switch focusing minimal garbage outputs and minimum number of

MZI switches. Our proposed design technique of RS flip flop is shown in fig 5(b). The truth

table of D flip flop in table III.

Table III: Truth Table of RS Flip-Flop

CP S R Qn Qn+1 State

1

1

0

0

0

0

0

1

0

1 NC

1

1

0

0

1

1

0

1

0

0 Reset

1

1

1

1

0

0

0

1

1

1 Set

1

1

1

1

1

1

0

1

X

X Invalid

0

0

X

X

X

X

0

1

0

1 NC

(CP: Clock Pulse, NC: No change, Invalid: Indeterminate state)

Invalid: Indeterminate state)

Q

R

S

CP

Figure 5(a): Classical design of RS Flip-Flop

M Z I

M Z I BC

R

S

1

Q

BC

M Z I

M Z I

CP

1

CP

Figure 5(b): RS Flip-Flop (NOR gate) implemented by MZI switch

29 | P a g e

5.2.2. D Flip-flop

In the D flip flop, which is a modification of clocked RS flip flop, the D input goes directly goes

to the S input and complement of D input is applied as R input. The truth table of D flip flop in

table IV. In this section we propose all optical reversible circuit design of positive edge triggered

D flip flop using Mach-Zehnder Interferometer (MZI) switches. The conventional circuit design

of D flip flop which consists of NOR and AND gates are shown in Figure 5(c). Figure 5(d)

shows our proposed design technique of D flip flop using MZI switch focusing minimal garbage

outputs and minimum number of MZI switches.

Table IV: Truth Table of D Flip-Flop

5.2.3. JK Flip-flop

In this section we design all optical based reversible circuit of positive edge triggered JK flip flop

using Mach-Zehnder Interferometer (MZI) switches. The JK flip flop is a versatile and also the

most widely used. Its functionality is identical to RS flip flop expect that it has no invalid state

like that of RS flip flop. Inputs J and K of JK flip flop behave like S and R inputs of RS flip flop,

CP D Qn Qn+1 State

1

1

0

0

0

1

0

0 Reset

1

1

1

1

0

1

1

1 Set

0

0

X

X

0

1

0

1 NC

(CP:Clock Pulse, NC: No change)

BC

CP

1

BC

M Z I

M Z I

M Z I Q

D

1

CP

Q

D

Figure 5(c): Classical design of D Flip-Flop

Figure 5(d): RS Flip-Flop (NOR gate) implemented by MZI switch

30 | P a g e

respectively. Figure 5(e) shows the JK flip flop designed from conventional irreversible

gates(NOR gate and AND gate). The truth table of JK flip flop is shown in table III. Figure 5(f)

shows our proposed design technique of JK flip flop using MZI switch focusing minimal garbage

outputs and minimum number of MZI switches. The truth table of JK flip flop in table V.

Table V: Truth Table of JK Flip-Flop

CP J K Qn Qn+1 State

1

1

0

0

0

0

0

1

0

1 NC

1

1

0

0

1

1

0

1

0

0 Reset

1

1

1

1

0

0

0

1

1

1 Set

1

1

1

1

1

1

0

1

1

0 Toggle

0

0

X

X

X

X

0

1

0

1 NC

(CP: Clock Pulse, NC: No Change)

Figure 5(e): Classical design of JK Flip-Flop

K

J

CP

Q

BC

K

1

BC

J

M Z I

M Z I

CP M Z I

M Z I Q M

Z I

M Z I

CP 1

Figure 5(f): JK Flip-Flop implemented by MZI switch

31 | P a g e

5.2.4. T Flip-flop

In this section we design all optical based reversible circuit of positive edge triggered T flip flop

using Mach-Zehnder Interferometer (MZI) switches. The T flip flop is obtained from JK flip flop

if both the inputs of JK flip flop are tied together and passed the same input signal. Figure 5(g)

shows the T flip flop designed from conventional irreversible gates (NOR gate and AND gate).

The truth table of T flip flop is shown in table VI. Figure 5(h) shows our proposed design

technique of T flip flop using MZI switch focusing minimal garbage outputs and minimum

number of MZI switches.

Table VI: Truth Table of T Flip-Flop

CP T Qn Qn+1 State

1

1

0

0

0

1

0

1 NC

1

1

1

1

0

1

1

0 Toggle

0

0

X

X

0

1

0

1 NC

(CP: Clock Pulse, NC: No Change)

BC

T

1

BC

M Z I CP

M Z I

M Z I Q M

Z I

M Z I

1

Figure 5(h): T Flip-Flop implemented by MZI switch

Q

CP

T

Figure 5(g): Classical design of T Flip-Flop

32 | P a g e

5.2.5. Master Slave Flip-flop

In this section we design all optical based reversible circuit of Master Slave flip flop using Mach-

Zehnder Interferometer (MZI) switches. A master slave flip flop is constructed by two separate

flip-flops, one flip-flop serves as a master and other serves as a slave, and the overall circuit is

referred as master-slave flip-flop. It is basically two gated flip flops connected serially where the

slave section is triggered by an inverted clock pulse. Generally master slave flip flop was

developed using to make synchronous operation more predictable. Three basic types master

slave flip flop in optical domain using MZI is depicted in fig 5(i), 5(j) and 5(k).

BS1

BS2

BS3

BS4

BS5

BS6

BS7

BS8

Master section

BC

CP

BC

M Z I

M Z I

D

M Z I

BC

1

BC

M Z I

M Z I Q

1

M Z I

M Z I

M Z I

Slave section

Figure 5(j): Master Slave D Flip-Flop implemented by MZI switch

BS1

CP M Z

I

M Z

I BC R

S BC

M Z

I

M Z

I

M Z

I

M Z

I BC

1

Q

BC

M Z

I

M Z

I

M Z

I

1

CP

Master section

Slave section

BS2

BS3

BS4

BS5

BS6

BS7

BS8

BS9

BS10

Figure 5(i): Master-Slave RS Flip-Flop implemented by MZI switch

33 | P a g e

5.3. Conclusion

In this work, we have presented MZI based all optical reversible design of Flip-Flops. Designs

complexities have been presented that ensure improved optical costs in optical sequential circuit

realization. All the designs of functionally reversible Flip-Flops have been made by keeping the

usage of MZI level minimum.

Table VII: Relative Comparison table of Flip-Flops

Type of Flip-flops No. of MZI

switches

No. of

beam

splitter

No. of beam

combiner

No. of

Garbage

Output

Optical

Cost

RS flip-flop 4 4 2 4 4

D flip-flop 3 3 2 2 3

JK flip-flop 6 4 2 6 6

T flip-flop 5 5 2 5 5

Master-Slave RS-

Flip-Flop 9 10 4 8 9

Master-Slave D -

Flip-Flop 8 8 4 6 8

Master-Slave JK-

Flip-Flop 11 8 4 10 11

M Z I

M Z I

BC

K

BC

J

M Z I

M Z I

CP

M Z I

M Z I

M Z I

M Z I

BC

1

BC

M Z I

M Z I Q

M Z I

1

CP

Slave section

Master section

BS2

BS1

BS3

BS4

BS5

BS6

BS7

BS8

BS9

Figure 5(k): Master Slave JK Flip-Flop implemented by MZI switch

34 | P a g e

Chapter 6

All Optical Implementation of Mach-Zehnder Interferometer based Reversible Sequential Counters

6.1. Introduction

This work presents all optical reversible implementation of sequential counters using

semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) switches. All

the designs are implemented using minimum number of MZI switches and garbage outputs. This

design ensures improved optical costs in reversible realization of all the counter circuits. The

theoretical model is simulated to verify the functionality of the circuits. Design complexity of all

the proposed memory elements has been analyzed.

6.2. Proposed Work

In this section, we present all optical implementation of counters with the property of

functional reversibility. Semiconductor Optical Amplifier (SOA) based Mach-Zehnder

Interferometer (MZI) switches are used to design the sequential circuits. Our primary objective

in this work is to achieve the reversible implementation of counters with minimum number of

ancilla lines and MZI switches. All optical implementation of MZI-based asynchronous and

synchronous counter is presented. Mathematical model to simulate the proposed architecture has

also been presented. Finally, design complexities of all the counters are analyzed.

6.2.1. Asynchronous Counter

Asynchronous counter is known as ripple counter. Design architecture and working

principle of all optical functionally reversible asynchronous down counter is presented here. The

mathematical model for simulation of this memory element is described.

6.2.1.1. Design of 2-bit positive edge triggered down counter

35 | P a g e

The schematic diagram of MZI based 2-bit positive edge triggered down counter is

depicted in Fig. 6(a), which is constituted with two positive edge triggered D flip flops viz. FF-0

and FF-1. Each of the positive edge triggered D flip- flop consists of three MZI switches viz.

MZI-1, MZI-2 and MZI-3, two beam combiner (BC) namely BC-1, BC-2 and four (expect the

last flip flop viz. FF-1) beam splitters namely BS-1, BS-2, BS-3, BS-4.

For proper understanding, we discuss the signal flow characteristic of the counter as

shown in Fig. 3(a). A light from input port CP (Clock Pulse) directly incidents on MZI-1 of FF-0

and acts as incoming signal. Similarly, another light signal from input port D0 directly enters into

MZI-1 of FF-0 and acts as control signal of MZI-1.The light from bar port of MZI-1(B1) and a

part of light from cross port of MZI-3(C3) is combined by BC-1 together to produce control

signal of MZI-2. In the same way, the output lights from cross port of MZI-1 (C1) and MZI-2

(C2) are combined by BC-2 and acts as control signal of MZI-3. A constant light signal (denoted

by 1) incidents on the beam splitter (BS-1) and splits into two parts, where one part acts as

incoming signal of MZI-3 and another part again incidents on another beam splitter (BS-2) and

splits into two parts. One part appears to MZI-2 as incoming signal and another part that goes to

next flip flop (FF-1) acts as a constant input light signal. The light from the cross port of MZI-

3(C3) is the final output Q0 where as another light signal which emits from the cross port of

MZI-2 (C2) goes back to port D0 and acts as incoming signal.

A part of light comes from BS-5 of FF-0 incident on MZI-1 of FF-1 and acts as clock

pulse of FF-1. Again, D1 acts as the input value of FF-1. We have obtained both the signals

(clock pulse and input signal) for FF-1 and as the design architecture of FF-1 is same as FF-0, we

omitted the control flow description of FF-1.

6.2.1.2. Operational principle of 2-bit positive edge triggered down counter

The operational principle of all the optical asynchronous down counter as shown in Fig 6(a), is

described below. Here, the presence of light is denoted as 1 state and absence of light is denoted

as 0 state.

State I: Let Q0=0 and Q1=0. As D0 is directly connected to , hence, the value of D0 is 1.

Now, the value of clock pulse is 1 i.e., both the control signal and incoming signal are present

in MZI-1. Hence, according to the working principle of MZI, only bar port of MZI-1 of FF-0

emits light which incidents on BC-1 and as a result, an output light signal emits from BC-1. On

the contrary, the cross port of MZI-1 emits no light which incidents on BC-2. Now, the output

signal of BC-1 acts as the control signal of MZI-2 and the input signal of MZI-2 is also present.

Therefore, the cross port of MZI-2 emits no light, as a result, no light incidents on BC-2. The

output signal of BC-2 emits no light and as a consequence, the control signal of MZI-3 is

absent. As the input signal of MZI-3 is present, the cross port of MZI-3 of FF-0 receives light

which is the final output Q0 i.e. Q0=1.

Now, this Q0 acts as incoming signal of MZI-1 of FF-1 and D1, which is directly

connected to the , acts as control signal of MZI-1. Therefore, both the incoming signal and

control signal are present at MZI-1 as both the value of D1 and Q0 are 1. Hence, the operational

principle of FF-1 becomes similar to FF-0 and the cross port of MZI-3 of FF-1 emits light i.e.

the final output Q1=1. So the next state becomes Q1=1 and Q0=1.

State II: Now, Q1= Q0= 1. Again the clock pulse (CP = 1) and D0 (equals the value of ) act

as incoming signal and control signal of MZI-1 of FF-1 respectively. Hence, only incoming

signal is present at MZI-1. According to the working principle of MZI, the bar port of MZI-1

36 | P a g e

of FF-0 emits no light and cross port of MZI-1 of FF-0 emits light which incidents on BC-2. So

the output signal of BC-2 is present that acts as control signal of MZI-3. Again, the input signal

of MZI-3 is also present. So the cross port of MZI-3 receives no light i.e. the value of final

output Q0=0.

This output Q0 acts as incoming signal of MZI-1 of FF-1 and D1 is directly connected

to . So the value of D1 is 0. As both the incoming signal and control signal are absent at

MZI-1 of FF-1, no operation is performed in FF-1. Hence, the final output value of FF-1 does

not change and it is same as the previous state’s output value of Q1. Therefore, the final output

of FF-1 is Q1=1.So the next state becomes Q1=1 and Q0=0.

State III: Now, Q1 =1 and Q0 =0. The value of D0 (directly connected to ) is 1 and the value

of clock pulse is 1 i.e. both the control signal and incoming signal are present at MZI-1. So the

situation becomes same as that of FF-0 at first stage. Hence, according to working principle of

FF-0 described in first stage, the final output of FF-0 is 1 i.e. Q0=1.

As Q0 acts as incoming signal of MZI-1 of FF-1 and D1 is directly connected to , so

the value of D1 is 0. Therefore, only incoming signal is present at MZI-1 of FF-1. This

situation is same as FF-0 of second stage. Hence, according to the working principle of FF-0 as

described in second stage, the final output of FF-1 is 0 i.e. Q1=0. So the next state becomes

Q1=0 and Q0=1.

State IV: In this state, Q1=0, Q0=1 and the value of D0 (control signal of MZI-1) is 0. As the

value of clock pulse is 1, only incoming signal is present at MZI-1 of FF-0. This situation is

same as FF-0 of second stage. Hence, according to working principle of FF-0 as described in

second stage, the final output of FF-0 is 0 i.e. Q0=0.

Now, this Q0 acts as the incoming signal of MZI-1 of FF-1 and D1 is directly

connected to complement of Q1. So the value of D1 is 1. As the incoming signal is absent at

MZI-1 of FF-1, no operation is performed in FF-1. Therefore, the final output value of FF-1 is

not changed and it is same as previous state of Q1. Finally, the output of FF-1 is Q1=0. So the

next state becomes Q1=0 and Q0=0.

The states of the counter are shown in Table VIII. The pictorial representation of positive edge

triggered asynchronous up counter, negative edge triggered asynchronous down and up counter

is depicted in Fig. 6(b), Fig 6(c), Fig 6(d), respectively.

Table VIII: Different States of Asynchronous Positive Edge-triggered Down Counter

Clock

Pulse

FF-0 FF-1

CP0 Q0 D0 ( ) CP1

Q1 D1 ( )

First 1 0 1 1 1 0 1 1

Second 1 1 0 0 0 0 1 1

Third 1 0 1 1 1 1 0 0

Fourth 1 1 0 0 0 0 1 0

Fifth 1 0 1 1 1 0 1 1

37 | P a g e

Figure 6(a): Design of all optical reversible Asynchronous Positive Edge-triggered Down Counter

Figure 6.( b): Design of all optical reversible Asynchronous Positive Edge-triggered Up Counter

Figure 6.(c): Design of all optical reversible Asynchronous Negative Edge-triggered Down Counter

Figure 6.(a): Design of all optical reversible Asynchronous Negative Edge-triggered Up Counter

38 | P a g e

6.2.1.3. Theoritical model of Simulation

In this section, we simulate asynchronous positive edge triggered down counter theoretically

using characteristics equation of SOA-based MZI switch. MZI is very powerful optical switch to

realize ultrafast all-optical switching. The transmission characteristics at bar port and cross port

of MZI switch as shown in Fig. 2(b) are defined [17] as

TR(t)=

G1{k1k2+(1-k1)(1-k2)RG -2 }... (1)

TS(t)=

G1{k1(1-k2) + k2(1-k1)RG -2 }... (2)

Here RG=G2/G1, where G1 and G2 are time-dependent gain and k1, k2 are ratios of couplers of C1

Clock Pulse

4

6

7

8

9

D0 MZI

CP=O

N?

MZI

CP=ON?

MZI

CP=ON??

Σ Σ

Q0 Q0 Q0

Clock Pulse

MZI

CP=ON?

MZI

CP=ON?

MZI

CP=ON?

Σ Σ

Q1

D1

Q1

1

1

Yes

No

Yes

No No

BS

BS

BS

BC BC

BS BS

Yes

No

Yes

No No

CP

CP CP

BS BS

BS

BS BS

BC BC

CP

CP CP

5

Figure 6.(b): Control flow analysis of Asynchronous Positive edge-triggered down counter.

39 | P a g e

and C2 respectively. We take 50:50 couplers (for simplicity of our calculation) and fixed the

values of k1 and k2 to

. The output signal power at bar port and cross port of MZI switch is

Pj(t)=Pip(t)Tj(t), j=R,S (3) Where Pip(t)=power of incoming signal.

Using the previous equations power at the different ports of FF-0 can be expressed as

. (4)

. (5)

(6)

. (7)

(8)

(9)

Similarly, the output power of the different ports of FF-1 can be expressed in similar way. The

flow chart of this simulation is shown in Fig. 6(e).The equation numbers are given with respect

to each output power in the flowchart.

6.2.2. Synchronous Counter

In the synchronous counter, all the flip-flops are triggered simultaneously. As we have already

explained the working principle of asynchronous counter with detailed diagram, here only the

Figure 6.(c): Synchronous Negative edge-triggered up counter implemented by MZI switch

Figure 6.(d): Synchronous Positive edge-triggered down counter implemented by MZI switch

40 | P a g e

pictorial representation of all optical reversible architecture of MZI based synchronous up

counter (negative edge triggered) and down counter (positive edge triggered) is depicted in Fig.

6(f) and Fig. 6(g), respectively.

Analysis of design complexities of all optical reversible counters is presented in table IX.

Table IX: Analysis on design complexities of all optical reversible counters

6.3. Conclusion

In this work, various architectures of MZI based functionally reversible all optical counters have

been proposed. As far as our knowledge is concerned, the design of reversible all optical counter

is a newer one. Our proposed design can be generalized for n-bit counter also. The proposed

design techniques implement all the optical functionally reversible counters with minimum

number of ancillary lines and minimum optical cost. Mathematical model has also been

formulated.

Different types of n-bit counters No. of MZI

(Optical Cost)

No. of

Beam

Combiner

No. of

Beam

splitter

Garbage

Output

Asynchronous

down counter (positive

edge-triggered) 3n 2n 6n 4

up counter(negative

edge-triggered) 4n 2n 7n 6

Synchronous

up counter(negative

edge-triggered) 4n 2n 7n 6

down counter (positive

edge-triggered) 3n 2n 6n 4

41 | P a g e

Chapter 7

All Optical Implementation of Universal Shift-Register Using MZI Switches.

7.1. Introduction

Now a day, research on design of optical circuits and devices has received wide attention

among the researchers due to ultra-high speed and low-power consumption properties in the

optical devices and interconnects. In this conjuncture optical design of combinational and

sequential elements are among the great priorities in optical circuit research arena. Previously

we have investigated how to design optical memory elements with minimum optical components.

Here, we have presented optical implementation of universal shift register. The design is

made using Mach-Zehnder interferometers (MZIs) based optical devices. Our proposed design

is the generalized one as it includes all the behavior of four typical shift registers. To reduce the

design complexity, we have used minimum numbers of MZIs, beam combiners and beam splitters

and also our design confirms zero overhead in terms of number of ancilla inputs and garbage

outputs.

7.2. Proposed Work

In the section we have presented the all optical design of universal shift register. Optical

devices like semiconductor optical amplifiers, Mach-Zehnder Interferometers, beam combiners

and beam splitters have been used to design the architecture. The proposed design ensures

minimal use of optical devices and the circuit does not need any ancilla line. The 4-bit design of

universal shift register is presented here but the design is scalable upto n-bit. Working principle

of the design and its analytical illustration is presented next.

42 | P a g e

7.2.1. All-optical design of 4-bit universal shift register

The proposed design of fully optical 4-bit universal shift register is depicted in Fig. 7(a).

The design has four identical blocks where each block is constructed using one 4x1 optical

multiplexer and one positive edge triggered optical D flip-flop. As per the design of optical

multiplexer and flip-flops is concerned, the optical design of D flip-flop is already reported in [8]

whereas we have designed the optical circuit for 4x1 multiplexer using six MZIs and three beam

combiners.

For proper understanding, here we discuss the signal flow characteristic of the proposed

design. As the universal shift register has four identical blocks, here we only discuss the signal

flow in one block which has been marked with dotted lines.

A light from input port S0 incidents on MZI-1 of MUX-1 and acts as control signal to

MZI-1 and using beam splitters this incoming signal is transmitted to MZI-2, MZI-3 and MZI-4,

where the individual distributed signal act as incoming, control and incoming signal,

respectively. As the output (Q0) from first block is directly connected to the incoming signal of

MZI-1, the light signal from serial output directly enters as control signal to MZI-2. Similarly,

the light signal from the output (Q1) of second block and the light signal from input port I0 act as

the incoming signal and control signal of MZI-3 and MZI-4, respectively.

The light from cross port (C1) of MZI-1 and the light from bar port (B2) of MZI-2 are

combined by BC-1 together that produce the incoming signal to MZI-5. In the similar manner,

the emitted light form cross port (C3) of MZI-3 and bar port (B4) of MZI-4 are combined by BC-

2 together to produce the control signal for MZI-6. A light signal from the input port S1 incidents

on a beam-splitter that splits into two parts, where one part act is control signal for MZI-5 and

another one enters MZI-6 as incoming signal.

The light from cross port (C5) of MZI-5 and the light from bar port (B6) of MZI-6 are

combined together using BC-3 to produce control signal for MZI-7. A light from input port CP

(Clock Pulse) directly incidents on MZI-7 in first block and acts as incoming signal. Similarly,

another constant light signal (denoted by 1) incidents on the beam splitter (BS-1) and splits into

two parts, where one part acts as incoming signal for MZI-8 and another part incidents on MZI-9

as incoming signal. The light from bar port of MZI-7(B7) and a part of light from cross port of

MZI-9(C9) are combined together by BC-4 to produce control signal for MZI-8. In the similar

fashion, the output lights from cross port of MZI-7 (C7) and MZI-8 (C8) are combined by BC-5

and the combined beam acts as control signal for MZI-9. The emitted light from the cross port of

MZI-9 is the final output (Q0) for the first block.

All the remaining three blocks are designed in the same above manner.

7.2.2. Operational Principle of 4-bit universal Shift Register

To construct an all optical Mach-Zehnder Interferometer based 4-bit universal shift

register we required two select lines S0 and S1, where for different values of S0S1 viz. 00, 01, 10

and 11 universal shift register performs different operations. The operational principle of this all

optical 4-bit universal shift register which is shown in Fig. 1(a) is described below. Here, the

presence of light is denoted as 1state and absence of light is denoted as 0 states. Let at any

instance the output value of the shift register is 0010(Q3Q2Q1Q0).

Case 1: Let the value of S0 =0 and S1=0. In this case the output of the multiplexer (MUX-1) is

equal to the input value of the incoming signal of MZI-1. As the incoming signal of MZI-1 is

43 | P a g e

directly connected to the output value of the Q0, the output of the multiplexer (MUX-1) is equal

to zero i.e. no light is emits from BC-3 of first block. Hence no light is incident on MZI-7 as its

control signal. Therefore the input value of D flip flop is zero. As the input of D flip flop is zero,

the output of D flip flop is also zero i.e. no light is present in the cross port of MZI-9. Therefore

the final output (Q0) of first block is 0.

In the similar way the output value of second, third and fourth block is 1, 0 and 0

respectively .i.e. Q1=1, Q2=0 and Q3=0. Therefore the values of output do not change when S0

=0 and S1=0.

Case 2: Let the value of S0 =0 and S1=1. In this case the output of the multiplexer (MUX-1) is

equal to the input value of the incoming signal of MZI-3. As the incoming signal of MZI-3 is

directly connected to the output value of the Q1, the output of the multiplexer (MUX-1) is equal

to one i.e. a light is emits from BC-3 of first block. Hence a light is incident on MZI-7 as its

control signal. Therefore the input value of D flip flop is one. As the input of D flip flop is one,

the output of D flip flop is also one i.e. a light emits from the cross port of MZI-9. Therefore the

final output (Q0) of first block is 1.

The design architecture of both the second and third block is same as the first block. So

the incoming signal of MZI-3 of second and third block is directly connected to the output value

of the Q2 and Q3. Therefore both the output values of the multiplexer (MUX-2, MUX-3) are

equal to zero i.e. no light is incident on MZI-7 of second and third block. Hence no light emits

from the second and third block i.e. the final outputs of second block and third block are zero (Q-

2=0, Q3=0).

In the fourth block serial input for shift-right is directly connected to the incoming signal

of MZI-3. As the design architecture of the fourth block is same as other blocks, the final output

of the fourth block is same as the input value of serial input for shift-right. Hence no light emits

from fourth block if no light incident on MZI-3 and a light emits from fourth block if a light

incident on MZI-3.

Therefore the final output when S0 =0 and S1=1 is

Q3Q2Q1Q0=0001, when no light incident on fourth block as serial input for shift-right

and the value of Q3Q2Q1Q0=1001 if a light incident on fourth block as serial input for shift-right.

Case 3: Let the value of S0 =1 and S1=0. In this case the output of the multiplexer (MUX-1) is

equal to the input value of the control signal of MZI-2. As the control signal of MZI-2 is directly

connected to the serial input for shift-left, the output of the multiplexer (MUX-1) is equal to the

value of serial input for shift-left. Therefore the final output (Q0) of first block is directly

dependent on serial input for shift-left.

44 | P a g e

1

BC

BC

M

Z

I

M

Z

I

M

Z I

M

Z I

M

Z

I

M

Z

I BC

Q0

I0

M

Z

I

M

Z

I M

Z

I

BC

BC

BC

BC

M

Z I

M

Z I

M

Z

I

M

Z

I

M

Z I

M

Z

I

BC

Q1

M

Z

I

M

Z

I M

Z

I

BC

BC

BC

BC

M

Z

I

M

Z

I

M

Z

I

M

Z

I

M

Z

I

M

Z I

BC

M

Z

I

M

Z

I M

Z

I

BC

BC

BC

BC

M

Z

I

M

Z I

M

Z

I

M

Z

I

M

Z

I

M

Z

I

BC

Q3

M

Z

I

M

Z

I M

Z

I

BC

BC

I1

I2

I3

Serial input for

shift-right

Serial input for

shift-left

MUX-1

D-FF

D-FF

D-FF

D-FF

MUX-2

MUX-3

MUX-4

Q2

CP

S0

S1

Figure 7.(a): 4-bit all Optical Universal Shift Register using MZI Switches

45 | P a g e

The design architecture of the second, third and fourth block is same. As the control

signal of MZI-2 of second, third and fourth block is directly connected to the output value of the

Q0, Q1 and Q2, the output values of the multiplexers (MUX-2, MUX-3 and MUX-4) are equal to

zero, one and zero, respectively. Therefore no light is incident on MZI-7 of second and fourth

block and a light is incident on MZI-7 of third block. As a result no light emits as the output

value of D-FF from the second and fourth block and a light is emits from the D-FF of third block

i.e. the final output values of second, third and fourth blocks are zero, one and zero respectively

(Q3=0, Q2=1 and Q1=0).

Therefore the final output when S0 =1 and S1=0is

Q3Q2Q1Q0=0100, when no light incident on first block as serial input for shift-left and the

value of Q3Q2Q1Q0=0101 if a light incident on first block as serial input for shift-left.

Case 4: Let the value of S0 =1 and S1=1. In this case the output value of the multiplexer (MUX-

1) of first block is equal to the input value of the control signal of MZI-4. As the control signal of

MZI-4 is directly connected to the input value of the I0, the output of the multiplexer (MUX-1) is

same as the value of I0. This output of MUX-1 also acts as the input of the D-FF of the first

block. Therefore the output value (Q0) of the first block is equal to the value of I0.

In the similar way the output value of second, third and fourth block is equal to I1, I2 and

I3, respectively. Therefore the values of output Q3Q2Q1Q0= I3I2I1I0 when S0 =1 and S1=1.

The different action of universal shift register is shown in Table-X.

Table X: Different States of Universal Shift Register

S0 S1 Action

0 0 No action

0 1 Shift-right

1 0 Shift-left

1 1 Parallel Load

7.3. Conclusion

In this work, we have presented an efficient all optical implementation of reversible

universal shift register using semiconductor optical amplifier (SOA) based Mach-Zehnder

interferometer (MZI) switches. The proposed design has zero overhead in terms of number of

ancilla inputs and garbage outputs. Design complexities presented ensure improved optical costs

and minimum delay in optical circuit realization.

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Conclusion and Future work

In this thesis the work is divided into two parts; in the first part implementation of all

optical based Mach-Zehnder Interferometer (MZI) based all optical reversible CLA circuit is

described and in the second part all optical based memory elements (sequential elements) using

MZI switches

In the first part, we have briefly discussed the properties (change of refractive

index with intensity of light) of nonlinear material semi-conductor optical amplifier (SOA) based

Symmetric Mach-Zehnder Interferometer (SMZI) suitable for all optical switching. We have

used all optical based Mach-Zehnder Interferometer (MZI) switches to design the CLA circuit

implementing reversible functionality. We have proposed two approaches for designing the

CLA circuit. First, we have proposed a hierarchical approach for implementation of 2n-bit

reversible CLA. In the second approach, we have removed the drawback of hierarchical CLA

and improved the design by implementing non-modular staircase structure of n-bit reversible

CLA. The design complexities of both the approaches have been computed. Experimental result

shows that the optical cost and delay incurred in staircase structured reversible implementation

of CLA is much less than that proposed in the recently reported works.

In the second part, various sequential elements are implemented in optical domain

using SOA based MZI switches. Among various memory elements, designing of RS, D, JK, T

flip-flops, Master-Slave Flip-Flop and universal shift register are presented. The proposed design

techniques implement all the optical functionally reversible flip-flops and counters with

minimum number of ancillary lines and minimum optical cost. Mathematical model has also

been formulated for counters and universal shift register. The proposed designs have zero

overhead in terms of number of ancilla inputs and garbage outputs. Design complexities

presented ensure improved optical costs and minimum delay in optical circuit realization.

In future, SOA based SMZI tree structure can be explored that can successfully be used

to design all optical half-adder, half-sub tractor, full adder, full subtractor, multiplexer, de-

multiplexer. We also are working on simulation of our proposed optical circuits using OptiBPM

[27] software. Simultaneously we are working on designing of all optical Arithmetic Logic Unit

(ALU) using MZI switches.

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