implementation of a fhss transceiver on an sdr

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Implementation of a FHSS transceiver on an SDR platform If I have seen further it is only by standing on the shoulders of giants

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Page 1: Implementation of a fhss transceiver on an sdr

Implementation of a FHSS transceiver on an SDR platform

If I have seen further it is only by standing on the shoulders of giants

Page 2: Implementation of a fhss transceiver on an sdr

SDR platform

RF

moduleData conv

module

DSP

module

Page 3: Implementation of a fhss transceiver on an sdr

Specs of an SDR platform

DSP Module:

oDSP CPU clock 594 MHz

oARM CPU clock 297 MHz

oNAND flash memory 128 MB

oDDR2 SDRAM 128 MB

oFPGA Virtex IV

Page 4: Implementation of a fhss transceiver on an sdr

Specs of an SDR platform

Data Conv Module:

– DC specs:

• Input channels 2

• Input channels resolution 14 bit

• Out put channels 2

• Output channel resolution 16 bit

– AC specs:

• Acquisition Sample Rate 125Msps

• Acquisition Bandwidth 150Mhz

• Transmission Sample Rate 500Msps

Page 5: Implementation of a fhss transceiver on an sdr

Specs of an SDR platform

RF Module:

– Receiver

• Frequency range 30Mhz to 900Mhz

• Switching speed 240us to 420us

• Minimum Detectable signal -102dbm

– Transmitter

• Frequency Range 200Mhz to 930Mhz

• Synthesizer Freq Range 500MHz to 930Mhz

• Switching speed 240us to 420us

Page 6: Implementation of a fhss transceiver on an sdr

FHSS on the SDR board

Transmitter:

Data Acq ModulationFrequency Hopping

Up Sampling

Up Conversion

to IF

DACUp

Conversion to RF

TxAntenna

Data ConvRF Module

Page 7: Implementation of a fhss transceiver on an sdr

Down Conversion

from IF

FHSS on the SDR board

Rx Antenna

ADC

De-hopping

Demodulation

Received Data

Down Sampling

Down Conversion

to IF

Data ConvRF Module

Receiver:

Page 8: Implementation of a fhss transceiver on an sdr

DM6446 Virtex-4 SX35 FPGAData Conversion

Expansion Connector

FPGA Virtex-4

ADC

Data Conversion Expansion Connector

RF Out

Tx Antenna

RF In

Rx Antenna

IF Out IF In

VPSS

DAC

PCM codecs

Hardware Flow Diagram

Page 9: Implementation of a fhss transceiver on an sdr

Synchronization

Pilot Signal PN Sequence Data

Page 10: Implementation of a fhss transceiver on an sdr

Technical Challenges

DM6446Modulation

SchemeComputational

EfficiencyVirtex-4 SX35

FPGAVPSS

4 MSPs

DAC

LYRIO 125 MSPs

Up SamplingNon-integer Up sampling

factor

Buffer Length=2^x

Less powerful ADC

RF module

Switching Speed 240us

Less powerful ADC

Synchronization

Page 11: Implementation of a fhss transceiver on an sdr

Conclusions

Successful Simulation of the FHSS system on Matlab

Successful Implementation of an FSK transceiver on a Spartan III kit

Successful Implementation of a test bench that could take any waveform and implement it

– Successful Implementation of an FHSS transceiver on the SDR platform

– A real time audio transceiver on the SDR platform with FSK

– A real time audio transceiver on the SDR platform with PSK

Page 12: Implementation of a fhss transceiver on an sdr

Recommendations

Comparison of a large number of modulation schemes on the developed test bench

Source Coding and Channel Coding Algorithms

Multi-node Communication

Page 13: Implementation of a fhss transceiver on an sdr

Questions