in this lecture: lecture 6: more gates and their...

E1.2 Digital Electronics 1 6.1 31 October 2008

Lecture 6: More Gates and their Applications

Dr Pete SedcoleDepartment of E&E Engineering

Imperial College Londonhttp://cas.ee.ic.ac.uk/~nps/

(Floyd 3.6, 6.8 – 6.10)(Tocci 4.6 – 4.8, 9.6 – 9.8, 3.15)


In this lecture:

• Exclusive-OR & Exclusive-NOR gates• Functions using logic gates• Parity circuits – using XOR gates• Multiplexer and Demultiplexer circuits• The IEEE Standard for logic symbols


Exclusive-OR (XOR)

The output of an exclusive-OR (XOR) function is HIGHwhen the inputs are different


Exclusive-NOR (XNOR)

The output of an exclusive-NOR (XNOR) function is HIGHwhen the inputs are the same

E1.2 Digital Electronics 1 6.5 31 October 2008 E1.2 Digital Electronics 1 6.6 31 October 2008

An XNOR gate is used here to simplify

the circuit implementation

(4 gates instead of 5)


Parity generator and checker


Enable/disable circuits

AND and NAND gates can function as enables/disables


Design a logic circuit that will allow a data signal (A) to pass through to the output only when two control signals (B, C) are both HIGH. If either control signal is LOW, the output should stay LOW.

Design a logic circuit that will allow a data signal (A) to pass through to the output only when only one (but not both) of two control signals (B, C) are HIGH. Otherwise the output should stay HIGH.


Merging & inversion circuits

A

B

X

An OR gate used for a signal merging function:

An XOR gate used for a signal inversion function:

Data Y

Data Z

Data

Control


Multiplexers

• A multiplexer circuit (MUX) is a data selector:• one of the data inputs is transmitted to the output,

depending on the values of the select inputs

I0I1I2

IN-1

OUTPUT

SELECT

MUX

DATA INPUTS


2-input multiplexer


4-input multiplexer


I7I7HHHLI6I6LHHLI5I5HLHLI4I4LLHLI3I3HHLLI2I2LHLLI1I1HLLLI0I0LLLLHLXXXHZZS0S1S2E

74ALS1518-input MUX

S2S1S0

E

Z Z

I0 I1 I2 I3 I4 I5 I6 I7

inputs outputs


Two 74HC151 (8-input) MUXscombined to form a 16-input MUX


A MUX used to implement a logic function

f ABC ABC ABC= + +

A B C f0 0 0 00 0 1 00 1 0 00 1 1 11 0 0 11 0 1 01 1 0 01 1 1 1

D0D1D2D3D4D5D6D7

Y

S2S1S0

f

00011001

Variables { ABC


Another example


Demultiplexers• A demultiplexer (DEMUX) is a data distributor• The data input is transmitted to ONE of the data outputs

depending on the values of the select inputs

D0

D1

D2

DN-1

DATA OUTPUTS

SELECT

MUX

DATA INPUT I


A 1-line-to-4-line DEMUX


A 1-line-to-8-line DEMUX

000000I0

O1

00000I00

O2

0000I000

O3

000I0000

O4

00I00000

O5

0I000000

O6

I0000000

O7

outputsinputs

0111001101010001011000100100I000

O0S0S1S2


Alternative symbols for gates

• Inputs on the left, outputs on the right• The Standard symbols have a qualifier at the top-centre:

1 & >1 =11

We have used two forms for drawing gates:

IEEE/ANSI standard

Traditional

MultiplexerMUXMultiplierPAdder∑XOR=1OR≥1AND&

Straight through (buffer)1


• Identical elements can be grouped as an array with common control signals

• An example: 4 identical AND gates sharing a single enable signal:

EN

&A1B1

A2B2

A3B3

A4B4

OUT1

OUT2

OUT3

OUT4


Control dependency notation

Label Name On assertion ... On de-assertion ...EN Enable permits action prevents actionG AND (Gate) permits action forces output lowV OR forces output high permits actionN NOT (Invert) Inverts output No effectS Set forces output high No effectR Reset forces output low No effect


Numbered dependency• Data inputs and outputs can all be numbered• A number following a control dependency label indicates which

inputs or outputs it affects• Example:

An array of buffers

Inputs (1) are ANDed with the ENABLE signal

Outputs (2) are inverted if INV signal is asserted (LOW)

G1

A1

A2

OUT1

OUT2

1 2

N2INV

ENABLE

1


Active High, Active Low & Asserted

• The device is enabled if the Enable input is “asserted”

• What does “asserted” mean?– in the active state– if the signal is labelled EN, then asserted means Enable = 1– if the signal is labelled EN, then asserted means Enable = 0

Outputs

Enable

Data Inputs

..

. ...

ENConsider some device

with an “Enable”control input

active high

active low


4-input MUX: IEEE Standard Symbol

MUX

f}0

10123

ABselect inputs

data inputs

G 03

in this lecture: lecture 6: more gates and their...

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