index to computer architecture: a minimalist perspective

8/14/2019 Index to Computer Architecture: A Minimalist Perspective

1/6

Index

4

4004.............................................27

6

6502 ...xiv, 9, 19, 28, 150, 151, 161,

169, 179, 181, 183, 189

68000 .....................9, 10, 11, 20, 28

68020 ...........................................28

8

8008.............................................27

8080 .......................................27, 28

8086 .......................................11, 28

8088 .............................................28

80x86 .......................8, 9, 10, 11, 28

A

ABLE...........................................53

accumulator ..5, 8, 9, 18, 19, 20, 21,

43, 48, 49, 69, 70, 75, 76, 77, 78,

80, 82, 85, 86, 88, 91, 92, 94, 95,98, 101, 102, 105, 108, 110, 123,

124, 125, 159, 160, 162, 163,

169, 170, 171, 172, 173, 174,

175, 176, 177, 178, 179, 180,

181, 197

activity packet....................130, 197

ADD ......8, 35, 68, 70, 88, 146, 148

address bus.................................197

Altera .........................................137

Amdahl, Gene....115, 116, 117, 118

ANSI C ..............................138, 139

arithmetic logic unit (ALU).......197assembler.......................89, 90, 197

assembly language.xiv, 89, 90, 110,

112, 150, 151, 183, 197

associative memory ...........197, 198

atomic instruction ......................197

Automatic Computing Engine

(ACE) ......................................52

average...........................96, 98, 123


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214 Index

B

B1700/B1800...............................53

Backus, John........................25, 113

Bell Laboratories .........................28

biological computing.....................2

Bhm, Corrado ............................xvBhm-Jacopini Theorem 56, 57, 58,

65, 67

branch on zero (BNZ)..................49

bubble sort .................................106

Burroughs ....................................53

bus.....11, 17, 21, 52, 113, 129, 130,

136, 197, 198, 199, 201

C

C language .......8, 10, 19, 90, 91, 93

cellular automata........................198

central processing unit....15, 16, 17,

197, 198, 199, 200, 201, 203

Church, Alonzo......................xv, 55

Cocke, John .................................26

compiler 29, 30, 34, 53, 89, 90, 112,

119, 120, 123, 138, 151, 155,

189, 198

complete1, 2, 15, 52, 61, 62, 63, 64,

66, 67, 69, 70, 71, 122, 143, 148,

151, 198

Completeness Theorem .........55, 63complex instruction set computer

(CISC)........................1, 137, 198

complex instruction set computer

(CISC).....1, 2, 33, 34, 35, 37, 38,

39, 47, 122, 198

complexity 1, 34, 35, 36, 37, 38, 42,

48, 49, 50, 89, 118, 157

condition code register...............198

conditional branch 7, 43, 48, 52, 66,

198

content-addressable memory .....198

Control Data Corporation............ 29

control unit (CU) ...........17, 25, 198

coprocessor ................................198

Corporaal, Henk ....................xv, 53

Cray I .........................................127

CRISP C-Machine.......................28

crossover....................142, 143, 144Crusoe..........................................30

Culler ...........................................29

cycle stealing .............................198

Cydrome ......................................29

D

data bus......................125, 128, 199

dataflow computer.... 127, 130, 131,

197, 199

DEC......20, 27, 83, 84, 92, 94, 100,

107, 160, 163, 172

decidability ..................................55

decode..................33, 120, 121, 199

DesignWare...............................139

dilation...... 144, 145, 146, 147, 148,

149, 150, 151, 183, 189, 193

Dinman, Saul .........................xv, 52

direct memory access (DMA).....16,

137, 198, 199

direct mode instruction.............. 199

DMA controller .................198, 199

DNA .. 134, 151, 152, 154, 155, 157DRAM.......................................199

dynamic memory.......................199

E

effective instruction 46, 62, 81, 199,

200

erosion .......144, 145, 146, 147, 149

exception..........................5, 11, 199

explicitly parallel instruction

(EPIC)................................29, 39


3/6

Index 215

explicitly parallel instruction

computing (EPIC)..............29, 39

F

fetch-execute cycle ............199, 202

field programmable gate array(FPGA)30, 31, 54, 135, 136, 137,

138, 139, 144, 148, 149, 151, 208

finite state automata (FSA)...60, 61,

62, 152, 153, 154, 199, 200

fitness.................141, 142, 143, 144

flush ...........................................200

Flynn, Michael...........126, 127, 128

FORTRAN...................25, 119, 155

fractal .........................................134

G

gene....................141, 142, 143, 144

general register ........17, 36, 37, 200

Genetic Algorithm.....139, 140, 206

greatest common denominator

(GCD)............................109, 110

GRI 909 .......................................52

H

half adder (HA)...41, 43, 44, 52, 70,

71, 134, 137, 144, 146, 149, 151,

152, 155

Handel-C....................................138

Harvard ............................21, 23, 24

Hennessyxv, 18, 21, 27, 28, 42, 207

Hilbert, David ..............................55

Hoare, C.A.R .............................118

hypercube processor .114, 115, 127,

132, 200

I

IBM.. 20, 23, 24, 25, 26, 28, 29, 206

IBM 704.......................................25

IBM 801.................................26, 27

IEEE 1364 .................................139

immediate mode instruction ......200implied mode instruction...........200

indirect mode instruction...........200

instruction parameterization .45, 46,

81, 200

instruction register....... 17, 199, 200

instruction sequencing...45, 81, 200

instruction synthesis .34, 47, 80, 81,

200

Intel..........10, 11, 20, 27, 28, 29, 39

interrupt .. 7, 9, 10, 16, 17, 172, 178,

179, 200, 201, 203, 204

controller..........................17, 200handler location .....................201

register ...................................201

return location........................201

vector .............172, 178, 179, 201

J

Jacopini, Giuseppe.................xv, 71

Java Virtual Machine.............21, 53

L

Laplante, Phillip ................... 25, 52

linear array processor.200, 201, 204

Lipovski, Jack........................xv, 53

LISP.......................................25, 32

M

machine code 18, 89, 90, 91, 92, 93,

94, 95, 119, 123, 197, 201


4/6


5/6

Index 217

Parvani, B., ..................................xv

Patterson, David.....................xv, 28

Pentium....................................8, 10

pipelining...........120, 121, 123, 202

postfix notation......................8, 202

preempt ......................................203

primary memory ............78, 79, 203processing element (PE) ...128, 129,

149, 203

program counter (PC) ...5, 7, 10, 17,

19, 28, 30, 42, 48, 50, 58, 59, 61,

62, 63, 64, 65, 66, 68, 70, 88, 89,

91, 92, 93, 95, 111, 148, 149,

172, 178, 181, 196, 198, 201,

202, 203

propagation delay...............129, 203

protein........................152, 154, 155

Q

Quicksort ...........................118, 119

R

reduced instruction set computer

(RISC).....1, 2, 21, 25, 26, 27, 28,

29, 33, 34, 35, 36, 37, 38, 39, 46,

47, 53, 78, 122, 127, 155, 203

register direct mode instruction.203

resultant ....6, 7, 8, 9, 12, 19, 20, 36,43, 44, 45, 47, 64, 70, 78, 79, 82,

83, 84, 85, 86, 87, 88, 89, 111,

142, 149, 203

reverse subtract and skip on borrow

(RSSB).....................................48

RISC I ..........................................28

RISC II.........................................28

Rojas, Paul.............................xv, 66

S

SBN

OISC......................73, 75, 76, 86

scratch pad memory...................203

selection..57, 58, 59, 60, 61, 62, 63,

65, 67, 141, 142, 143, 147self-modifying code...................203

Sierpinski Triangle ............134, 135

SOLOMON ...............................127

SPARC ..................................21, 28

speculative execution.................203

speedup......114, 115, 116, 117, 118

SRAM........................................203

stack 5, 8, 17, 18, 20, 21, 27, 38, 73,

74, 75, 80, 97, 98, 102, 105, 108,

110, 124, 125, 159, 160, 172,

174, 176, 177, 178, 179, 203, 204

stack architecture 18, 19, 20, 21, 38,73, 74, 75, 80

stack pointer.........17, 172, 178, 204

Stanford University .....................28

static memory ............................203

status register..9, 10, 17, 43, 48, 52,

58, 59, 61, 62, 63, 64, 66, 87,

111, 169, 170, 171, 176, 204

subtract and branch if negative

(SBN).41, 44, 48, 49, 51, 52, 156

instruction.41, 43, 48, 54, 67, 69,

73, 76, 77, 79, 88, 89

Synopsys....................................139

systolic processor.......127, 130, 204

T

Tabak, Daniel ........................xv, 53

Transmeta ....................................30

transputer ...........................131, 204

trap...................................7, 89, 204

Turing computable.....66, 67, 69, 70

Turing, Alan .................... xv, 52, 55


6/6

218 Index

V

van der Poel ..xv, 41, 42, 48, 51, 75,

76, 77, 78

van der Poels Criterion...............48

VAX 11/780 ................................27

vector processor.........................204Verilog...............................138, 139

VHSIC Hardware Description

Language (VHDL)...51, 138, 139

VLIW.....................29, 30, 128, 206

von Neumann....2, 24, 30, 113, 127,

131, 135, 204

bottleneck.......................113, 204

processor........................131, 204

W

wavefront processor..127, 128, 130,

204

X

Xilinx...................54, 137, 138, 208

XOR.. 9, 52, 82, 83, 84, 87, 88, 111,

133, 154, 155, 172, 181, 204

closure....................................204

Z

Zilog ............................................28

index to computer architecture: a minimalist perspective

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