Indicators of mobility extraction error in bottom gate CdS metal-oxide-semiconductorfield-effect transistorsUkjin Jung, Young Gon Lee, Jin Ju Kim, Sang Kyung Lee, I. Mejia, A. Salas-Villasenor, Manuel Quevedo-Lopez,and Byoung Hun Lee Citation: Applied Physics Letters 101, 182106 (2012); doi: 10.1063/1.4765067 View online: http://dx.doi.org/10.1063/1.4765067 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/101/18?ver=pdfcov Published by the AIP Publishing Articles you may be interested in A 60nm channel length ferroelectric-gate field-effect transistor capable of fast switching and multilevelprogramming Appl. Phys. Lett. 99, 182902 (2011); 10.1063/1.3657413 High field-effect mobility ZnO thin-film transistors with Mg-doped Ba 0.6 Sr 0.4 Ti O 3 gate insulator on plasticsubstrates Appl. Phys. Lett. 90, 043502 (2007); 10.1063/1.2434150 Effects of bias stress on ZnO nanowire field-effect transistors fabricated with organic gate nanodielectrics Appl. Phys. Lett. 89, 193506 (2006); 10.1063/1.2378445 Single-crystal CdSe nanoribbon field-effect transistors and photoelectric applications Appl. Phys. Lett. 89, 133118 (2006); 10.1063/1.2345255 Dual insulated-gate field-effect transistors with cadmium sulfide active layer and a laminated polymer dielectric Appl. Phys. Lett. 84, 2922 (2004); 10.1063/1.1704875

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Indicators of mobility extraction error in bottom gate CdSmetal-oxide-semiconductor field-effect transistors

Ukjin Jung,1 Young Gon Lee,1 Jin Ju Kim,2 Sang Kyung Lee,1 I. Mejia,3 A. Salas-Villasenor,3

Manuel Quevedo-Lopez,3 and Byoung Hun Lee1,2,a)

1School of Material Science and Engineering, Gwangju Institute of Science and Technology, Oryong-dong 1,Buk-gu, Gwangju 500-712, South Korea2Department of Nanobio Materials and Electronics, Gwangju Institute of Science and Technology,Oryong-dong 1, Buk-gu, Gwangju 500-712, South Korea3Department of Material Science and Engineering, University of Texas at Dallas, Richardson, Texas 75080, USA

(Received 11 May 2012; accepted 17 October 2012; published online 1 November 2012)

Widely varying mobility values of CdS metal-oxide-semiconductor field-effect transistors have been

reported in the literature (l¼ 1–48 cm2/Vs). Sulfide vacancies in CdS channel generated by an

incomplete post deposition anneal are found to be the origin of scattered mobility values. The presence

of sulfide vacancies can be easily diagnosed by simple electrical measurements checking a strong

channel length dependence of mobility and an abrupt drain current increase due to the carrier ionization

at sulfur vacancies. VC 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4765067]

CdS (Eg 2.4–2.6 eV) is one of the most studied II-VI

semiconductors, especially for flexible electronics applications

because CdS thin film can be deposited at a temperature

below 100 �C using a chemical bath deposition (CBD)

method.1 However, the electrical properties of CdS channel

thin film transistors (TFTs) reported in the literature varied

widely and were inconsistent. First, various conduction mech-

anisms have been reported. Mereu et al. reported that the con-

duction mechanism of a CdS channel is dominated by space

charge-limited currents (SCLC),2 while Voss et al. reported

CdS FETs behaved like buried channel MOSFETs.3 The ma-

jority carrier type of CdS layer was unstable and it could be

changed from p-type to n-type by an annealing.4 Furthermore,

the mobility of n-channel CdS FETs reported in the literature

ranges from less than 1 cm2/Vs to 48 cm2/Vs.5

Widely scattered device characteristics were also observed

at other thin film channel devices such as organic MOSETs

and silicon TFT.6 In case of organic MOSFETs, mobility val-

ues were found to be modulated by the oxygen doping which

caused a bulk current conduction.7 Similar problem has been

reported in silicon TFTs, where bulk defects in the amorphous

silicon channel generate bulk conduction leakage current,8

which is known to cause errors in the mobility extraction.

Although the bulk conduction leakage current usually

results in high off current of MOSFET, the high off current itself

cannot be directly related to the errors in the mobility extraction

because there are many other sources of leakage current. In this

work, device characteristics of CdS MOSFET were investigated

while modulating the channel conduction mechanism by post

deposition anneal (PDA) to find the origin of mobility extraction

error in CdS MOSFETs.

The device structure used in this work is shown in

Fig. 1. To fabricate CdS MOSFETs, 100 nm Al bottom gate

electrodes were first formed on a SiO2 substrate followed by

atomic layer deposition (ALD) of 90 nm HfO2 gate dielectric

at 100 �C. Then, 30, 70, 100, and 130 nm of CdS active layers

were deposited using CBD at 70 �C.9 Finally, an 80 nm Al

contact was formed on the CdS channel using a lift off process

as the source/drain metal contacts. After the device fabrica-

tion, output and transfer characteristics of each device were

electrically tested using a semiconductor parameter analyzer

before and after the PDA at 200 �C in N2 ambient for 30 min.

The PDA is a critical process to reduce the bulk defects

in CdS layer, primarily sulfide vacancies.10 Before the PDA,

threshold voltage (Vth) of CdS MOSFETs decreased due to

the bulk conduction through defect sites as the thickness of

CdS (tCdS) increased (Fig. 2(a)). Vth of 100 nm and 130 nm

devices did not show clear difference due to high defect den-

sity and poor gate control.

On the other hand, Vth of annealed devices did not vary

much as a function of tCdS (Fig. 2(b)), as previously

reported.10 The lower Vth and Id at thicker tCdS before the

PDA indicate that the quality of CdS channel is not uniform

in vertical direction. This is a reasonable assumption because

an increase of defect density in CdS channel after an air ex-

posure has been reported.11,12

The bottom gate MOSFET structure is the one of the fac-

tors making device characterization inconsistent. In the bot-

tom gate structure, the conduction channel is electrically

disconnected from the source/drain contact. The high resist-

ance region between the source contact and the surface chan-

nel (Rsc)/the drain contact and the surface channel (Rdc) is

formed as shown in Fig. 1(a). When tCdS increases, Rsc and

Rdc also increase. Furthermore, Rsc and Rdc are modulated by

the gate bias which affects the bulk conductivity of CdS

region under the source/drain contact. At a low Vg and high

Vd condition, Rsc is high (Vg–Vs¼ 0 V), while Rdc is low due

to high drain bias (Vg–Vd¼ high). As Vg increases, Rsc is still

high, but Rdc increases rapidly because the field applied

between channel and drain contact decreases. As a result, Ioff

actually decreases linearly as Vg increases at subthreshold Vg

region as shown in Figs. 2(a) and 2(b).

Output characteristics were drastically changed by the

PDA. After the PDA, Id–Vd curves of annealed devices

increased uniformly as a function of overdrive bias (Vg–Vth)

a)Author to whom correspondence should be addressed. Electronic mail:

bhl@gist.ac.kr.

0003-6951/2012/101(18)/182106/3/$30.00 VC 2012 American Institute of Physics101, 182106-1

APPLIED PHYSICS LETTERS 101, 182106 (2012)

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like a normal surface channel MOSFETs (Fig. 2(c)). On the

other hand, unannealed devices (Fig. 2(d)) showed an abrupt

Id increase at a certain over drive bias.

The abrupt jump in Id–Vd characteristics was also

observed in many of prior works, but not much attention was

paid to understand the origin of this phenomenon.2,5,9,13 In

our opinion, this phenomenon can be explained with a field

induced ionization of electrons from sulfide vacancies. Fig.

3(a) illustrates our working model to explain the abrupt Id

increase. It is well known that CdS molecules have many

sulfide vacancies acting as double donors.10,13 Charges in the

sulfide vacancies shift Vth as a function of tCdS and act as

hoping sites for a bulk current conduction between source

and drain. When the electric field applied to the CdS channel

reaches a critical value, carriers from these sulfide vacancies

are ionized and Id increases abruptly. The values of critical

ionization field observed in different tCdS are summarized in

Table I. The ionization fields observed at different tCdS are

similar, confirming that the abrupt Id increase was caused by

same physical mechanism, i.e., field ionization.

The role of sulfide vacancies on the bulk leakage current

generation is clearly shown by modulating the stoichiometry

of CdS film. As the concentration of sulfide vacancies

increases, the total channel resistance is exponentially

reduced as shown in Fig. 3(b). In other words, the leakage

current between source and drain (Isd) increases very rapidly

as the sulfide vacancies increase. The temperature depend-

ence of Isd shows another aspect of same phenomenon. After

the PDA, Isd was drastically reduced by 2–3 orders of

magnitude and the activation energy of leakage current is

also increased to 2.59 eV from 2.02 eV. Modification of

dominant leakage current mechanism by the PDA corrobo-

rates with the reduction of the sulfide vacancy after PDA

reported in the literature.14 In summary, Id of CdS MOSFET

consists of both surface channel and bulk channel current,

i.e., Id¼Id,surface þ Id,bulk. Id,surface is independent of tCdS, but

Id,bulk varies with tCdS and the defect distribution.

The presence of Id,bulk conduction seriously distorts the

device characteristics of CdS MOSFETs. For example, the

drain current of long channel MOSFET is inversely propor-

tional to the channel length as shown in the following

equation:

Id ¼ leffCoxðW=LÞ½ðVg � VthÞ � Vd=2�Vd: (1)

However, Fig. 4(a) shows that the channel length depend-

ence of the drain currents is very weak because the drain cur-

rents are dominated by the surface leakage current and a

bulk leakage current through sulfide vacancy sites. On the

other hand, inverse channel length dependence was observed

after the PDA. The impacts of defects induced leakage cur-

rent were more pronounced at thicker tCdS. 130 nm CdS

channel devices showed weak channel length dependence

even after the PDA, indicating 200 �C might have not been

enough to fully passivate defects in the thick CdS channel.

Thus, the abnormal channel length dependence of Id can

be used to detect the presence of Id,bulk. To emphasize the

FIG. 2. Device characteristics of CdS MOSFETs; (a) Id–Vg curves measured

before PDA, Vd¼ 20 V, (b) Id–Vg curves measured after PDA, Vd¼ 20 V,

(c) Id–Vd characteristics measured after PDA. tCdS¼ 100 nm, (d) Id–Vd char-

acteristics measured before PDA. tCdS¼ 100 nm. The Id decrease at high Vd

region is attributed to high series resistance (Rsc þ Rdc).

FIG. 3. Schematic model illustrating the influence of sulfide vacancies in

CdS channel; (a) Before PDA, bulk conduction current via sulfide vacancies

dominates Id. (b) After PDA, surface conduction current dominates Id, but

series resistance components increased. (c) Total resistivity of CdS channel

as a function of the stoichiometry of CdS. Source to drain leakage current

increases as the concentration of sulfide vacancy increases, (d) Activation

energy calculated from the temperature dependence of source to drain leak-

age current before and after PDA.

TABLE I. Critical field (tCdS/Vg–Vth) to initiate an abrupt Id step.

CdS thickness (nm) 30 70 100 130

Electric field (MV/cm) 1.6 1.1 0.8 1.0

FIG. 1. Schematic structure of bottom gate CdS channel MOSFETs; (a) side

view. Rsc and Rdc are source to channel and drain to channel resistances

respectively, (b) top view. The area between source and drain works as a

channel region. In this structure, the bottom gate bias is applied to source

and drain region also.

182106-2 Jung et al. Appl. Phys. Lett. 101, 182106 (2012)

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impact of Id,bulk on the device characterization, field effect mo-

bility values were extracted from the data shown in Fig. 4(a).

In this calculation, the series resistance values were extracted

from Id–Lgate curve. For annealed devices, RscþRdc were

around 550 KX. It is more difficult to extract the series resist-

ance of unannealed devices because Rsc and Rdc are varied by

the bottom gate bias as mentioned above. Actual series resist-

ance should be higher than the approximation and the mobility

values will be underestimated without the series resistance cor-

rection to compensate the Vd reduction (DVd¼ Id�Rs, where

Rs is the series resistance). In this work, drain current reduction

due to the series resistance was compensated using the follow-

ing equation:

I�

d ¼Id�

1� RsId

Vd

� : (2)

Id̊ is the compensated current and Id is the measured current.

Thus, as an approximation, 550 KX was used as an approxi-

mation for unannealed devices. Actual series resistance

should be higher than the approximation and the mobility

values will be underestimated.

The results of this calculation are interesting. After the

series resistance correction, the mobility values of annealed

devices shown in Fig. 4(b) are approximately 1 cm2/Vs at all

channel lengths from 5 to 80 lm, which is close to the major-

ity of data reported in the literature.15 Since the mobility

should not be dependent on the Lgate at the long channel

region, this is a reasonable result. However, the mobility of

unannealed devices shows strong channel length dependence

as expected from Id weakly dependent on Lgate. Furthermore,

the mobility values varied from 1 to 29 cm2/Vs, even with

a slight underestimation as mentioned above. The high

mobility values are obtained because the leakage current

component was included in the mobility calculation. This

error will get worse at long channel devices because the por-

tion of bulk leakage current in the total drain current will

increase at long channel devices. Thus, we are speculating

that the wide scattering of mobility values reported in the lit-

erature might be due to the calculation errors originated from

the inclusion of bulk current component, which is generated

by an insufficient passivation of sulfide vacancies.

In summary, the effects of PDA on CdS channel

MOSFETs have been examined and the root cause of widely

scattered mobility values reported in the literature has been

identified. Channel length independent bulk leakage current

due to an insufficient PDA is found to cause a serious mobil-

ity overestimation at long channel devices. In addition, a few

device characteristics such as an abrupt current jump in

Id-Vd curves, a high series resistance and weak channel

length dependence were identified as indicators for the prob-

lems due to bulk conduction component.

This work was partially supported by WCU program

through NRF grant funded by the Korea government (MEST)

(No. R31-10026) and Inter-ER Cooperation Projects funded

by the MKE through KIAT.

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FIG. 4. (a) Channel length dependence of drain current measured before and

after PDA, measured at Vd¼ 20 V, Vg–Vth¼ 15 V. (b) Channel length de-

pendence of field effect mobility at channel width 160 lm and tCdS¼ 100 nm,

Vd¼ 5 V, Vg–Vth¼ 5 V.

182106-3 Jung et al. Appl. Phys. Lett. 101, 182106 (2012)

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