inf3430 - h131 dcm location and clock distribution
TRANSCRIPT
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INF3430 - H13 1
DCM Location and clock distribution
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INF3430 - H13 2
DCM and clock distribution 1
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INF3430 - H13 3
Xilinx Digital Clock Manager
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INF3430 - H13 4
Xilinx Core Generator
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INF3430 - H13 5
Xilinx Core Generator Project
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INF3430 - H13 6
Xilinx Gore Generator Project Setup 1
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INF3430 - H13 7
Xilinx Core Generator Project Setup 2
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INF3430 - H13 8
Generating Single DCM module
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INF3430 - H13 9
DCM Setup 1
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INF3430 - H13 10
DCM Setup 2
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INF3430 - H13 11
DCM Setup 3
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INF3430 - H13 12
DCM Setup 4
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INF3430 - H13 13
DCM Setup 5
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INF3430 - H13 14
DCM module Entity
library ieee;use ieee.std_logic_1164.ALL;use ieee.numeric_std.ALL;library UNISIM;use UNISIM.Vcomponents.ALL;
entity clkmng is port ( CLKIN_IN : in std_logic; RST_IN : in std_logic; CLKFX_OUT : out std_logic; CLK0_OUT : out std_logic; LOCKED_OUT : out std_logic);end clkmng;
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INF3430 - H13 15
DCM module Architecturearchitecture BEHAVIORAL of clkmng is
signal CLKFB_IN : std_logic; signal CLKFX_BUF : std_logic; signal CLK0_BUF : std_logic; ……
begin CLK0_OUT <= CLKFB_IN; CLKFX_BUFG_INST : BUFG port map (I=>CLKFX_BUF, O=>CLKFX_OUT); CLK0_BUFG_INST : BUFG port map (I=>CLK0_BUF, O=>CLKFB_IN); DCM_INST : DCM generic map( CLK_FEEDBACK => "1X", …… ) port map(CLKFB => CLKFB_IN, CLKIN => CLKIN_IN, …… RST => RST_IN, …… CLKFX => CLKFX_BUF, …… CLK0 => CLK0_BUF, …… LOCKED => LOCKED_OUT, …… );
< Evnt. Generert Reset logic; se slide 18-19 > end BEHAVIORAL;
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INF3430 - H13 16
CRU med clkmng module Entity
entity cru is port ( arst : in std_logic; -- Asynch. reset refclk : in std_logic; -- Reference clock; 50 MHz rst : out std_logic; -- Synchronized arst_n for mclk rst_div : out std_logic; -- Synchronized arst_n for mclk_div128 mclk : out std_logic; -- Master clock; 50 MHz pclk : out std_logic; -- Processor clock; 100 MHz mclk_div : out std_logic -- Master clock div. by 128. ); end cru
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INF3430 - H13 17
CRU with clkmng module Architecture
::
clkmng_0: clkmng port map ( CLKIN_IN => refclk, RST_IN => arst, CLKFX_OUT => pclk, CLK0_OUT => mclk_i, LOCKED_OUT => open);
-- Removed in architecture str2 with DCM ---- bufg_0: bufg-- port map (-- i => refclk,-- o => mclk_i);
::
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INF3430 - H13 18
DCM med ekstra reset logic del 1
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INF3430 - H13 19
DCM med ekstra reset logic del 2