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Information-Reduced Carrier
Synchronization of BPSK and QPSK Using
Soft Decision Feedback
Esteban Vallés, Richard Weseland John Villasenor
Electrical Engineering DepartmentUCLA
Marvin Simon and Christopher Jones
Jet Propulsion Laboratory
2
IntroductionThis paper addresses the carrier-phase estimation problem under low SNR conditions in a soft decision-directed LDPC-coded system.
Two distinct techniques for joint decoding and synchronization :1. Modifying iterative detection/decoding algorithms and/or graph structure
to include parameter estimation2. Turbo Synchronization: Pass messages between an independent
phase estimation block and an essentially unmodified iterative decoder [Noels05]
The technique in this presentation falls into this second category.
We propose a soft decision-directed pilotless carrier recovery circuit with little modification to either the iterative decoder or the carrier recovery block.
3
MotivationWhen designing communication systems engineers need to decide whether or not to suppress the transmitted carrier power
Total power = Carrier Power + Data Power Pt=Pc+Pd
Carrier Power: related to the accuracy of the carrier synch processData Power: related to the accuracy of the data detection process (in the presence of perfect carrier synchronization).
System design requires a proper trade off between these power requirements to minimize the average error probability of the system [Simon96] .
Traditional synchronization circuits:Residual Carrier: Utilize phase-lock Loops (PLL) to provide an accurate synchronization. (Used in NASA’s deep space comm. systems.)Suppressed-carrier: Tracking loops such as the Costas loop require a larger SNR to track the carrier with a given accuracy.
4
Phase-Lock Loop (PLL):Use residual carrier information inside the tracking loop to aidsynchronization.
Loop SNR:
BL: Loop Bandwidth, Pc: Total Carrier Power, No: Noise PSD Øc: Carrier Phase Estimation Error
There always exists an optimum (in the sense of minimum average error probability) split between Data and Carrier power .
If m2=Pc / PT , typical systems require m2≈0.1or less [Simon96]This trend suggests using suppressed-carrier systems, i.e. m2=0
Possible Synchronization Circuits
fc
DataPower
CarrierPow er
fc
DataPow er
Suppressed CarrierResidual Carrier
2
1
c
PLLo L
cPN Bφ
ρσ
= =
5
Possible Synchronization CircuitsCostas Loop
Can track fully suppressed-carrier signals.Loop SNR:
BL: Loop Bandwidth, Pt: Total Power, No: Noise PSD,RD: Input Data SNR, SLC: Squaring Loss, Ts: Pulse Duration
Requires significantly larger loop SNR than a PLL to be able to track.At low data SNRs, the SL can be large enough to prevent tracking.
For a fixed input data SNR , SL does not improve with decoder iterations.
For a wide input data SNR range, Costas loop systems are still more efficient (in the sense of minimum average error probability) than PLL circuits.
Alternative Circuit: design a suppressed carrier system for low data SNR that uses a PLL circuit instead of a Costas loop.
2
1 11 . 11 1
2 2c
C
oL
d T s
t TC
o L o L
NSR P
P PTN B N Bφ
ρσ
− −⎛ ⎞ ⎛ ⎞
+ +⎜ ⎟ ⎜ ⎟⎝ ⎠ ⎝ ⎠
= = =
6
Information-reduced carrier-synchronization (IRCS)
Use a soft estimate of the instantaneous data symbol (and thus of the instantaneous phase modulation) to reduce the amount of randomness (information) in the signal being processed in the carrier loop. [Simon97]
LDPC symbol estimates “wipe-off ” modulated symbols in a decision directed loop to enhance the carrier information such that a classic PLL can provide increasingly accurate phase estimates over LDPC iterations.
Latency penalty: tracking improves with increased iterations
System complexity: No significant modifications to the current residual carrier recovery techniques used for BPSK/ QPSK modulation in NASA's deep-space network.
7
DelayΔ
1 ( ; )cy t θ 1 ( ; )cy t θ− ΔPLL
( ; )cu t θcθ
22
( )( ) ( ) n ty t m tA
= − Δ +
DetectedData
-M ixer-Demodulator
-Decoder
IRCS BPSK System Description
BPSK Modulation:
Signal Input:
AWGN Noise:
IR Signal:
( ) ( ) ( ) ( )1 1; 2 sinc c cy t P t n tm tθ ω θ= + +
( ) ( ) ( )1 1 12 ( ) cos ( )sinc c c s c cn t N t w t N t w tθ θ= + − +⎡ ⎤⎣ ⎦
( )( ) k sk
m t d p t kT∞
=−∞
= −∑
( ) ( ); 2 sin [Noise terms]c c cu t P w tθ θ= + +
8
Carrier Detection Process
Assume N=5 transmitted BPSK symbolsSample transmitted waveform = [ 1, -1, 1, -1 ,1 ] Plot shows received waveform affected by symbol-wise noise
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
-1
0
1
t
Am
plitu
de
-80 -60 -40 -20 0 20 40 600
0.05
0.1
0.15
0.2
f
Am
plitu
de
1 -1 1 -1 1
9
Carrier Detection Process
Modulation is removed by multiplying the received waveform by soft-estimated symbols from the decoderSymbol Information randomness is reducedPlot shows “IR” waveform after the first iterations
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
-1
0
1
t
Am
plitu
de
-80 -60 -40 -20 0 20 40 600
0.05
0.1
0.15
0.2
f
Am
plitu
de
Soft Symbol informationmay still beincorrect
Incorrect information has lowreliability
Unmodulatedfrequency spectrum begins to show the presence of a carrier tone.
10
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
-1
0
1
t
Am
plitu
de
-80 -60 -40 -20 0 20 40 600
0.1
0.2
0.3
0.4
f
Am
plitu
de
Carrier Detection Process
As the number of iterations increase, soft-symbol estimation becomes more accurate.Frequency spectrum has a distinctive tone that a PLL based circuit can now track.
11
Proposed Synchronization CircuitInformation Reduced Carrier Synchronization (IRCS)
Can track fully suppressed-carrier signalsLoop SNR:
BL: Loop Bandwidth, Pt: Total Power,SL IRCS: Squaring Loss, A: Estimated Signal Amplitude
The ratio represents the decoder soft-estimate data SNR.
Symmetry condition: For decoding of LDPC and turbo codes σ2=2A. [Chung01]
Decoder data SNR increases with iterations causing:SL IRCS 1Loop SNR approaches PLL performance using the total transmitted power for carrier estimation
2
12
211 .c
IRCSIRCS Lo L
TPAN B
Sφ
ρ σσ
−⎛ ⎞
+⎜ ⎟⎝ ⎠
= =
2
2
Aσ
LDPC
1
21
o L
T
AN BP −
⎛ ⎞+⎜ ⎟⎝ ⎠
=
12
PLL:
Loop SNR exhibits No squaring lossUtilizes carrier power for carrier estimation
Costas Loop:
SL is independent of the iteration process, for a given SNR.Suppressed carrier scenario
IRCS:
SL approaches unity as the number of LDPC iterations increaseSuppressed carrier scenario
Loop SNR Summary
2
1
c
PLLo L
cPN Bφ
ρσ
= =
2
1 . 112
c
CCL
Lt
o dNS
RPBφ
ρσ
⎛ ⎞+⎜ ⎟
⎝=
⎠=
1
2 . 211IRCS
c
IRCSo
LT
L
PAN
SBφ
ρσ
−
= = ⎛ ⎞+⎜ ⎟⎝ ⎠
13
BPSK Digital Circuit Implementation
( )ˆcosck cw θ=
DetectedData
Sample &Hold
( 1)( ; )s
s
k T
ckTx t dtθ
+
∫( ; )s cx t θ
2π
Sample &Hold
( 1)( ; )s
s
k T
ckTx t dtθ
+
∫( ; )c cx t θ
1( ; )cy t θ
LDPCDecoder
NCO ACC
( )ˆsinsk cw θ=
2 2 /k k ky d n A= +
skz
ckz cku
sku
ke
( )2 sin cw t
( )2 cos cw t
( )ˆ2 sink s c ce T P Noiseθ θ= − +
θc
y1
Re
Im
sin( )cos( )
ck k
sk k
z d c N oisez d c N oise
θθ
= += +
sin( )cos( )
ck c
sk c
u A Noiseu A Noise
θθ
= += +
( ; ) ( ) sin( ) ( ; )
( ; ) ( ) cos( ) ( ; )c c s c c
s c s c c
x t PT m t N oise t
x t PT m t N oise t
θ θ θ
θ θ θ
= +
= +
( )( )2
22
2 where 2
s
k sk ck ck sk LLRsLLR
o
PTQ z w z w E
N
σσ
= + =LDPC LLR Inputs:
14
BPSK : Algorithm Initialization
Step 1: Resolve initial phase ambiguityMeasure average power across a single codeword of the signals zc and zs.
Choose component with higher power to initialize the phase estimation processAn error of 180 degrees may remain
Re
Im
Re
Im
π Ambiguity
ˆ 0cθ =cθ π=
15
BPSK : Pilotless Phase Ambiguity Correction
Step 2: Remove possible 180° offsetRun a single PLL passRun up to 4 LDPC iterations and choose the orientation that produces the maximum percentage of satisfied constraints on odd degree check nodes (even degree checks remain satisfied after a π rotation of its inputs)
Im
Re
1 2 3 445
50
55
60
65
70
75
80
Iterations
Sat
.Con
stra
ints
%
Es\No=1.6dB
ˆ 0cθ =
{ }ˆ, ,04c cπθ θ ⎧ ⎫= ⎨ ⎬
⎩ ⎭
{ }ˆ, ,4c cπθ θ π⎧ ⎫= ⎨ ⎬
⎩ ⎭
16
Step 3:For i=1 to Max_Iterations1. Estimate Carrier Phase Offset 2. For j=1 to LDPC_iter
Update VariablesUpdate Constraints
3. Update Variables4. Go to 1
Performance plots in the nextslides are shown for LDPC_iter ={1,2} BER/FER performance starts to degrade for cases where phase estimates are computedafter a higher number of decoder iterations.
BPSK Main Decoding Algorithm
+
+
+
VariableNodes
ConstraintNodes
( )
( )2
2
2
2
where 2
k sk ck ck skLLR
s
LLRs
o
Q z w z w
PTEN
σ
σ
= +
=
17
Experimental Results: Loop SNRPlot shows loop SNR vs Iterations. θc=0° and θc=45° 2
1Loop SNRcφσ
=
0 5 10 15 20 25 30 35 40 45 500
10
20
30
40
50
60
70
1 Loop Update every 2 LDPC Iterations
1/ E
( φc2 ) [
dB]
Iteration
θ=0 Eb/No=1.0 dBθ=0 Eb/No=1.25dBθ=0 Eb/No=1.5dBθ=0 Eb/No=1.75dBθ=0 Eb/No=2.0 dB
0 5 10 15 20 25 30 35 40 45 500
10
20
30
40
50
60
70
1 Loop Update every 2 LDPC Iterations
1/ E
( φc2 ) [
dB]
Iteration
θ=π/4 Eb/No=1.0 dBθ=π/4 Eb/No=1.25dBθ=π/4 Eb/No=1.5dBθ=π/4 Eb/No=1.75dBθ=π/4 Eb/No=2.0 dB
Note the curious performance for the θc = 0° case.In this region the initially correct PLL’s phase estimate is affected by poor initial LDPC soft-symbol estimates.Both LDPC estimates and loop-SNR dramatically improve after the 10th iter.
{ } { }0 0ˆ, ,=c cθ θ { } 04
ˆ, ,⎧ ⎫= ⎨ ⎬⎩ ⎭
c cπθ θ
18
Steady State is reached after 50 iterations
As we will see in the next slide this means that
Some loss occurs with a reduced number of iterations.
After 50 iterations, a small marginal degradation in loop-SNR remains
Experimental Results: Loop SNR
0 5 10 15 20 25 30 35 40 45 500
10
20
30
40
50
60
70
801 Loop Update every 2 LDPC Iterations
1/ E
( φc2 ) [
dB]
Iteration
Eb/No=1.0 dBEb/No=1.25dBEb/No=1.5dBEb/No=1.75dBEb/No=2.0 dB
θc=0°
θc=45°
0 5 10 15 20 25 30 35 40 45 500
5
10
15
20
25
30
35
Δ (1
/ E( φ
c2 )) [d
B]
Iteration
Loop SNR Difference
Eb/No=1.0 dBEb/No=1.25dBEb/No=1.5dBEb/No=1.75dBEb/No=2.0 dB
2 20
4πσ σ− −−
19
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.410-5
10-4
10-3
10-2
10-1
100FER performance
FER
Eb \ No [dB]
FER 20it.CodeFER (20-10)it.φ=π/4FER (20-20)it.φ=π/4FER 50it.CodeFER (50-25)it.φ=π/4FER (50-50)it.φ=π/4
BPSK Frame Error Rate Performance
20 Iterations
Loop did not reach Steady State
Performance loss at a FER of 1e-3 is
0.15dB with a (20-10) = (1 Loop update every 2 LDPC iterations) scheduling
0.07dB in the (20-20) = (1 Loop update every 2 LDPC iterations) scheduling
50 IterationsLoop in Steady StateSmall performance difference after 50 iterations due to loop-SNR marginal degradation
5 10 15 20 25 30 35 40 45 5010-5
10-4
10-3
10-2
10-1
100
Eb \ No =1.0 [dB]
FER performance
FER
Iterations [dB]
Eb \ No =1.5 [dB]
Eb \ No =2.25 [dB]
Stand-alone Code(1 Update-2 Iter) φ=0(1 Update-2 Iter) φ=π/4(1 Update-1 Iter) φ=π/4
20 iter.
50 iter.
20
QPSK Analog Circuit Description
DelayΔ
1( ; )cy t θ
MixerDemodulator
Decoder
PLL( ; )cz t φ
22
( )( ) ( )I
II
n ty t m tA
= +
DetectedI & Q Data
DelayΔ
-π/2
22
( )( ) ( ) Q
Q Q
n ty t m t
A= +
( ; )I cu t θ
( ; )Q cu t θ
+
DelayΔ
1( ; )cy t θ 1( ; )cy t θ− ΔPLL
( ; )cu t θcθ
22
( )( ) ( ) n ty t m tA
= − Δ +
DetectedData
-M ixer-Demodulator
-Decoder
The QPSK IRCS carrier recovery circuit follows the same principles as its BPSK counterpartSymbol feedback is now done for the real and imaginary signal components
BPSK QPSK
21
Squaring Loss (SL) for QPSK systemsRecall the BPSK SL expression:
For our QPSK system :
where the noise variance factor (1+Rd) (RD: Input Data SNR ) comes from the presence of a quadrature (signal x noise) term. [Simon06]
The penalty in performance due to the Rd term becomes insignificant for low symbol SNR scenarios.
No 4th order (signal x noise) or (noise x noise) in the loop as in QPSK Costas or hard-decision IRCS loops.
1 12
2
21 1LSA Aσ
− −⎛ ⎞ ⎛ ⎞+ = +⎜ ⎟ ⎜ ⎟⎝ ⎠⎝ ⎠
1 12
2
(1 ) )21 (11Ld d
ARS
AR σ
− −+⎛ ⎞ ⎛ ⎞+ = +⎜ ⎟ ⎜ ⎟⎝ ⎠⎝ ⎠
+
22
ConclusionsWe have demonstrated a method for improving the carrier synchronization function for iterative BPSK using soft output information from an LDPC decoder .
Motivation is to overcome the performance loss due to a noisy signal reference at low SNRs, characteristic of suppressed carrier loops such as the Costas loop.
Steady state operation is reached after around 45 LDPC iterations.
Performance degradation with respect to the perfect phase information case, in steady state and with a proper loop update schedule, is smaller than 0.1dB.
23
ReferencesM. Simon and S. Million, “Residual versus Suppressed-Carrier Coherent Communications”TDA Progress Report, vol. 42-127, Nov. 15, 1996.N. Noels, V. Lottici, A. Dejonghe, H. Moeneclaey, M. Luise, and M. Vandendorpe, “A theoretical framework for soft-information-based synchronization in iterative (turbo) receivers,” EURASIP Journal on Wireless Communications and Networking, vol. 2005, pp. 117–129, 2005.M. Simon and V. A. Vilnrotter, “Iterative information-reduced carrier synchronization using decision feedback for low SNR applications,”TDAProgress Report, vol. 42-130, Aug. 15, 1997. [Online]. Available: http://tmo.jpl.nasa.gov/progress report/42-130/130A.pdfM. Simon and A. Tkacenko, “An iterative information-reduced QPSK carrier synchronization scheme using decision feedback for low SNR applications,”TDA Progress Report, vol. 42-164, Feb. 15, 2006. [Online] Available: http://tmo.jpl.nasa.gov/progress report/42-164/164H.pdfS. Chung, T. Richardson, and R. Urbanke, “Analysis of sum-product decoding of low-density parity-check codes using a Gaussian approximation,”IEEE Trans. Inform. Theory, vol. 47, pp. 657–670, Feb. 2001.