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UMI
Application of Static Transfer Switch
for Induction Motor Load Transfer
Yuri Pavlyuk
A thesis subrnitted in confonnity with the nquirements
for the de- of Master of Applied Science
Graduate Depammnt of Electricd and Computer Engineering
University of Toronto
0 Copyright by Yuri Pavlyuk 1997
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Application of Static Transfer Switch for Induction Motor
Load Transfer
by
Yuri Pavlyuk
A thesis subrnitted in conformity with the rcquircments
for the degree of Mater of Applied Science
Graduate Department of Electrical and Computer Engineering
University of Toronto 1997
Abstract The most cost-effective way to provide a large power user with unintemptible power is
to supply the consumer's facility with two feeders and to install automatic transfer equipment
to switch over to an altemate fecder if the primary supply fails. The given work is concemed
with such a type of load transfer. For the purpose of a transfer process study, a laboratory
prototype of an automatic transfer switch was built. The control algorithm of the switch
operation was developed and implcmentcd on the controller board utilizing a TMS320C40
digital signal processor. Transfer tests wcre perfomcd on various types of common industrial
Ioads under differcnt disturbances, although the siudy of an induction motor transfer was of
primary importance. Likewise digital time-domain simulations using PSCAD/EMTDC
software was made and comparison with laboratory tests provided. Results and observations -.
found in the studies are pnsented in this thesis.
Table of Contents
Abstract
CHAPTER 1 Introduction
1.1 Typical Application of Automatic Transfer Switches
1.2 Thesis Objective
1.3 Thesis Outline
CHAPTER 2 Static Trader Switch (STS)
2.1 Main Power Circuit Configuration
2.2 STS Performance During Undervoltage and Overvoltage Conditions
2.2.1 Mode 1 Operation
2.2.2 Mode 2 Operation
2.3 Required Feanires of Automatic Static Transfer Switches with Dual Feeders
2.4 Conclusions
CHAPTER 3 Dynamic Behavior of Induction Motor during Transfer between Two
Sources
3.1 The General Nature of the Problem of Motor Load Transfer 20
3.2 Transfer of a Group of Induction Moton 24
3.3 Criteria for Safe Transfer of an Induction Motor 26
3.4 Industrial schemes for Conventional Motor Load Transfer 28
3.4.1 Fast Transfer 28
3.4.2 Paralle 1 (Hot) Transfer 28
3.4.3 Dclayed In-Phase Transfer 29
3.4.4 Delayd Residuai Voltage Transfer 30
3.4.5 Slow Transfer 3 1
3.5 Conc 1 usions 33
CHAP'ïEk 4 Deveiopmnt of a Laboratory prototype d the Staüc Trrasler Switch
4.1 Functiond Characteristics of the Dcveloped Laboraîory Prototype of STS 34
4.2 Powtr Circuit 35
Ili
4.3 STS Controller 36
4.4 Sensing and Gating Circuits 39
4.5 UndervoltagdOvervoltage Deteciion Mcthod 41
4.6 Load Transfer Strategy 5 1
4.7 Conclusions 55
CHAPTER 5 Testhg and Evaluation of Static Tmnster System
5.1 Results of Experimental Tests of the Dcveloped Laboratory Prototype of STS 56
5.1.1 Resistive Load Transfer 56
S. 1.2 R-L Load Transfer 58
5.1.3 R-C Load Transfer 40
5.1.4 Inductive Load Transfer 62
5.1.5 Motor Load Transfer 64
5.2 Results of Digital Time-Domaan Simulation of Induction Motor Transfer 7 1
5.2.1 Undervoltage and Loss of Power Supply Simulation 73
5.2.2 Short Circuit Faults Simulation 76
5.3 Conclusions 79
CHAPTER 6 Conelusions and Proposais for Future Studies
6.1 ConcIusions 80
6.2 Proposais for Future Studies 81 +
REFERENCES
APPENDIX A Program for Static Transfer Switch Control
APPENDIX B Magnitude .ad Phase Rcsponse of the Implemented MgiW Filter
APPENDIX C ALTERA MAX+plusIl Graphk Design File
APPENDIX D Panmeters d the ExperimcnW Iaductioa Motor
APPENDIX E PSCAD/EMTDC Graphic Design File
APPENDIX F PSCADIEMTDC Data Fik . -.-
List of Figures
FIGURE 1. Double-ended substation
FIGURE 2. Spot network (with network protectors, i.e. circuit breakers with reverse power
protection)
FIGURE 3. Transfer switch (manual or automaiic operation)
FIGURE 4. Typical design goals of powersonscious computer manu fac turers ( from IEEE
S td. 446)
FIGURE 5. Typical power plant auxiliary system
FIGURE 6. Static Transfer Switch with Dual Service Topology
FIGURE 7. Static Transfer Switch with Bus Tie Topology
FIGURE 8. Diode Bridge STS
FIGURE 9. Inductive Load Voltage and Cunent Waveforms
FIGURE 10. Mode 1 Operation
FIGURE 11. Mode 2 Qperation
FIGURE 12. Three Phase Static Transfer Switch
FIGURE 13. Supply and Motor Voltage Phasors
FIGURE 14. Results of Simulation of a IO-kW Induction Motor Transfer [4]. Power Supply
is Resumed at t=255 ms aftet interruption
FIGURE 15. Rcsults of Simulation of a IO-kW Induction Motor Transfer (41. Power Supply
is Resumed at t=286 ms after Intemption
FIGURE 16. Power Interruption for a Group of Two Induction MotorsMotor 1 (7.3 MW)
with Nominal Load, Motor 2 (2.5 MW) Unloaded. - Specd, - Torque [SI.
FIGURE 17. Typical Curve of Motor Bus Voltage Magnitude Versus Anplar Difference
Between Motor Bus Voltage and hcoming Source Voltage
FIGURE 18. Rcsidual Voltage Phase Angle for 3500 HP Induction Motor [8]; H - inertia
. constant (a), L - torque (P.u.).
FIGURE 19. Types of Motor Lod Tmsfer Depending on the Phase Difference and Resid-
ud Voltage
FIGURE 20. Universal High-Performance Conmmllcr UHP-U)
FIGURE 21. Sensing and Gating Circuits
FIGURE 22. Cwrdinate Transformation
FIGURE 23. Cornponcnts , and Amplitude of Voltage Sprc Phasor in Balanced (a) and
Unbalanced (b) Thme-Phase Sy\tcm
FIGURE 24. Undervoltage/Overvolisge Deteciion Method B;rïcd on Equation (EQ 5)
FIGURE 25. Waveforms Obtained Applying t EQ 5) io r Thme-Phase System during Bal-
anced (a) and Unbaluiccd (b) Opration
FIGURE 26. Undervoltage/Overvoltage Detcction Method Using (EQ 6)
FIGURE 27. Integration-Reset Methcxî
FIGURE 2û. Characteristic of Uoder- and Ovcrvoltage Detection System
FIGURE 29. Thyristor Voltage and Cunent Woveforms during Tum-Off
FIGURE JO. Failure to Ensure Thyristor's Turn-off State results in a Subcycle Overlap
FIGURE 31. Control Diagram of the Laboratory Prototype of STS
FIGURE 32. Resistive Load Transfer
FIGURE 33. R-L Load Transfer
FIGURE 34. R-C Load Transfcr
FIGURE 35. Inductive Load Transfer
FIGURE 36.
FIGURE 37.
FIGURE 38.
FIGURE 39.
FIGURE 40,
FIGURE 41.
FIGURE: 42.
FIGURE 43.
FIGURE 44.
Induction Motor Transfer Due to Voltage Sag in Phase A
Induction Motor Transfer Due to Loss of Phase B
Induction Motor Transfer Due to Loss of Preferred Source
Induction Motor Behavior during Transfer to Altemate Source
Simulation of the Induction Motor Transfer Due to a Voltage Sag In One
Phase
Simulation of the Induction Motor Transfer Due to Loss of the Referred
Source
Maximum Stator Peak Cumnt as a Function of Fault Instant
Simulation of the Induction Motor Transfer Due to a h - P h a s e Short Circuit
Maximum Stator Peak Cumnt as a Function of Fault Instant
CHAPTER 1
Introduction
1.1 Typical Application of Automatic Transfer Switches
Automatic transfer switches have ken used for years to provide altemate sources of ac
power for critical loads in the event of disturbance or loss of the normal or preferred sources.
The critical equipment served by these switches has varied in scope from the whole industrial
uni& using many rnegawatts of power served by dual utility feeden from different
substations to hctional kilowatt engine generators switched in to restore domestic lighting
during a blackout. This switching has been accomplished traditionally by electromechanical
means. At low c u m t ratings interlocked or double-throw contactors have been used with
either mechanical or electrical latching. In the larger sizes, "double-ended substations" with
a norrnally open tic circuit breaker configuration as shown in Figure 1, or "spot networks"
using "network pmtectors", as shown in Figure 2 have been used [14]. Tôe later case
disconnects paralleled fctders rather than transfers between them. Similar configurations
have k e n used at medium voltage (5 and 15 kV class) using circuit breakers or other power-
operatecl electromechanical switchgear for automatic operations.
The spot network has ken used successfully by utilities to protect customers from loss
of power to traditional loads. However, they can actually be a detriment when applied to
cntical loads, for example computers, for two reasons. First, the operating time to disco~ect
h m faulted fecder (several cycles) is too long to be effective for computers. Second, by
paralleling feeders, the incidence of feeder faults is significantly increased since momentary
faults on al1 connectai fdm appear at the load. Again this is no problem for naditional
loads but is disastrous for sensitive loaâs. For this reasons, it is more appropriate to transfer
feeders as shown in Figure 1 or 3 rather than use a spot network when serving such critical
equipment 11 41.
Utility Feeder
FIGURE 1. Double-ended substation
Utility Feeder
FiOlJRE 2. Spot nehvork (with network protectors, i.8. circuit breakers with reverse powei protection)
Utility
I; Utility Feeder
_1. 'T
FIGURE 3. Transfer switch (manual or automatic operation)
For many applications the characteristics of automatic rlectrornechanical transfer
switches are very satisfactory. This is particularly tme whcn used in combination with
emergency engine generators for bachp power because the time involved to suu i the engine
is fa; grrater than the operating time of the transfer switches. However, there are two
catcgories of loads for which the sensing and a s f e r tirnes of several cycles create problems.
One problem area is dual-utility source feeding equiprnent that cannot tolerate the
resultant momentary loss of voltage. Cornputers, process controls and communication
equipment generally fa11 into this category, with a typical inteiniption tolcrance of IR cycle
(Figure 4) (141. Also, metal vapor lighting systems extinp:ish after 112 cycle of power
intcmption i d cannot k rcstarted for several minutes. When this type of quipment is used
in cri tical applications in which domitirne cannot be accepted, :inother solution is necessary.
nie second problem a m is feeding active equipment, i!iat is, equipment with energy
stomge, sÜch as fmresonant transfonmrs or motors, even if inomentary intemiption can be
tolcrated.
Typicrl Application of Automatic Tnirmtu Switchas
. -- ." - COMPUTER VOLTAGE r TOLERANCE ENVELOPE '
m
87% ACK OF STORE0 ENER OME MANUFACTURER'S QUIPMENT
r 1 1 1 1 0 1 0.01 . 0.1 0.51.0 6 1 0 30 100 1000
TlME IN CYCLES (60 Hz) 2%
FIGURE 4. Typical design goals of power-conscious cornputer manufacturen
(from IEEE Std. 446) (141
Figure 5 shows typicai power plant auxiliary systcm which serves a large number of elecvic
motoa [SI. These moton an typically induction machines and drive loads such as pumps. fans.
cornpressors, pulverizea and conveyors. In order to provide continuity of proccss, the auxiliary
systern is supplied from two sources of power. Start-up and shutdown power is provided from one
source through the Start-up Transformer whcn the main gencrator is off-line. Once the unit has
been tied to the systern, the station srnice load is transfemd to the unit Auxiliary Transformer or --- normal source. This transfer operation can also bc done on emergency basis when t h e ~ is an
unplanned unit trip or a sudden loss of the normal power source.
Typicrl Applicrtlorr of Automrtic Tnnrkr Swltch.8
Ld+ Unit Aullimias Tranitormar
Station Sarvice - Stui-up Sourco Souno - SM-up Brorkar
Motor Bus T
I
Omar L o d
Station Sewkr Source: The power source tor the power planrs auxiliary systern. typically taken from the generator bus through the unit euxiliaries tmnsfomef and auxiliiry b rea km.
Start-up Source: Source wbkh provides power to operatr the plant's auxiliaiy systern while a gmemtor h rhut down or king started.
Motor 8ur: An auxiiiary systrm bus that pflrnailly feeds power to a plant's large moton.
RGURE 5. Typical power plant auxiliary system
The use of conventional elcctromechanical transfer switches usually rcsulu in power
interruption time of several cycles [1.2]. As it will be shown in Chapter 3, a several cycle transfer
interval can mate an out-of-phase condition between the ultimate source and the load upon
transfer to that source. This rnay rcsult in damage to the equipment. such as motors, or extendcd
loss of operation due to the neccssity to stop and then attcmpt to restart (perhaps sequentially
when multiple loads arc involved, to keep inrush within the source rating).
In order to avoid the above mentioncd negative phenornena, the spced of transfer must be as . --
high as possible. This can be accomplished using a solid-state transfer switch.
1.2 Thesis Objective
In the ment years Static Tnuufe Switchci (STSs) ha! . been widely used to pmvide
unintemptible power supply for voltage sensitive equipmci t (electronic instruments and
cornputers) and in continuous proceu planis [ I I . 1 2, 1 3. 14 1. Since little has ken reponed on the performance of'a S O during the m s f e r of high
inertia motor ioads, the objective of ihis work is it) rlevelop 3~ 1 teSI the laboratory prototype
of a STS for this particulai application.
The presented work consists of two pans:
development of a laboratory prototype of a STS:
experirnental study of the STS performance during moior I lad transfer.
The development of STS includcs:
rating of semiconductors and equipment in order to implen lent the irans fer of a 5- 1 O hp
AC motot;
control algorithm development and implementation in 3 m srocontroller board;
identification of undervoltage/overvoltage detection mahod which can provide desirable
sensitivi ty and speed of operation;
building laboratory senip for motor load transfer implemer tation.
The developed prototype is used to:
study the STS perfomnce under different fault and distur3ance conditions;
identiQ the maximum motor inrush current during transfe: transients.
Finally, the experimental results are compared with simulation results in order to
valiàate the computer model. nie computer model is used to study the motor load ûansfcr
whm the experimmtal setup becomes impractical in tems of rost and equipment.
1.3 Thesis Outline
This thesis is composed of six chapters. The first cliapter attempts to clarify the
motivation of this thesis and covers introductory material.
Chapter 2 introduces static trans fer switch détails: main power circuit configuration
and principle of operation. Switch performance dunng RL load tmsfer is analysed and
maximum tmsfer time for two different transîer co;itrol s:ratcgic?s is identifid.
Chapter 3 reviews dynarnic behavior of iriduction motor d u h g power supply
interruption. Analysis of physical processes in large inenia induction motor during power
intemption is given. Problems of motor load transfcr and possible solutions are discussed.
Chapter 4 covers development of laboratory prototype of STS: power circuit,
undervoltagdovervoltage detection method. control algorithm implementation using digital
signal pmcessing board.
Chapter 5 discusses obtained expenrnental results. The cornparison between the
expriment and simulation is provided.
Chapter 6 provides conclusions about the feasibiliiy of the STS implementation for
moior ioad tmnsfer and some recornrnenâations for iùnire work.
CHAPTER 2
Static Transfer Switch
2.1 Main power circuit configuration
Figure 6 displays a single-line diagram of a systeni in which S, and S, are two solid
state switches. One is connected between the normal (preierred) source V I and the load and
the other one is connected between the altemate source Y, and the load. Such a configuration
fonns Static Transfer Switc h (STS) [ 141.
Preferred Source Y, I
Akernate Source V2 I
critical Load
Nomlly Closed I
FIGURE 6 Static Transfer Switch with Dual Sewice Topology
During normal operation only one pair of thyristors is nimed on in each phase -. comspondingly. P r e f d and altemate source voltages are continuously monitod by
conml logic. Wôen the p n f d source &as a proper voltage, control logic uns on .
thyristors on the prferred soum side. If a deviation of the p r e f d source voltage h m the
S~
I Ir
I
pre-specified limits is detecteâ, transfer to the altemate source is initiated by removing gating
pulses from the thyristors of the preferred source switch and firing thyristors on the altemate
source side. Transfer to an altemate source is prevented if the alternate source voltage is not
present. Upon restoration of the preferred source voltage within the preset limits. a transfer
back to the preferred source is initiated.
Figure 7 shows another widely used configurarion for a Static Transfer Switch. The
power system in service in this figure serves pan of the load from Source A and the other part
of the load fiom Source B. For a disturbance on Source A. switch SI opens, the bus tie switch
S3 closes and the entire load is then served from Source B.
A diode bridge and a thyristor can be used to perfon the same hinction as two
antiparallel thyristors (Figure 8) [14]. Although the drawbitck of this circuit is that it has less
overload capability because a thyristor conducts on both half-cycles and has higher losses
due to the additional voltage drop in two senes conducting diodes.
Usually thyristors or GTOs are used as semicmductor devices in STS applications.
Since a thyristor is nimed off at zero crossing of the clrrrenr, its tumsff tirne can be as long as
half period of the power source. On the other band, 3 GTO breaks current within about 20
rnicroseconds, since it has self-tum-off capability. Although the GTO has supior tumsff
time characteristics, it bas some disadvantages as cornpwed with the thyristor, such that the
GTO itself is still expensive, steady-state dissipation !s large and gating and snubber circuits
are large [iZ].
Source A Source B
Bus Tie Switch
1 1 Critical Loads 1 1
FIGURE 7. Static Transfer Switch with Bus Tie Topology
#' - - - - O
- - - #
+
current flow uring 1 R cycle
ÇlWRE 8. Static Transfer Switch with Diode Bridge
2.2 STS Performance During Undervoltage/Overvoltage
Conditions
To illustrate the STS performance under vMous opcrating conditions a simple single-phase
circuit diagram can be used.
According to the inductive load voltage and currents wavefoms of Figure 9, there are four
typical regions of operation in one cycle:
Region 1: v o > O . i , < O ;
Region 3: v o < O , i , > O ;
Region 4: v, < O . i , < O .
The circuit operates in exactly the same way in Region 1 and 3 and in Region 2 and 4.
There are, therefore, two modes of operation. In Mode 1, the load voltage and current have
opposite signs (Region I and 3) and in Mode 2 they have the same sign (Region 2 and 4).
Two methods can be used to trigger the thyristor switches:
conventional gating;
selective gating. .
In the first case both thyristors of one switch are tumed on immediately after the control circuit
removes gating sigoals from the other switch. In the second method only the desired
thyristor is tumed on immediately while its antiparallel counterpart is tumed on only after the
current zero crossing.
2.2.1Mode 1 Operation.
In Region 1. thyristor SI, conducts and al1 other thyristors are off (Figure 1 Oa).
If then is a voltage drop on the prefemd source side V,, , the control logic will initiate a transfer . -..
from source VI, to V2, by blocking the gating signals of thyristors SI, and SI, , and providing
gating signais for SZp and S2,. Because of the load cumnt direction, thyristor S2. should k
FIGURE 9. Inductive Load Voltage and Current Wavefoms
conducting the load current. At this instant. however. since v, is srnaller than v,, thyristor S2,
is reverse biased and can not be turned on. Thyristor SZp however is fonvard biased and tums on
instantaneously. This results in paraileling preferred and altemate source with maximum overlap
tirne n. During the overlap timc there is a current flow from the altemate source to the preferred
source. If the voltage drop is caused by a shon cirquit on the prrfemd source side, such an
overlap may lead to an increase in fault cumnt. By the use of selective gating during the transfer.
so that only the desired alternate source thyristor conducts initially. the overlap is prevented
(Figure lob). Maximum transfer time in this case is equal to the load power factor angle cp . If an overvoltage occurs on the pnferred soum side (VI, > V2, ), thyristor S2,, is forward
biased and ~ r n s -. on instantaneously. This rrsults in commutation bctween S,, and S2,, in such a
manner that the cuncnt through S,, declines and increases through Sin (Figure WC).
a) Load Transfer Due to Voltage Drop on the Preferred Source Side with Overlap
b) Selective Gating Prevents Overlap at Transfer under Conditions a)
-.. Ivld > 1vz.l
c) hstantaneous Load Tramfer Due to Overvoltage on the Prcferred Source Side
FlGURE 10. Mode 1 Operation
2.2.2 Mode 2 Operation.
In region 2, thyristor SI,, conducts positive load cumnt. When the voltage VI, rises above
a tolerable level, the transfer process is initiatcd. The control logic blocks gating pulses for
thyristors SI,, and SI,, and provides gating pulses for SzP and S2,. Because of the load current
direction. thyristor SZp should be conducting. Since the load voltage v , in this case is higher than
the second source voltage VZa, thyristor S2, is reverse biased and cannot be turned on
instantaneously. However. thyristor SZn is forward biased and tums on instantaneously. When
both thyristors SI, and S2, are conducting rt the same time. the two sources VI, and V2. are
paralleled for a maximum interval I. During the overlap interval line current flows from the
prefemd to the altemate source (Figure I 1 a). The magnitude of this current is determined by
voltage difference V I , - V2, and the impedances of the supply system and line. If the line and
supply system impedances are small in cornparison to the load irnpedance the overlap may result
in considerable overcumnts leading to switch and associated equipment damage. This can be
avoided by the use of selective gating in which thyristor Slp is gated irnrnediately after the
overvoltage is detected. but Sln is gated only after the cumnt through the thynstor S l p declines
to zero (Figure 1 1 b). Maximum transfer dclay in this case is x - cp . In the case of an undervoltage on the pnferred source side, thyristor Sb is fomard biased
and tums on imrnediately. This results in commutation between thyristors Slp and S Z p . The
transfer is completed when the cumnt through Slp declines to zero and S2,, takes on the full load
. current. This is illustrated in Figure 1 lc.
The nsulu of a qualitative analysis of static transfer switch khavior in differcnt modes of
operation are summarized in Table 1.
The conCcpt of a singlephase static transfer switch can k extended to a thrce-phase
application (Figure 12a). The gating signais for thyristors and cumnt through TI are shown in
Figure 12b.
a) Load Trmsfer Due to Overvoltage on the Prefemd Source Side with Overlap
b) Selective Gating Prevenu Overlap ai Transfer under Conditions of a)
lvld 1vz.l
c ) instantaneous Load Transfer Due CO Undervoltage on the Prefcrnd Source Side
-. FIGURE 11. Mode 2 Operation
STS Perlorminco During Onâewolt~wnroItrgo Condition8
Disturbance
r
Undervoltage
Overvoltage
TABLE 1.
1 ( Maximum 1 Maximum Type of Gating Region of Operation I Delay
Gating 1 Quadrants 2&4 ( O I O
Selective Gating
Conven tional
Gating
Quadrants 1&3
Quadrants 2&4
Selective Gating
Quadrants 1&3
Quadrants 2&4
-
cP
O
Quadrants 1&3
Quadrants 2&4
- --
O
O
O
O
--
O
72
O
x-CP
O
O
a) Circuit
b) Waveforms for Resistive Load -"
FiGURE 12. l'hree Phase Static Transfer Switch
2.3 Required Features of Automatic Static Transfer Switches with Dual Feeders A properly designed static tnnsfcr rwitch intiiates tnnsfcr to the alternate source due to
over- or undervoltage conditions. such a! might uccur owing io o feeder fault. power factor
correcting capacitor switching, or motor styiing on ihc preferrcd source [ 1 1.12. 13. 141. It should
do this within the transient tolerance lirnits of the vrved critic~l equipment while ignoring less
severe transients. Such a switch should also be designed to automatically retum to the preferred
source once that source has returned to normal voltage. It should transfer to the altemate source
and remain in that position until manually reset in ihc event of a dixontinuity of the normal path
for the power flow frorn the prefemd source. such as loss of thyristor gating signal. A
synchronizing check should be built into the switch logic. which prevents transfer in either
direction if the two sources are not within 10 electrical degrees of phase with respect to each other
to prevent excess circulation of cumnt between sources during the transfer process [14].
Static transfer switches should include self-contained protection for transient surges that
rnight occur on either source. which would otherwise turn on a thyristor intended to be off and /or
damage the switch. This cm be achieved, for example. by using switching devices with forward
and reverse voltage ratings of at lest twice the maximum peak line voltage plus a tolerance
margin to account for reverse phase condition. Built-in surge suppressors, such as MOVs (metal
oxide variston) with breakdown voltage above the rated line voltage but below twice line
voltage, should ôe included on both sources with sufficicnt energy-absorbing capacity to handle
the worst expected voltage surges 1141. Provisions should be included to prevent false t u m a for
the fastest rising voltage wavefonn expected on either source. Typically this is achieved by the
use of dvldt snubbers across each thyristor pair 1141.
2.4 Conclusions
A Static Transfer Switch is a very efficient means of providing an unintemptible power
supply to criticd loads which cannot tolcnte a mornentûnly loss of power. It can transfer loads to
an altemate power supply in less than a cycle of the supply voltage.
The main power circuit configuration of a Static Transfer Switch can generally be divided
into two categories:
Dual Service Topology ;
Bus Tie Topology.
Operation of the STS is deterrnined by the type of disturbance. and the polarity of the
voltage and current. There are therefore two modes of STS operation which are mirror images of
each other:
Mode 1: voltage and cumnt have the same polarity;
a Mode 2: voltage and cumnt have opposite polarity.
Selective gating of thynston in a STS entirely eliminates cross-cunents between preferred
and altemate sources during a transfer.
CHAPTER 3
Dynamic Behavior of the Induction Motor during
Transfer between Two Sources
3.1 The General Nature of the Problem of Motor Load
Transfer
Figure 13 shows the supply and motor voltage phasors before and after the motor is
disconnected from the power supply [2] . Phasor V, in Figure 13 represents the supply voltge.
Phasor V, represents the motor voltage. 8 is the phase angle between the supply and the motor
voltage.
Prior to disconnection, the supply voltage phasor V, is roiaiing at synchronous speed while
forcing the motor voltage V, to follow in synchronism but at an angle 8 behind it corresponding
to the load-torque angle.
When the motor is disconnected from the supply bus, the supply bus voltage V, continues
as it did when connected to the motor. without varying in amplitude and frequency. However, the
motor terminal voltage V, does change after the disconnection. The total rotating inertia acts as a
prime mover and delivers energy to the xrved load. While üiis energy is transfemd from the
rotating mass to the load, deceleration in the rotating mass results. Such a deceleration coupled
with decaying trapped air-gap flux in the motor produces a decaying voltage whose frequency is
alw continually dropping. nie rotor of a disconncctcd motor immcdiatcly star& to decelerate at a
rate determincd by the rotating inertia and the load chuacteristics; the frequency of the motor
voltage starts decreasing [ I l . Further, the motor residual voltage s t u i s decreasing and the relative
phase angle bétween the motor voltage and the supply voltage starts incnasing. After a certain
time the motor has slowed down such that the motor rcsidual voltage is out of phase with respect
to the supply bus voltage by an angle Q, which is greater than . This situation is illustrated in
Figure 13b.
FIGURE 13. Supply and Motor Voltage Phasors
If the motor were to be rwlosed to the bus voltage at phase angle Bi , shown in Figure
13b. the intemal voltage drop in the motor would be extremely large as indicated in the figure.
However, if the angle between the supply voltage and motor voltage phasors reaches 180
electrical degrees. and the amplitude V, does not reduce appreciably, the phasor sum of V,
and V, would be almost twice the normal line voltage. Upon reconnection, the statting inrush
cumnt could be two tirnes the normal starting innish cumnt of the motor, which is about 6 to 10
times the rated full load cumnt of the motor [l-31. Since the force to which the motor is
subjected is proportional to the square of the cumnt, it should be obvious why out of phase
switching of a motor can bc a problcm. Such forces could loosen the stator coils. loosen the rotor
bars of the induction motors, twist a shaft or even rip the machine from its basc plate. The
cumulative abnonal magnetic stresses andlor mechanical shock in the motor windings and to
the shaft and couplings could ultimatcly lcad to prematun motor failure due to fatigue.
~xtensive studies have bem done regarding the transient khavior of an induction machine
during a transfer ktween two power sources [l-71. Fipns 15 and 16 show rcsults of a digital
simulation of a 10 kW induction rnotor transfer nported in (41, where VS2 - stator terminai
nia Ormnl Natut. of !ha Problrm of Motor Lord tnnrfw
voltage, Is2 - stator cunenl M - torque and s - slip. î h e powcr supply is reconnecied at t = 255
ms after the interruption.
RGURE 14. Results of Simulation of a 10-kW Induction Motor Transfer [4]. Power
Supply is Resumed at 1-255 ms after Interruption
th. Chnoml Natun of tha Probkm of Motar Lord Tnnrkr
which resulu in 8 = 180" phase difference between the supply and motor terminal voltage.
The maximum stator current reaches a value of 10.7 times the rated stator current amplitude and
the torque reaches a value of 5 times the rated torque. Howevcr. the same simulation approach
shows that the worst mm on instant in terms of torque does not nccessarily occur at O = 180" .
In the case of the machine under study, the biggest torque occun at At = 286ms. which
corresponds to a phase diffennce 8 = 205" (Figure 16). It naches value of 6.3 times the nted
torque.
FIGURE 15. Results of Simulation of a 1 0-kW Induction Motor 1 ransfer [4]. Power
Supply is Resumed at b286 ms after Interruption
3.2 Transfer of a Group of Induction Motors
Special attention should k p i d to the cau when the trinsferred load is composed of a
group of different induction motors. Sevenl p;ym have k e n written to explain transients
during motor group tnnsfer (5. 7). To mdyzc the transient bchavior of a group of different
induction moton a parallel connection of iwo machines cm be considered. becruse this
configuration aireaciy exhibits ail the essentid fcaiurcs of r multi-motor group. In addition. a
group of induction moton can be rcduccd to r iwo-machine cquivalent in many cases.
The voltages, induced in stator windings of two panIlcl connected induction rnotors,
are functions of rotor speeds. rotor iime constants and load characteristics (51. If the induced
voltages have different amplitudes or phase angles during the voltage interruption period. a
circulating cumnt between the two parallei connected machines will flow. This cumnt
contributes to a balancing torque in the machines if there is an angular difference between the
rotor fluxes. The torques have the srme amplitude but opposite directions. The machine with
leading rotor flux phasor develops a braking torque and acts as a generator. while the machine
with a lagging rotor flux phasor develops accelerating torque and acts as a motor.
In the beginning of the transieni. rotor fluxes of both machines are in synchronism with
respect to each other. Developed electromechanical torques are equal to driven load torques.
Therefore. the initial speed reduction in both machines is almost the same. Later, per contra.
the speed diffennce between the machines grows in such a way chat the machine acting as a
generator. develops a higher spced than the machine acting as a motor. As the flux
magnitudes of both machines rcduce, the speed difference bctween the machines increases.
Simultaneously the angular diffmnce ktween fluxes grows. When the anplar difference
naches a value of 90'. the torque balance cm no longer be maintained. and the machines faIl
out of synchronism with respect to cadi 0th.
Besides the above discussed electromechanical transients. then are electromagnetic
transients btween two machines so long as they are in synchronism. Figure 16 illustrates the
simulation of power interruption for a grwp of two induction motors.
FIGURE 16. Power Interruption for a Group of Two Induction Motors. Motor 1 (7.3 MW)
with Nominal Load, Motor 2 (2.5 MW) Un1oaded.n - Speed, dm - Torque (51.
-- -
3.3 Criteria for Safe Transfer of Induction Motor
In order to transfer an induction rnotor without damage. motor designers have
established a rule of thurnb. giving conxrvative rcsults in most cases. which indicates that
reclosing or transfer of induction motors should be avoided when the phasor difference
between the residual voltage and the incorning voltage exceeds about 125% to 135% of the
rated voltage of the moior [Z]. The American National Standards institute (ANSI) standard
(30.41-77 (Polyphase Induction Motors for Power Generating Stations) and a proposed
National Electric Manufacturing Association (NEMA) standard would permit a maximum
voltage of 1.33 per unit for out-of-phase transfer or reclosing [2] . With 1.0 p.u. residual
voltage at the rnotor temiinals. the reclosing should occur when the phase difference brtween
the voltages is less than 83 electrical degrees. With the voltage phase difference of 180". for
the reclosing to occur. the residual voltage at the motor terminais should be less than 0.33 p.u.
As stated in Section 3.1, the rate at which the residual voltage decays is dependent upon the
tirne constant of the motor. and the frequency of the residual voltage decays at a rate equal to
the decay in motor speed depending on the type of the load. It is necessary to minimize speed
reduction and voltage drop in order to maintain process continuity. By lirniting the load
which must be reaccelerated. the voltage &op can be reduced. Al1 unessential loads should be
intentionally disconnected from the line and sequentially nstarted after the disturbance.
A typical curve of induction motor bus voltage magnitude versus angular difference
bctween motor bus voltage and incorning system voltage is shown in Fipre 17 [2]. When the
typical decay of motor bus voltage as a function of timc is supcrposed as in Figure 17, for the
group of induction machines that the curve repmscnts. it can k seen that the reclosing or
transfer must be pnvented ktween 0.25-0.4 seconds aftcr the power interruption. If the
residual voltage is ailowed to decay to 33% or less of the rated voltage. any nclosing angle
will. of course, k acceptable. Anothcr helphil guidcline for induction m o t m rhat can be
observed from Fipre 17 is that. from the standpoint of motor damage, it is generally safe to
ieston power immediately after the disconnection so long as the nsidual voltage has fallen
less than 80' bchind the incoming system voltage.
Angular Diffennce between Motor Residual Voltage and Incoming System Voltage
0.2 -
FIGURE 17. Typical Cuwe of Motor Bus Voltage Magnitude Versus Angular
Difference Between Motor Bus Voltage and lncoming Source Voltage
Safe for nclosing
90° 180" 270" 360" 450" 540" 630" 720" 1 1 I 1 1 I 1
3.4 Industrial Schemes for Conventional Motor Load
Transfer
To guard ûgainst excessive reclosing innish currents and torques, the following five
general transfer schemes are used [2 .8 .9] :
3.4.1 Fast Transfer
The basic philosophy behind the fast trmsfer is to transfer the rnotor as fast as possible.
keeping the dead time (time of disconnection from both sources of power) to a minimum.
This is to minimize the decay in the bus residual voltage and phase angle before the transfer
is completed. Fast transfer is often made possible kcause the induction motor is designed to
withstand a reasonable number of transfers at a closing angle less than 80' without a
significant loss in the life expectancy. This transfcr approach provides increased assurances
that the bus has been disconnected from the normal source prior to the altemate source
breaker closing. Bus dead times of 5 to 10 cycles can usually be obtained (using conventional
switchgear) [2, 8, 91. However. failure of the normal source breaker to open will result in
paralleling two sources and may result in equipment damage. This transfer method is widely
used to provide continuous power supply for power plant auxiliary systems and has the
following advantages:
1. Speed of transfer minirnizes the interruption of power supply to the motor bus;
2. Provides the minimum ltvtl of motor stresses of al1 methods available;
3. A safe method to maintain operation of the motors and the most diable rheme;
4. Avoids paralleling of the prefcrnd and altemate sources;
5. Simplescheme to implement.
This transfer method also has the following disadvantages:
1 . Interruption of power supply during the transfer;
2. if the @ansfer occurs fnquently, significant transient torques contributing to fatigue fail-
ures will be prrsent.
3.4.2 Parallel (Hot) Transfer
A common form of planned bus transfer is the parallel bus transfer scheme in w hich the
prefemd and altemate sources are connected in panllel for a short period of time during the
transfer of the motor bus between sources. Prior to paralleling the sources it is ensured that they
are approximately in phase to minimize electrical and mechanical transients that can damage the
assuciated equipmcnr. This method has gnined wide acceptmce bcc;iusc. assuming two sources
are in phase. the transient on the motor bus is eliminated. However. the bus system designed for
this transfer will usually violate the intempt rating for the switchgear and the shon ierm
withstand rating for the transfomen. The advantages of the parallel transfer are:
Continuous power to the motor bus permits an orderly shut-down of units by eliminating
bumps and avoiding motor overstress;
Ease of application and operator understanding.
The limitations of the parallel transfer are as follows:
During parallel operation, the increase in available fault current to the rnotor bus caused by
paralleling the sources requins equipment with much higher fault duty ratings or minimized
paralleling time;
Will not work when steady state differences of voltage and/or voltage angle are too large to
allow safe transfcr.
Cannot be used to transfer when the source to the rnotor bus is lost due to an electrical fault
or abnormal condition.
3.4.3 Delayed In-Phase Transfer In-phase transfer is a scherne designed to monitor the relative phase angle of the motor bus
nsidual voltage with respect to the source voltage and connect the bus to a new source when the
angle is ncar zero. This definition implies that the bus has k e n dixonnected from its primary
source and the motor residual voltage is asynchmnous with the new soum voltage. In order to
connect the bus to the new source, the In-Phase Transfer system must know the time required for
the switch to close and prcdict when to initiate closing. Although. due to variations in the bus
Indu8ttiil Sehamas for Convontlonril Motot Loid T rinater
loading in the time of transfer the residual voltage angle ch;ir;ictenstics may Vary. widely as
shown in Figure 18. This may result in large mgulîr mors on closure [8].
Modem relays chat rneasurc the phase mgle decay charûcteristics use the fint and
second denvatives to predict when CO close the brerker. This minimizes errors due to
variations of residual voltage angle chuacteristics caused by bus loading [2,8].
O 6 12 18 24 30 Xme (Cycles)
FIGURE 18. Residual Voltage Phase Angle for 3500 HP Induction Motor [8]; H - inertia constant (sec), L - torque (pu.).
It should k crnphasized that the in-phase transfer technique is generally suggested for
emergency transfen and not for routine transfers. It provides a diable method of transfer in
instances when the two sources of power are not initially in synchronism [8]. This could be
due to a system design that results in a significant phase angle betwecn two power sources.
3.4.4 Delayed Residual Voltage Transfer W . .
This method involves waiting until the motor residual voltage drops bclow a
predetcrmined level kfon connecting to an alternate source. By waiting until the nsidual
voltage is low such as 25 to 35% of the normal beforc completing the transfer, the rcsultant
lndudrid Sc)Hmaa for Convmtionrl Motor Lord Tnnmfw
voltage at the instant of reconnection to the ultimate source is reduced to a maximum of 1.25
to 1.35 p.u. However. in most bus systems by the timc the voltage drops to this level. the
motor loads would have decelerated to a point. when a portion of this loads may have to be
disconnected because sirnultaneous reacceleration of d l motors is noi possible. Such load
shedding funher complicates the trans fer scheme and requins the operators to mrnuall y
restart the motors that have been taken out of service,
The nsidual voltage transfer wiil always subject the motor to a larger value of open-
circuit voltage than the proper choice of either fast or in-phase transfer. Also the residual
voltage transfer introduces a significantly longer tirne delay than either fast or in-phase
transfer. Therefore the residual voltage transfer should be used only as a backup and either
fast or in-phase trmsfer should be used to provide the minimum transfer transient on the
motor bus.
Advantages of the residual voltage transfer include:
1. Relay and conuol equipment to implement the transfer scheme is relatively uncompli-
cated with an accompany ing high dependabili ty of correct operation.
2. Most auxiliary systems can be successfully transfemd using a sid du al voltage scheme.
3. There is minimal chance of inadvertently paralleling the normal and rltemate sources
due to equipment malfunction.
The disadvantage of nsidual voltage transfer is the following:
The longer time rquircd to transfer to the alternate supply, as compared to a fast
transfer scheme, increases the possibility of low voltage motor starting problems andor the
necessity of shedding loads pnor to transfer.
3.45 Slow Transfer Slow ttansfer is a transfer schemè designed to wait for a predetcrmined time (usually
greater then 20 cycles) after the motor bus power source is removed before connecting this
bus to another source. Voltage rclays do not supervise the transfer. -..
The practice of slow transfer is not widcly used and has no advantage in cornparison to
other schemes.
- -
InduWîrl Sc)nma for Conwntlonrl Motor Lord Tnnatw
The disadvantages of this schemc arc:
1. This scheme takes too long to transfer key motor loads;
2. Gencrally requires some motor loûds to k shed to reduce inrush.
Figure 19 illustrates the three zones for the tnnsfer using the typical voltage and phase
curves as a function of time. Fast iransfer requires that the ultimate source is reconnected
before the phase angle moves outside of Zone 1 . Zone 2 of Figure 19 repnsents the in-phase
transfer when the ultimate source is reconnected when the motor residual voltage is in phase
with this source. When the motor residud voltage drops below a predetermined level (such as
33% of the rated voltage) the ultimate source c m be reconnected with any phase difference.
This is represented in Zone 3 of Figure 19.
Zone 1 2d \ \
ase Di fference \ \
Timc -. -
FIGURE 19. Types of Motor Load Transfer Dependhg on the Phase Diff erence and
Residual Voltage (2)
3.5 Conclusions Transfer of an induction motor between two sources is a senous and challenging
problem, because immediately after the disconnection the motor will not become free of
c k n t s and fluxes. On the contrary, the flux linked with rotor circuit will decay in a iransient
process controlled by the circuit parameten of the rotor (its L/R ratio). This flux will induce
a voltage in the open stator circuit as long as the rotor kecps rotating. However. after
disconnection the rotor stans to slow down at a rate dctermined by its moment of inertia and
the characteristics of the driva load. The nsulting angular difference between supply and
motor residual voltage may lead to significant overcumnts and torque pulses at the moment
of reconnection.
According to [4] the wont case for motor reconnection from the siandpoint of torque
pulse does not necessarily occur when the angular difference between the supply and the
motor residual voltage is 180' . To guard against excessive inrush currents and torques dunng induction motor transfer,
reconnection should be avoided between 0.25-0.4 sec after power interruption.
If the motor residual voltage is allowed to decay below 33% any reclosing angle is
permissible. Although. by the time voltage drops to this level, motor spad reduces such that
continuity of some critical process may be lost.
The ideal solution to the pmblcm of motor load tramfer is to do this operation as fast as
possible. Application of a Static Transfer Switch is very advantageous for this purpose.
CHAPTER 4
Development of Laboratory Prototype of
the Static Transfer Switch
4.1 Functional Characteristics of the Developed
Laboratory Prototype of Static Transfer System
To study the operation of a static transfer system. a laboratory prototype of such system
was developed. It consists of two pairs of thyristors per phase where each pair is connected in
inverse parallel. One set of thyristors is connected to the prefemd power source. while the
other set of thyristors is connected to the alternate source. The outputs of two sets of thyrisors
are connected together and fumish power to a critical load (dual service configuration. as
shown in Figure 6). Thyristors are nanirally commutated.
Power is provided from two synchronized power sources. The steady state voltage is
assumed to be sinusoidal with a maximum Total Harrnonic Distortion (THD) of 5%. The
waveform has no single hamonic component with a magnitude gnater than 3% of the
magnitude of fundamental. Cumnt distottion is expected to be higher. but it should not cause
voltage distortions grcater than the above specified.
The transfer system provides unintemptible power supply for a critical load in the
event of any disturbance:
undervoltage or overvoltage conditions in al1 three phases;
voltage sag in only one phase which results in a total undervoltage of 10%;
short circuit conditions;
loss of one or two phases of the prefemd source;
complete loss of prefemd source. -. (
At the same time the rransfer switch does not rcspond to short term abnomal conditions so
long as significant disturbances do not appear at the served Ioaâ.
- -
Although synchronized sources are assumed, a phase difference between both power
sources is checked and. if any diffennce is found. it is identified as unit malhinction and
transfer is prevented.
The served load is a three phase symmetrical static load or induction motor load. If the
load is an induction motor. it may backfeed the energy stored in spinning shafts into the faulty
system. Therefore. the transfer operation should be accomplished without
faulty system.
4.2 Power Circuit
Since the primary goal of this work is to drvelop of a static trmsfer
induction motor, the ratings of power circuit components should satisfy
regeneration to the
system for 5- 10 hp
requirements for a
safe steady state operation as well as expected worst case overvoltages and overcunents. The
rating of the main components of such a system is specified in this section.
Power Supply: I 15V AC thm-phase three-wire system.
Power Rating: 12.5kVA.
Powcr Factor: the static transfer system is able to power loads with a power factor ranging
from 0.5 (lagging) to unity.
Maximum Continuous Steady State Current: 63A mis.
Overcument Protection: 50-A extemal fuses are placed in the prefemd and altemate side
of the static transfer system.
dV/dt Protection: a snubbcr circuit is placed across each STS thyristor (R = 15 Q.
C = 0.22 pF).
Semiconductor Devices: naturally commutatcd thyristors are u r d as switching devices in
the STS.
4.3 STS Controller
The control of the static transfer sysiem i s ptovided by r Universal High Performance
Controller Platform (L'HP-40) dcvelopd ri thc Pnwer Gmup of the Department of Electrical
and Computer Engineering at the Univcrsiiy of Toronto 11 5). A short description of the
controller and sorne peripheral devices i s given in ihis seciion.
The UHP-40 controller piaiforni i s bûsed un the tloaitng point digital signal pmcessor
TMS320C40 from Texas Instruments (Figure ?O). It ha^ r Harvard architecture with two
separate buses which are called a local and a global bus. The intemal structure of the UHP-40
is 32 bits for al1 address and data paths.
Two static RAM modules (Bank I and Bank 2) with standard sizes can be connected via
SIMM-sockets to the local bus. Bank I is usually populated to provide a minimum amount of
R A M space. A third RAM module (Bank 3) is connected in a similar way to the global bus.
RAM modules are fast enough to operate at a frequency of 40 MHz.
The global bus can be considercd as the peripheral bus on the board since it serves
besides the RAM module also additional hardware. A Dual-Port-RAM with a data bus width
of 32 bits can be accessed directly in order to provide a fast communication with the VME bus
circuit controllcd by the MC68030. The global bus is connected to the FPGA from Altera
which is used to generate gating pattern signais depending on the application. The 9 bit pons
for input and output arc also accessible via the global bus. The output port (Global Control
Register, GCR) provides signals to control several functions on the board whereas the input
port (CornPort Input Register, CPIR) can k used to read status signals on the four CornPort
soc kets . The communication ports provide eight bit asynchronous data paths with handshake
mechanism. Communication ports O to 2 an token owners after rcset. This means that they are
set as output ports whereas communication ports 3 to 5 are set as input ports. Four connectors
on the board provide acccss to the communication ports 1. 2. 4 and S. Thcy are mainly used
for communication with A/D converter bards, but c m also be connected to other üHP-40s in
a multi-DSP rtup. The rcmaining communication ports O and 3 can dso k dimtly accessed
through the connecter on the front panel. They am used for cornrnunicating with a personal
STS Contralkr
cornputer. This interface uses communication pon O for output and communication port 3 for
input data. The second function of cornmunicriion port 3 is io nceive data coming from the
MC68030 in order to download programs.
The circuit around the Motorola CPU MC68030 consists of another 32-bit wide bus. It
accesses a fourth SRAM module (Bank 4) ihat has io k populated in order to provide RAM
for the CPU. Besides Bank 4 an in-circuit programmable Flash-PROM is also connected to the
bus. It uses only 8 data lines but can be directly rcessed by the CPU using its capability of
dynamic bus sizing. A dual asynchronous recciver/transmitter (DUART) with 8 bit bus
interface provides a serial RS-232 interf'ace.
The SCV64 chip 1s connected to the MC6830 and consists of a complete VME bus
interface. It can prform all common types of VME bus transfer cycles and therefore
guarantees full VME bus compatibility of UHP40. Most of the VME bus signals have to be
buffered using bidirectional bus drivers. The SCV64 provides control signals to set the
direction of the fast TTL drivers.
Communication with a cornputer is provided through a serial transmission line
"Hotlink". The Hotlink operates at a speed of 20 MHz w hich corresponds to a data transfer
rate of 20 MBytedsec. It consists of one set of receiving and transmitting lines with associated
circuity and provides most of the functionality mcessary to develop a powerful interface for a
reliable and electrically decoupled data transmission to and from the PC.
The integral part of the DSP system is a quad channel malog to digital converter board.
The board provides high speed data conversion (20 MBytedsec) and maximum use of the
UHP-40 arc hi tecturt . The DSP board can execute user programs for a vat range of industrial control
algorithms. These prognuns arc written in C pmgiamming language using the TMS320
Aoating Point C Compiler. User programs typically requin differcnt signals to be monitored
and puameters/command valucs to be set. This is done through the DSP-Monitor program
which manages data transmission between the U H P 4 and PC. The program emulates
functionality of an oscilloscope and provides data npnscntation in a graphicd form.
SRAM Bank 4 I I P l
F m PROM
V M E b interface scv64 N M d g e J
PZ
FPGA Aîien
FIGURE 20. Universal High-Performance Controller (UHP-40)
4.4 Sensing and Gating Circuits. The static transfer system requires continuous voltage and current monitoring for its
operation. Since the UHP-40 controller board cannot process line voltages and cumnts directly,
special sensing equipment is necessary. It provides a safe level of electrical isolation from the
main power circuit and fumishes distortionless data signals for reliable DSP operation. In the
laboratory setup this is accomplished using voltage and cumnt sensors. Voltages and currenis are
measured at the inputs of the solid state switches on prefemd and altemate source sides. Since
the system is powered from a thne-phase thm-wire supply system and serves only symmetncal
load with dlowable unbalance limits not more than 5%. only two phase-to-phase voltages c m be
monitored. If, for example, voltages VAB and VBC are rneasured directly, the third voltage
VCA can be obtained as follows:
whercas phase voltages can be obtained from the following relations:
The gating signals are developcd by the UHP-40 and amplified by a gate pulse amplifier.
The schematic diagram of the static transfer switch with the controller, and the equipment
which generates the sensing and gating pulses is shown in Figure 2 1.
The frequency spectra of signals for samplc-data systems must be limited to avoid the
aliasing effect. Usually this is achicvcd by the use of an antialiasing filter 1161. Since the
sampling frequency in the actuai setup is rclatively high (5.28 kHz), no aliasing effect was
obsewed and no antialiasing filter was used. Instcad, noise caused by EMI in power electronics
systerns rcsults in signals distortion. To d u c e the influence of this noir on the accuracy of
measurcments, a fourthsrder FIR digital filter was impkmented in the control program. The
filter coefficients were calculated using MATLAB Signal Rocessing Toolbox. The Harnming
window function technique [16] was employed in the filer design. Since no filter specifications
werc initially assumcd, a triai and enor mcthod was used until the desircd rcsults were achieved.
The filter coefficients am givm in Appndix A. Amplihi& and phase chancteristics of the filter
are ploned in Appendix B. Cdculated grwp L l a y of the filter is two sampling periods.
4.5 UndervoltagelOvervoltage Detection Method Since thyristors are uscd as switches in the developed static transfer system. the tum off
time can be as long as half the cycle of the source period. as described in Section 2.2. Therefore,
the method of sensing an undervoltage/overvoltage condition is a key for realizing high-speed
operation. Generally an AC voltage drop can be sensed through cornparison of the refennce
voltage with a DC signal that is obtained by ACDC conversion 111, 12). Voltage dips. however.
do not always occur in three phases at the sarne time. If the sampled voltage is converted into DC
through the-phase rectification, a voltage drop in only one phase-to-phase voltage may not be
detected. Moreover. the signal obtained by AC/DC conversion contains not only a pure DC
component. but some ripples as well. Therefore, an RC filter must be used to eliminate these
ripples. However. this arrangement introduces detection time delay.
To avoid the above drawbacks. the properties of the thne-phase system can be utilized. If
such a system is balanced and supplies power for a balanced load the d-q-O transformation can be
applied to obtain ripple free DC quantitics:
cos(8 - 2n/3) cos(@ + 2n/3) sin(e) sin@ - 2n/3) sin (8 + 2+/3) 1
when 8 = or + cp in particular.
Equation (3) shows that when the lhrre source voltages are balanccd, the Y, component is
zero. Furthennorc, the value of cp can be choscn such that the q-component becomes zero.
Thenfore. the transformation will nsult in a pure DC d-component which is proportional to the
source voltage and can be cornparcd with a refennce voltage.
The d-q-O transformation is a very usehl rnethod to redize DC conversion. but requires - --+
very accurate syncluonization with the thm-phase system. Thercfore, it is difficult to
implement in a practical setup. As an rltcrnativc IO the d g 4 innsformation the a - P - O
trmsfomiation can be used. Thc a - B Irame ih no longer synchronized with the system but
fixed in a certain position with respect io it as show in Figure 3. I t can be seen that a and
p components are not constant vducs. Y in the case of the Park's transforrnation but
J-i functions, of ut. However. the value of a + is constant. It yields the amplitude of the
+ line voltage phasor Vs in a symmctricd thrcc-phsu system. and can be used for overvoltage/
undervoltage detection.
If the a - frame is positioned with respect to the three phase-system as shown in
Figure 22b. the following transformation matrix rpplies:
The elements of the transformation matrix (EQ 4) are no longer trigonometrical functions
of ut + rp as in the case of d-q4 transformation but fixed numben. Furthemore, the a - P - O
transformation does not requin synchronization with the supply system. Hence. it is easy to
implement with less computational effon.
The space phasor obtaincd by transformation (EQ 4) is composed of each component VA.
Vg and V, of the thme-phase system. nius, if undervoltage/overvoltage occun in al1 three
phases simultaneously. it can be effcctivtly dttccted using (EQ 4). However, if a voltage
disturbance occurs in one phase only. it may not be detected. Moreover. if a disturbance results
in topologicai changes in the system. such as loss of phase. then an unbalanced operation of the -.
system happens. In this case transformation (EQ 4) does not yield a DC value. Figure 23a
shows the rcsults of the transformation (EQ 4) implementation on the acnial laboratory setup
for a balanced t h e - p h w system. It can k secn that this transfomation yields a DC signal
FIGURE 22. Coordinat8 Transformation
time (sec)
FIOURE 23. Cornponents va , va and Amplitude Jmi of Voltage Space Phasor in
Balanced (a) and Unbalancd (b) Three-P hase System
V, which cm be compared to the reference V, in order to detemine an overvoltagel
undervoltage condition. Fipre 23b shows results of the same method but for the case when
phase A of the supply system is lost. The signal V, is no longer pure DC value md cannot be
used (without incorporating additional logic into the control algorithm) for disturbance
detection since this may lead to enoneous operation of the transfer system.
Reference [ I l ] describes an oventoltagelundervoltage method in which each phase
voltage (or line voltage) is squared and added as shown by the following relation:
In order to detect undervoltage/overvoltage in each phase separately, equation (5) was
adopted for a real static transfer switch as shown in Figure 24. Although, the control algorithm
shown in Figure 24 allows one to detect an abnormal condition in each phase separately it has
the same drawback as the two previously discusscd methods: equation (5) holds only for a
balanced three-phase system. Results of tcsting this method on the laboratory setup are shown
in Figure 25a for a balanced operation and in Figure 25b for the case when phase A of the
supply system is lost.
In [12] a dctcction methd is introduced which effcctively eliminates deficiencies of the
above approaches. It is descrikd by the following set of equations:
tirne (sec)
0.005 0.01 0.01 5 0.02 time (sec)
flaURE U-vWaveforms Obtained Appîying (EQ 5) to a Three-Phase System during
Balanced (a) and Unbalanced (b) Operation
Block diagram of the system concsponding to 46) is shown in Figure 26. It nalizes ACDC
conversion theontically without ripplcs and dlows disturbûnce detection in each phase
separate l y.
FIGURE 26. UndervoHage/Ovewoltage Detection Method Using (EQ 6)
To incorporate this system in the laboratory prototype of ihe static transfer switch, the
realization of a -90' phase shifting is needed. In the DSP board this can be achieved by
impkmenting an all-pass digital filter with a 90" phase delay i.e. Hilbert transformer. An attempt
to implement such a filter in the actual xtup nsulted in a significant nduciion in the sample rate
because of the high order of the filter. Thercfore an alternative approach was sought.
One way to detcct an abnormal condition in each phase separately is to calculate in the DSP
the amplitude or mis value of the supply voltage directly at each sampling instant as follows:
Vi = si/ sino>ti (EQ 7)
where si is the sarnpled value at instant ti .The dnwback of this approach i s that the function
sinot yields zero at each zero crossing of the sampled signal. Then are also numerical problems
close to the zero crossing since the denominator in (EQ 7) approaches zero. Thenfore. to
implement this'detcction method, a "window" must be established in which rcliable results cm k
obtained. In the vicinity of zero mssing it cannot be used.
Another way is to integrate the sampled signal over hrlf a period. calculate the average
value and compare it with the teference value. Detcction time in this case is half a cycle of the
supply voltage. although it may be reduced to a quuier of cycle using the following property of
a sine function:
According to (8) a sampled signal is integrated over each qumer of a cycle. After thüt the
average value of the signal is calculated and compared with the reference value. The integrating
block is reset and a new integration period stms (Figure 27).
Thus. the calculated average voltage is compared with the reference voltage four times over a
cycle at the instants: r/2, +. 3x/2. 2ir. Also. to satisfy the requirements of the CBMA curve
(Figure 4), an additional block for instantaneous detection is built in. It performs ABC to apO
transformation and calculates the magnitude of the line voltage space phasor. If it is more chan
100% or less than 50% with respect to the reference value. command to transfer is issued
immediately . The operational characteristic of the detection system is plotted in Figure 28. The solid
line indicates the "best" case of detection in which a disturbance is detected within a quarter of
a cycle. The dashed line repiesents the "worst" case of detection which is half a cycle. This
happens when a disturbance begins somewhere within the integration period such that it does
not result in sufficient enor obtaincd during this pcriod. Hence. it can be detected only after the
next quarter of cycle
The integration-reset mehod is the most robust among ail considered and involves
minimum computaiiond efforts using the trapemidal rule of intcgration with a step equal to the
sampling period. -. In addition it allows one to distinpish between abnomai conditions and
momcntary voltage spikcs or short-term transients. Abnomal condition can be detected in each
phase sepamtely. Thenfore. the integrationiesct rncthod was findly implemented for
ovcrvoltagdun&rvoltagc detection in the actual setup.
FIGURE 27. Integrationdeset Method
0.24 0.5 0.73 1.0 1.25
time in cycles
FIGURE 28. Characteristic of Under- and bveivoitage Detection Systern
4.6 Load Transfer Strategy
The main automatic transfer techniques for major rotating machinery loads summarized in
Section 3.3 are Fast. Slow, Parallel, Residual Voltage and In-Phase methods. Although each
method has its advantages and disadvantages the universal solution is to transfer ;is fast as
possible. This ensures power supply continuity for essential Ioads and minimizes transients on the
ioad bus during the transfer. However. it is also important that a fault on one source does not
disturb loads of the other source. In this case no overlap of the supply systems is allowed. Al! of
these requirements can be met by gating thynston pmperly.
Generally, STS thyristor gating methods faIl in two categories, as outlined in Section 2.2:
conventional gating;
selective gating.
The first method may result in subcycle overlap depending on the disturbance type and operating
point while the other one always provides nonoverlapping transfer. Therefore, in order to prevent
fault back-feed from one source to another. selective gating was used to implement loûd transfer
on the laboratory prototype of STS.
According to the selective gnting method, only that thyristor of the incoming source switch
is gated immediately after a disturbance is detected. which can prevent supply systems from
overlapping or comrnutate with cumntly conducting thyristor of the other switch. Its antiparallel
counterpart is turned on only after the load is isolated from the previous source. In the STS
control algorithm this is done by checking the polarity of the current during the transfer. If the
line cumnt is positive. then the thyristor which conducts during the positive half-cycle of the
incoming source is gated immediately. If the line cumnt is negative, the thyristor which conducts
during the negative half-cycle of the incoming source is gated immediately.
To guarantee a nonoverl.apping transfer, the mans should bc provided to detect thyristor
tum-off. In the actual senip this is done by monitoring the line cumnt. if the cumnt drops below
a holding level, which is 250 mA for the givcn device, then the thyristor loses its cumnt latching
capability. This condition solely docs not ensun the tum-off state of the device since a certain
amount of time ton is rcquind to remove excess carriers and then dlow the device to .kcovcr its
fonvard blocking capability as shown in Figure 29. If a fonvard bias voltage i s reapplied to a . thyristor, which is being tumed off, ai the moment t c ta,,--. it will be turned on again. This
results in subcycle overlap of two supply sources as illustnied in Figure 30. For the actual
thyristors the tum-off time toj, is specified to be 100 p. Thercfore, since the sampling period
T,,,, in the control program is 189.3939 p S. ihen one sampling period delay after the current
in the device drops below holding level would be long enough to ensure the thyristor's tum-off
state. But due to the implemented digital filier the sampled signal is delged by 2 sampling
periods. Hence, the tum-off state is reached when the filiered current is less then the holding
current because the necessary delay is already introduced by the filter. At this instant the load
is completely isolated from the previous source.
If an abnormal condition and operational point of the STS results in commutation
between thyristors on each source side, the served load undergoes an almost "seamless"
transfer. However, in the opposite case there will be sorne "dead" time caused by power
interruption. This is because of the necessity to prevent overlap and due to the imprecision in
thyristor mm-off state detection. Since the sampling process is not synchronized with the
signal the "dead" tirne can be as long as 3 sarnpling pends which is 0.568 ms in the worst
case. This is the limit. obtained by a trial and error method, providing non-overlapping transfer
in the actual laboratory setup. To =duce the dead time, more sophisticated instrumentation is .
required. But this makes the system bulky and costly. The control system implemented in the
laboratory prototype of STS incorporating intcgration-met fault detection method and
selective gating of thyristors during the &ansfer is illustrated in Figure 3 1.
1 1 Turn off timc t,,, 1 I fl '!
FIGURE 29. Thyristor Voltage and Current Wavefoms during Tum-Off
Load Transfsr Due to Undsniobge with ûwriap
FIGURE 30. Failure to Ensure Thyristor's Tum-off State results in a Suôcycte Overîap
Lord Trrnrfu Stntogy
' I I I
4.7 Conclusions
This chapter outlined important aspects of the laboratory prototype of Static Transfer
System development. The functional characteristic of the systcm and the rating of the main
components are provided. Principal features of the STS controller as well as gating and
sensing equipment are introduced.
The method of undervoitage/overvoîtage detection is crucial for reûl izing high speed of
sw itch operation, therefore it is addressed in panicular. Several methods for undervol tagel
overvoltage. among them those implernented in real static tnnsfer switches are described in
Section 4.5. Each of them has its advantages and disadvantages. Considering the available
control and instrumentation hardware, the integration-reset method was finally selecied
because of its robustness and reliability.
Rarultm of Lwpdnnritil hat8 of th . bvalopoâ C.bamtoy Prototype of Strtic Tnndw Sylam.
CHAPTER 5
Testing and Evaluation of Static Transfer System
5.1 Results of Experimental Tests of the Developed
Laboratory Prototype of Static Transfer System.
The developed prototype of a static transfer system was subjected to a number of
experimental tests involving various loads and abnormal conditions which caused a transfer. The
purpose of these experiments was to study the performance of the static transfer system during
load transfer. to determine the maximum transient on the served load and to identify the potential
problems and methods of their elimination. Two categories of load were used in the studies:
passive (resistive, inductive) load;
induction motor.
Specific tests were selected to provide a complete picture of the static transfer system
performance. This chapter presents the selected tests and follow-up evaluaiions.
5.1.1 Resistive Load Transfer Resistive load transfer was the fint full-scale test perfonned on the laboratory prototype to
check the propemess of systern operation under practical abnormal conditions. The sets of
obtained results are plotted in Figure 32.
Figure 32a illustrates the resistive load R = 12 SL transfer to the altemate source due to an
undervoltage which was implernented by reducing the prefemd source voltage with a laboratory
transfomer below 0.9 p.u. The plotted data npresent thrcc line currcnts and phase A voltages of
the prefemd and altemate sources respeaively. An abnormal condition was detected and transfer
initiated at t = 0.018 sec on the cumnt plot. Because of the load cumnt direction and type of
disturbance, transfer prmess is completed instantaneously as a result of commutation between
thyristors in each phase.
Figure 32b illustrates an opposite case to the previous one. The transfer process is initiated
due to an overvoltagc on the prefemd source which was implemcnted by incrcasing the supply
voltage with the laboratory transfomm above 1.1 p.u., although, it is not accomplished '
instantancousi y.
- 2 .s 1 I O 0 . 0 0 5 0 . 0 1 0 . 0 1 S 0 . 0 2 0 . 0 2 s 0 . 0 3 O . O 3 5 0 . 0 4
tirna ( s o c )
FîGURE 32. Resistive Load Transfer
Reaulta of ErprlnmW T ~ B of th. ûovdopd Libontory Prototype of S W c Tnnakr Syatm.
Because of the load cumnt direction md type of disturbance. there is no commutation between
thyristors. Hence. each phase is transferred sepantcly after the cumnt zero crossing. The transfer
process is completed after 0.005 sec from the moment of its commencement.
To test the sensitivity of the static transfer system to disturbances in one phase only. a
voltage sag was caused by inserting a series resisior 10 Q in phase A. Voltage dips to 0.7 p u . at
r = 0.01 sec in phase A. as seen in Figure 32c. although it is detected at t = 0.01 5 sec. For this
particular case the transfer process is instantaneous. Upon completion of transfer. the voltage of
the faulted phase is restored because there is no cunent flow.
Another common type of asymmetrical fault is loss of one phase of a power source. The
behavior of the transfer system dunng this fault was studied by subjecting it to a loss of phase B
of the prefemd source. Obtained results are plotted in Figure 32d. Phase loss occurs ai
t = 0.0 17 sec. It is detected at t = 0.02 sec. Again. the transfer process is instantaneous.
Figures 32a-d illustrate idealized cases of transfer. As the served load is pure resistance. it is
transferred "seamlessly". No transients wen obsewed during and after the iransfer.
5.1.2 R-L Load Trader
Since the majority of industrial loads are resistive-inductive in nature, the second set of
tests was performed on this particular type of load. It consists of a resistor R = 12 Ci, and an .
inductor . L = 25.3 mH. Thus. the cumnt is lagging behind the voltage with an angle 38' . This
is a typical case of a passive R-L load with a power factor coscp n 0.8. The performance of the
static transfer system is similar to that with a pure rcsistive load. In case of an undervoltage on the
prefemd source. the load is transferrcd with commutation between thyristors in phases B and C,
as shown in Figure 33a If an overvoltage mon than 1.1 peu. occurs on the prefemd source. the
load is transfemd to the altemate source phase-by-phase after the zero crossing of the prefemd
source's cumnt (Figure 33b). Because of the selectivc p i n g of thyristors in semiconductor
switches. then'is no overlap of the systems and no overcunents. Abnomal condition on the
prefemd source does not disturb loads suppliexi from the ditmate soua.
Fipm 33c illustrates the R-L load tramfer to the alternate source due to voltage dip to 0.6
peu. in phase A of the pnfcned source.
FIGURE 33. R-L Load Transfer
While the transfer in phases A and C is instantancous. in phase B it occurs only after a zero
crossing of the prefemd source's cumni.'lhe tnnrfer process is completed after At s 0.6 ms
from the moment of its commencement.
One of the most disturbing load abnonnd conditions is r complete loss of a power source.
Performance of the system for this case is illustnicd in Figure 33d. The preferred source is lost
just before the zero crossing of the phase B currcnt. Sincc ii cumnt through an inductor cannot
change instantaneously, phaxs A and C yc si i i i conducting the load current. The fault is
detected with a delay At = 3 ms. which is approximately 65 electrical degrees. This is well
within the "ride through" limiü of major sensitive clcctronic equipment.
5.1.3 R-C Load Transfer
To study static transfer system performance during the transfer of loads with leading
power factor, a number of experiments was performed on an R-C load. In the example of Figure
34. the load consists of a resistor R = 6 fi in series with a battery of capacitors C = 250 pF.
Thus. the cumnt leads the voltage at an angle 60'. If an undervoltage occurs on the preferred
source, the load is transferred instantaneously as a result of commutation between thyristors. as
shown in Figure 34a. However, in case of an overvoltage. the load is not transferred to the
altemate source until zero crossing of the prefemd source current, as shown in Figure 34b.
Therefon, the transfer pmcess takes At = 15 ms from the moment of its commencement.
Fiprc 34b shows. that during the transfer interval the served load may draw cumnt from both
power sources (phases A and B). Although, due to selective gating, current flow from one
source to another is effectively blocked. This minimizes transients during the load transfer.
Figure 34c illustrates the load transfer due to voltage sag to 0.7 p.u. in phase A. An abnormal
condition occurs at t, = 17 rns. It is detccted at t = 21 ms. Phases B and C of the load are
transferred instantamously, while phase C is uansferred only after the current zero crossing.
Again, there is no considerable disturbances to the load during ihc transfer.
Figure -34d illustrates the transfer system performance when the prefemd source is
completely lost. A fault is detccted after At = 3 ms. However. in the beginning of the transfer,
the thyristor of phase B does not turn on because it is reverse biased. It tums on only at
t = 25 ms with a momentary cumnt overshwt.
. v ..... ....... ; ........ .W. . ;'?evf. .. :. ..... ;. ..... .:. .:. .... i
0 O .O O S O . O 1 0 . 0 1 S O . O 2 0 . 0 2 5 O .O 3 0 . 0 3 1 O . O 4 I i m o ( r o c )
FIGURE 34. R-C Load Tmnsfer
Peak cucrent reaches almost twice the steady state value. But the transicnt decays very fast.
Already at t = 28 ms. the normal power supply for the load is restored.
5.1.4 Inductive Load Transfer.
This test is unique in a sense that it gives an insight into the static transfer system
behavior during transfer of an almost purely inductive load. The served load is an inductor
L = 35.1 mH. Its resistuice is negligible in cornparison to its inductance. Due ro an iilniost
90 degrees phase shift between currcnt and voltage transfer conditions in each phase differ
fmm those in the case of an R- or R-L load. as shown in figures 38 a, b. In addition this
particular load is poorly damped, and it takes a much longer time. before steady state
operation is attained. Experimental results showed. that the transient penod may last for
about 7 cycles.
The conducted tests demonstrated, that the developed prototype of a static tnnsfer
switch has proved to be a very effective means of maintaining power for different types of
passive loads. They also verified proper operation of the implemented control algorithm. The
served load is transferred to the altemate source in the event of any disturbance on the
pnferred source within tolerable time limits. The transients during load transfer are
minimized.
a) Imbdvm Lord Tmnder Due to Undrrvdirgo on the P d e m Soum
! . . . ....... O
b) IncbcUva Lord Tmndar Due to Ovewdtigs on tha P r o k m Source
- c) Inducihm L W Tmihr Dur to Vo)tige Sig in P h r e A
1 1
t . a . . . . ....... !
O O . O O 5 0 . 0 1 O . O 1 5 O . O 2 O .O 2 s O . O 3 O . O 3 5 O . O 4
flOURE 35, Inductive Load Transfer
5.1.5 Motor Load Transfer
The performance of the laboratory prototype of a static transfer system during transfer of
active (i.e. energy storage) loads was studicd using a 5-hp (3.725-kV) I IO-V three-phase
induction motor. Parameters of the equivalent circuit of expcrimental machine are given in
Appendix D. The system was subjected to the s m e type of the disturbances as in the previous
cases. The experimental induction motor operated under rûted conditions. A separately excited
DC motor was used as a loading machine to provide constant load torque. Selectzd tests results
are illustrated in Figures 36-39. where experimental data is represented in per unit values for
greater convenience.
Figure 36 shows the induction motor transfer due to a voltage sag in phase A. Momeniary
voltage sag to 0.8 peu. was rnodeled by inserting 1 R series resistor in phase A of the preferred
source circuit. The fault occun at t = 0.1014 sec. as seen in the figure. The undervoltagel
overvoltage detection logic recognized the abnormal condition at t = 0.1044 sec or 65
electrical degrees later. The transfer process occurs alrnost instantaneously. The initiai peak
cumnt in each phase does not exceed 1.5 times the rated cument.
Figure 37 shows the induction motor transfer caused by loss of phase B of the preferred
source. Phase loss occurs at time t = 0.05 sec. It is detected at t = 0.0522 sec or 47 electrical
degree later. Load transfer in al1 t h e phases is accomplished with commutation between
thyristors of the pnfemd and altemate source. The overall detection and transfer time is 1.1
msec. Again, peak current aftcr the transfer does no< exceed 1.5 times the rated current.
Figure 38 illustrates an example of an induction motor transfer due to the complete loss
of the prefemd source. A fault occua at t = 0.0536 sec according to the voltage plot. It is
detected instantaneously. Transfer in phases A and C is accomplished as a nsult of
commutation between thyristors, while in phase B transfer does not happen until the prefemd
source current falls to zero. Although the induction motor under test was subjected to a very
severe disturbance, fault detcction and transfer occurs so fast that the phenomena described in
Chapter 3 not observed. The transfer process is accomplished without significant
overcumnts. This can be bctter obsemd in Figun 39, where amplitudes of the stator cumnt
space vector as well as pnfemd and Plternate source voltages are plotted versus time.
O - 1 2 O . I 4 0 . 1 1 O - 1 8 O - 2 O - 2 2 Hm, sec
FIGURE 36. Induction Motoi Transfer Due to Voltage Sag in Phase A
- t . s 1 O O . O 5 O . I O . l 5 O . 2
Hm, sec
FlGURE 37. Induction Motor Transfer Due to Loss of Phase 6
FiGURE 98. Induction Motor Transter Due to Loss of Prefened Source
Space vectors of the measured values are obtrined in the stator fixed frame using (EQ 4).
This figure illustrates another example of motor transfcr when the preferred source is lost
completely. The initial peak current in this case is 1 .S times the rated current. and the
transient process lasts 22 mec.
time, (sec)
flGURE 39. Induction Motor Behavior dunng Transfer to the Altemate
Results of the experimental tests an summarired in Table 2 .
Source
TABLE 2.
LOSS of One 1 0,003 1 Phase
Overvol tage l Voltage Sag in ( O,m5 ~ One Phase
Transfer Timeqsce
0.0006
0.005
ferred Source Loss Of 1
Total Time, sec
-
*
Disturbmce
Undervoltage
Overvol tage
Fil!urr
32a I
32b
L
Voltage Sag in 1 One Phase
Detection Ti
-
-
I
C-
h d L
Resistive Load
Loss of Pn- 1 *,W*, ferreci Source
Voltage Sag in OnePhlse 32c
I
~ o l t a ~ e Sag in1 Ont Phase
, I
7-
s s O 1 1 fernd Source
TABLE 2.
*
Load I
Motor Load
Fipre
36
37
38
Disturbance
Voltage Sag in One Phase
Loss of One Phase
Loss of Pm- femd Source
Detec tion Tirne,
0.003
Transfer Time, sec
0.006
0.008
0.0037
Total Time, sec
0.009
0.0 102
0.0039 1
5.2 Digital Tirne-Domain Simulation of Induction Motor
Transfer Although the developed laboratory prototype of the static transfer system proved to bc a
very useful tool for studying the ôehavior of a real static transfer switch dunng transfer of power
to major practical loads, it has the following limitations:
disturbances cannot be üpplied at a certain. prcdetennined time by the user;
short circuit tests cannot be conducted since they might affect other loads. connected to the
sarne power supply line and because of safety considerations.
Therefore, further studies were performed by computer simulation of the developed system. The
need for computer simulation was dictated also by the impossibility io make conjecture about the
worst case scenario for the transfer and to reproduce it in al1 details on the laboratory prototype.
Among al1 of the commercially available power system simulation software packages
PSCAD/EMTDC [18] was chosen. This package provides a very flexible graphical interface to
electrornagnetic transients simulation program, a built-in library of power system component
models and procedures as well as plotting and analysis tools for convenient representation of data
generated by simulation. Thus, it is a very suitable software to handle problems studied in this
thesis.
PSCADIE- library provides components which allow one to build various practical
analog control systems. However. in the STS laboratory prototype digital control was used. It
rnight seern, that this fact requircs developrnent of a customized rnodcl of the irnplernented
digital control to make expcrimcnt and the simulation results compatible and comparable. On the
other han& any analog component is npresentcrl in EMïDC by its digital indel. Therefore it is
truc to say that if the tirne step of the digital simulation of a continuous time system is equal to the
sampling period of a real m p l e d data system performing the sarne control algorithm.
comparison ktween thcm can be made. This is of course tnie if sarnpling period is small enough.
so that the simulation timc step of the s u m value will not cause numerical problems. Since the
sampling priod used in the UHP-40 to pcrfomi control of the STS labontory prototype is as low
as 189.394 p, the above assumption is justifiai. Thus, the simulation time step was chosen to k
equal to the sampling pend and EMTDC libiary components w m used as building blocks to
60 80 time, sec
O ICI 0 ta
Figure 41. Simulation of the Induction Motor Tnnsfer Due
create the simulation mode1 of the STS control system. With exception of the digital filter the
implemented control system was accurately modeled. Since thete is no such phenomenon as EMI
noise in cornputer simulation. there is no need to filter out measured signûls. Though, to account
for time delay introduced by the filter, i first-order delay bloc k from EMTDC library was used.
Figures 40 and 4 1 provide simulation results of the induction motor transfer under the same
conditions as those illustrated in figures 36 and 38. As seen. simulation results are very close but
not exxtly the same as in the experiment. The differenccs c m be explaincd by the impossibility
to reproduce in simulation the exact real situation because in the laboratory prototype of the STS.
line voltages, sampling and fault events are asynchronous with respect to each other, whereas in
the simulation everything is synchronized with the time step. Although. without loss of generality
simulation can be used to study performance of the laboratory prototype of STS during induction
motor transfer.
5.2.1 Results of Undervoltage and Loss of Power Supply Simulation This simulation was performed to study the relation between maximum transient current in
the motor and the instant at which the abnorrnal condition occurs. This allows one to identify the
worst case condition for the motor to be transferred. The absolute value of the induction motor
s p r e phasor current was chosen as a criterion determinhg the severity of the transient. Since
supply voltages and currents are priodic signals it is enough to limit the snidy interval to one
pend of the supply voltage or 0.0167 sec. The transfer system will operate in the same way
anywhen beyond this time interval. Also, to guarantee a systematic simulation approach, the
system was subjected to disturbances at equidistant moments of time (At = 570 psec) on this
interval. In the viccinity of extrema this time resolution was increased to find the maximum or
minimum values. ksults of the simulation are pnsented in the fonn of plots in Figure 42. Circles
on these plots denote the absolute value of space phasor of the initial stator peak cumnt caused
by a transfer to the altemate source if the fault occurs on prefemd source at time t. One period of
phase A voltage was arbitrarily iaken as the interval of study, i. e. v,, = O at t, = O . Prior to
transfer the motor was operating at rated conditions.
As seen fiom the plots. the simulation results do not reveal any discrepancy as compared to
those obtained in the experiment. The initial peak stator cumnt varies between 1.4 and 2.2 p. u.
and two phases-to gmund shon circuits. According to actual simulation results. the initial
stator peak cumnt reaches up to five times the rated cumnt.
Loss of Phase A
O 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018
Loss of Phases A and B
Loss of Prcfemd Source
depending on the type of disturbance and the moment of its occurrence. Although intuitively one
would expect higher transients in the case of a complete loss of power supply. in fact they are
lower as compared to those in the case of one or iwo phases k i n g lost. This is because the
implemented control logic detects a supply source loss mon quicker. Another interesting
phenornenon which can be observed from this figure is the periodicity of the results. In the case
of a symmetrical fault such as the loss of a supply source. this period tends to be 116 times the
voltage period, which is explicable for a three-phase system.
5.3.1 Results of Short Circuit Fault Simulations
Similar io the studies described in the previous section, the simulation of short circuit faults
was performed and the behavior of the static transfer system was investigated. This simulation is
of particular importance since no such tests were performed on the laboratory prototype of STS.
The results of short circuit fault simulations revealed different STS performance as compared to
that in the previous section. Figure 43 illustrates the example of an induction motor transfer due
to a three-phase shon circuit on the preferred source. As seen in the figure, the difference in the
system behavior is caused by induction motor currents changing their direction immediately after
the fault. This is due to the fact that mechanical energy stored in the spinning shaft of the motor
does not dissipate instantaneously but acts as a prime mover thus turning the induction motor into
a generator which delivers substaniial amounts of power to the fault. Thus, if in one of the phases
a change in the instantaneous current polarity was expected shortly k f o n the fault. this would
not happen. On the contrary. cumnt starts to rise again prcserving its sign, as can be observed
from the plots of phase B and C cumnts shown in the figure. As a consequence. one cumnt zero
crossing is missed. Comspondingly, if die transfer in this phase is accomplished after a cumnt
zero crossing, it is delayed. During this delay significant fault cumnt flows. The worst situation
aises when fault occurs just beforc a cumnt zero crossing. in this case transfer is delayed by
almost half a cycle.
Dependence of stator pcak cumnt from the type of fault and instant at which it occurs is
plotted in ~ i g u k 44. It can be observed. that the most severc types of faults are three-phase and
two phases-to ground short circuits. According to actual simulation rcsults, the initial stator peak
cumnt naches up to five times the ratcd cumnt.
a VC1 0 ICI A I c 2
Figure 4 1. Simulath of the Induction Motoi Tmfcr Duc
to aTbiise-Phase Short Circuit
6 Phases A and B to Ground Fault
I I 1 1 1 I 1 I ,
Fault Between Phases A and B
Phase A to Ground Fault
- 0 0.002 0.001 0.0080.008 0.01 0.012 0.014 0.016 0.018
-. Fault Occurrence Instant, (sec)
FIGURE 44. Maximum Stator Peak Current as a Function of FauR Instant
5.3 Conclusions Experimental tests conducted on the labontory prototype of the Static Transfer Switch
as well as computer simulations dcmonstrated quite satisfacrory system performance during
transfer of common industrial loads due to typical disturbances.
Motor load transfer due to under- and overvoltages or loss of power supply occurs so
Fast that transient are minimized. Negative phenornena descnbed in Chapter 3 were not
observed. The highest value of overcumnts cruscd by a transfer is ûpproximately 2 times the
rated fùll load cumnt. In fact. system behavior during transfer of the experimental motor
does no< Vary considerably from that during transfer of a passive inductive load.
In the case of short circuit faults and an induction motor load, a different STS
performance was observed. Immediately after the fault. the stator cumnt changes its
direction providing additional power to the fault spot. This may lead to the omission of a
cumnt zero crossing in one of the phases. As a consequence. transfer in this phase will be
delayed until the next cumnt crossing or until commutation between thyristors is possible.
Maximum delay in one phase can be almost half a cycle. However. the overall transfer time is
still less then a cycle.
CHAPTER 6
Conclusions and Proposals for Future Studies
6.1 Conclusions
The study conducted in this thesis dernonstnted that one of the most cost effective ways
to pmvide unintemptible power to critical industrial loads is to use a Static Transfer Switch
(STS). Its performance dunng the transfer of viuious static loads and particularly an induction
motor load was investigated on the developed laboratory prototype and with the help of digital
computer simulations. The following observations were made during the studies:
Load transfer by STS is accomplished either as a result of commutation between thyristors
or with temporary overlap of the prefemd and altemate sources. In the f i n t case smooth
transfer is usually achieved. However, in the second case significant overcurrents may
arise depending on the type of fault and the system's parameten. To avoid these overcur-
nnts, transfer shouid not start until a cumnt zero crossing is detected.
Selective gating of thyristors in the STS dunng the trmsfer prevents overlapping of the
sources while preserving high spced of the operation. Thenfore, loads supplied from the
sound source are not disturbcd by faults on the other source.
An integration-Reset fault detection method implemented in the laboratory prototype and
in the computer simulation proved to be very robust and diable.
Experimental tests and simulation ~ s u l t s of the 5 hp induction motor transfer during
under- and ovcrvoltages, unbalanctd conditions and loss of power supply dcmonstrated
that the process is accompished in reasonable time so that associated transients are Mn-
imizcd.
Transfer due to short circuit faults was found to be the most scvere for the induction
motor. m e uansfet process is delayed in this case by almost half a cycle. resulting in an
initial stator pcak cumnt of up to 5 times the ratcd cumnt. This is comparable to inrush
cumnt values dunng start-up and therefoie still within tolerablc limits. Duc to good .
damping, the transient current decays very quickly.
6.2 Proposals for Future Studies
The scope of the cumnt work included the study of the Static Transfer Switch operating
principles. the development of the STS laboratory prototype. expcrimental tests of the static
and induction motor load transfen and the computer simulations of the induction motor
transfer and its verifkation. Complete answers were obtained on the behavior of the STS
during transfer of a single induction rnotor in ternis of the speed of operation and maximum
transients. although, the studied single-machine case is somewhat idealized. Most of the
practical systems include transfomers which like the electric machines represent an active or
energy storage load. if there is residual magnetism in the core of a transformer at the instant of
voltage reapplication and this residual flux possesses an opposite polarity to the normal flux
which the transformer would rather have. then significant innish current will flow. Therefore.
to make the study case more redistic. the transformer should be taken into consideration.
' Most of the real motor loads are not homogeneous. i. e. they do not consist of one or a
group of the same machines. but rather a group of different machines or even a mix of motors
and static loads. Although interaction between different motors in the group is not expected
due to the high specd of transfer. static loads may mitigate transients cauxd by short circuit
faults absorbing a part of the energy supplied by the motor to the fault.
A more elaboratc picturc of the Static Transfer Switch performance can only be
obtained by studying a reai system, e. g. power plant auxiliary system. This can be effectively
done by computer simulation since the simulation results reportcd in the work wcll agree with
experiments.
References
1. J. D. Jill. "Transfer of Motor Loads Between Out-of-Phase Sources".
EEE Trans. on Industry Applications. Vol. 1 A. 15, #4. JulylAugust 1979,
pp. 376-38 1.
2. S. S. Mulukutla. E. M. Gulachcnski. "A Critical Survcy of Considerations
in Maintaining Process Continuity During Voltage Dips while Protecting
Moton with Reclosing and Bus Transfer Practices", IEEE Trans. on
Power Systems, Vol. 7. #3. August 1992. pp 1299- 1305.
3. J. Reynaud. P. Pillay. "Reclosing Transients in Induction Machines
Including the Effects of Saturation of Magnetizing Branch and a Practical
Case Study", IEEE Trans. on Energy Conversion, Vol. 9, # 4. Iune 1994.
pp 383-389.
4. R. Probst, "Übergangsverhalten von Asynchronmotoren bei Netzum-
schaltung unter Berücksic hiigung der S tromverdrangung in den Laü fer-
staben". ETZ Archiv, Vol. 94 (1973) H.9, pp 5 15-520.
5. M. Abbe, bTransientes Verhaiten von Asynchronmotonng~ppen bei
Spannungsunterbrechungen", ET2 Archiv. 1979 H.3. pp 83-86.
6. M. Abbe. "Digitde Simulation von Asynchronmotorengruppen bei Net-
zumschaltungen", Archiv fUr Elektrotechnik, 62 ( 1980).
7. S. Sriharan, L.H. Tan, H.M. Ting, "Reduced Transient Model of a Group
of Induction Motoa", IEEE Trans. on Energy Conversion, Vol. 8. # 4,
Dcccmber 1993, pp 769J77.
8. R. D. Pettigrew, P. ~owell, "Motor Bus Transfer", . IEEE Trans. on Power
- . Delivery, Vol. 8. # 4, October 1993, pp 1747- 1758.
9. A. Higgins. P. L. Young, W. L. Snider. H. J. Holley, "Report on Bus
Transfer. Part 1-3. IEEE Trans. on Energy Conversion. Vol. 5. # 3. Sep-
tember 1990. pp 462-484.
10. S. Mazumdar, M. Chiramal, "Bus Transfer Practices at Nuclear Plants",
IEEE Transactions on Power Delivery. Vol. 6, #4. October 1991. pp
1448- 1443.
1 1. T. Masaki, Y. Kataoka. M. Ono, Y. Yokoi, "Development of Static Trans-
fer Switch Equipment for Different Distribution Systems". IPEC Yoko-
hama 95, pp 1588- 1593.
12. K. Matsushita, Y. Kataoka. M. Ono. "High Speed Switchgear Protecting
Power Generating Facilities against Voltage Dip and Interruption". E E E
Catalogue U95TH8025. 1995, pp 726-73 1.
13. W. Schartzenberg, R. W. De Doncker, " 15 kV Medium Voltage Static
Transfer Switch", EEE Industry Application Society. 30th Annual Meet-
ing, 1995, pp 25 15-2520.
14. D. C. Griffith, "Unintemptible Power Supplies", Marcel Dekker, 1989.
15. .S. Krebs, "UHP-40 User's Manud", University of Toronto, Power Group,
1995.
16. A. Oppenheim, "Digital Signal hocessing". Prentice-Hall. 1975.
17. N. Mohan, T. M. Undeland, W. R. Robbins, "Power Electronics", John
Wilcy & Sons, 1995.
18. PSCAD/EMTDC, Manuals, Manitoba HVD<J Rescarch Centre, 1993:
r i u n r d lonq d a t ~ l . d a t ~ 2 . a L l t . r p . .Ut-. 4 d J t r m p . a L 4 t . q ~ static i n t coun tg* - 0. c o u o t ~ J c - 0 , c o w i t ~ - c a 0 ; r t a t i c i n t c o u n t . b - 0, c o u n c ~ c - O, c o u n t ~ c a - O ; n t a t i c i n t p-to-a - 0, ~ t 0 - p - O , narm = 1. a8aorm - 0: n t r t i c f l o a t v l - a b ~ ~ e v - f - 0.0, v l 4 c g t e v - f = 0.0, vl-cwrmv-f - 0.0; 8 t a t i c f lait ~ 2 - 4 b ~ r . v - f 0 .o. ~2-bcgr .v-f 0 0 . O , v ~ , c w ~ w , ~ o. O ; r t a t i c f lomt e p i i l o n = 0.0, c o r r g - a b = 0.0. c o r r g g c - 0.0. c o r r g s r = O . O ,
corr- ab - 0.0. corr-a-bc - O . O , c o r r - ~ c a 0. O I s t a t i c f l o a t i l - w r e v i l - (0.0, 0 .0, 0.0. 0.0. 0.01: r t r t i c f l o r t i l J~ ,p revI l - IO.0, 0 .0, 0.0, 0 .0, 0.01; r t a t i c f l o a t i l - c g r m v l l - (0.0, 0.0. 0.0. 0.0, 0.01; n t a t i c f l o a t i l ~ r * v [ ] - ( 0 . 0 , 0.0, 0.0, 0.0. 0.01; a t a t i c f l o a t i 2 , p g r e v l l - (0 .0 , 0.0. 0.0, 0.0, 0.011 r t a t i c f l o a t i2 ,cgrevlI - 10.0, 0.0, 0.0. 0.0, 0 ,O); u t a t i c f l o a t vl ,abgrev[l - [O.O. 0.0, 0.0, 0.0, 0.01; r t a t i c f l o a t v l J ~ g r i v [ l = 10.0. 0 .0. 0.0. 0.0, 0.01; i t a c i c Cloa t v l - c w r e v i l - (0.0. 0 . 0 , 0.0, 0.0. 0.011 r t a t i c t l o a t v 2 - a b g r e v [ l - I0.0, 0 . 0 , 0.0, 0.0, 0.01; r t a t i c f l o a t v 2 ~ c g r e v ( l - (0.0, 0 .0 , 0.0, 0.0, 0 .01; r t a t i c f l o a t v 7 , c ~ r e v l l = (0.0, 0 .0 , 0.0, 0.0, 0.01; n t a t i c f l o a c bI1 - 10.0, 0.0746, 0.2344, 0.46l21, 0.7344, O.O746l; /*diqtcal f i l t e r c o e f f . * / r t a t i c f l o a t vl,trap& - 0.0, v1,trrpJc * 0.0. vl,trrp,cr - 0.0: r t a t i c f l o a t v2,trap-~b = 0.0. v2,trapJc - 0.0, v2,tr.p-cr - 0.0; i a t i ;
/ * A/D & t a acquisition * / data-1 - f r l r o r d l l l t d a t a - i r c u o r d (1 : a L l t . a i 9 = ( ( d a t u i OxOOOOffff) ** 161 i Oxffff0000; r u t - - I (data-1 r Owffff0000) 1 ; 4 U t m m p = ( ( d a t k 2 i Ox0000ffff) << 16) i OxfLttOOOOr .tut- ' ( ( d a t a i O x f f f f 0 0 0 0 ~ ) ; A u ( f h ~ t l adJtUUQt r u - ( f l o a t l rL1taaig; r L 3 - t f l o a t l acl3t.mg: a L 4 - ( f l a a t ) rtL4tmnp;
/ a p r e f e r r e d r o u r c e l i n o - t o - l i n e v o l t r g d r * / vl-ab œ 5 .O ad-1 / ( IriTJ(AiCFL0AT) : vlJc - 5.0 a u / I I K F ~ M A T I ; v L c a = . (vl-ab + v l h c ) ;
/ a a l t e r n a t . s o u r c e I f n i - t a - l i n * v o l c r g e r ./ v L a b - 5.0 a L 3 / t I N T ' s L O A T ) : v 2 h c - 5.0 - a c l ( / i I N T W L O A T I ; v2,ca - - Iv2,ib - v 2 A c ) ;
/ * A/D 6*t4 a c q u i s i t i o n * / d a t c l - i r l v o r d ( 2 1 I d a t u 0 &-rd (2) 1 adJtaup - î ( d a t k l L Ox0000ffff i << 16) L Oxffff0000; a L 2 t . m ~ ' ((data-1 r O x f f f f 0 0 0 0 1 ~ t a L 3 t a p - ( ( d a r d r Ox0000ffff l <c 16) 6 Oxff ffOOOO t acL4ta rg = ((d4t.J r Oxffff000011; .CL1 = (fl0.t) rdJtIIPg1 .La - (fl0.C) ad.Jt8mp; ad-3 r ( f l o a t l aL3t-; a L 4 - ( f l o a t ) rC4tmmpr
/ * p r e f a r r e d i o u r c a l i n @ cur rmnt r * / i L a 5.0 . .Li/ [IHT3NUU)AT) ; i l b - 5.0 0 r u / tIHFJAXJ'LOAT1 ; i l s = 5.0 . a & 3 / ( I H F m L O A T ) t
/ * A/D a c q u i r i t i o n * / d a t ~ l - i i l u o r d ( 5 1 I d i t e = i ~ w r d ( 5 ) t rL1tmmp - ( ( â a t ~ l r Ox0000fLff 1 16) 6 Oxf t f fOOOO; .ut- = t ( d a t u i Oxf f f t 0 0 0 0 ) 1 ; rd-3~- = ( ( d a t u L OrOO00f f f f 1 *< 16) 4 OxffffOOOOt rd - l t . .~ - ( ( d m 0 r O x f f f f 0 0 0 0 ~ ~ 1 4d-l (fl0.t) ad-lt-I r d 3 - c f l o r t l r43t.rsp: ad-3 - ( f l a a t l a L 3 t r m p t rd-4 - ( f l o a t l aL4trsi0t
/ * a l t e r n a t e r o u r c 8 lin. c u r r 8 n t a + / iL. - 5.0 a m / (XWUNU&ûAT) ; i 2 - b 1 5 .O a u / iXHPlUL?LûAT) ; i L c - 5.0 0 rU/(Xm-TI I
/ * p r e f a t m d nourc8 c u r r a n t s f i l t a r i n g * / i L ~ t a o - i L a b 111 ; f o r (i = 1; i <- 41 i++l i l ~ t a m p - i-tu i U r w [ i I b [ i + l l ; i l cf i â - 8 - t q t / * phare A currrnt f i l c i r a d */ 1-3- - tu b t l l r f o r (i - 18 i <= 4; i+*) i-trq = f a t u + i - rwt i l b i i * l l ; iLbf = i l L t i 9 t / * phare 8 curroat f i l t o n b ./ ii,c,t- - il& b i l1 t
t r l b [ i + l l r f o r t i = 1; i <= 4r i*+) if-c-tump = il-c-tamp i l - cg rev il-c,f il-c,cemp;/* phare C cu r r en t f i l t e rmâ * /
/ * r l t e r n a t e rource cu r r en t r f i l t e r i n g * / i 2 , ~ t a q = il-8 b t l l ; f o r (i = I r i a= 4: i++) i 2 , ~ t i m g = i l - ~ t r a ~ - i2,rgrev i&J = i l , a ~ . a g ; / * phaim A current f i l t e r e d * / i2J-t.r0 = il2 bill; fo r (i = l r i *- 4 1 i+*i i2-b-cemp - i2A-tailp i 2 J g r e v il&-€ - i7-b-craip:/. phare 0 current f i l t e r e d il-c,t.ig - il-c b [ l l ; f o r I i - I r r <= 4; i*+) il-c-cril~ = i2,c-r.ag + i 2 , c g r ~ v [ i l . b [ i * l l r 12-c-f = i7-c,tmpt/* phare C current f i l t e r d * /
/ * p r e f r r r e à source voltaqer f i l t e r i n g * / vl,.b,tamp = vl-ab b l l l ; f o r ( i = 1: i <= 4; i++) vl,a.b,tmp = v l B - r u n g + vl,abgrevti l bIbtr-11 ; vl,ab-f r vl,&b,canigr v U c - t w = v l h c b I l l : fo r [i - Ir <- 41 i++) v l , b c , c ~ vlJc,cuap v l J c g r e v [ r l b [ i * l l : v 1Ac-f = v l b c - t u g t v L c d = . (vl-ab-f vlJc-f 1 ;
/ * a l t e r n a t e source vo l t rqa s f i l t a r i n q * / vl,&-temp = vl-ab b i l l J
f o r ( i = I r i 4; i++) v2-lb-ttag = v2,ab,temp v7-abgrev v 2 ~ b - f = v 2 , ~ ~ c t l ~ g r v lbc- teap = v2Ac b I l l : fo r ( i - 1; i <= 4 ; i**) vlJx,cemp = v2Ac,trmp * v 2 A c g r e v v23c-f - vaAc-camg : vl-CL€ - - (v2-ab,f + va-bc-f :
/ * prefer red rource l i n s - t o - n u e t r a l volcrqer * / vl& = ( v l - c ~ f - vl-ab,f)/3: v1g-f = (vl-ab-f - vlJc,f)/3t vl-c-f = ( ~ 1 - b ~ - f - v l - c ~ f ) / 3 r
/ * a l t e r n a t e source l i n o - t o - n u a t r a l vo l t rqe r * / v L ~ f = ivl-ca-f - v2,rb-f / 3 t v a 4 3 (vl-ab-f - V~JC-c 1 / 3 ; v2-c-f = ~ V ~ J C - f - V ~ , C L ~ 1 / 3 ;
/ * voltage zero crorminq de t ec t i on * / i f ((VI-abgrev,f vl-ab,f 0.0) CC (countg-ab > 5 1 1 councg-ab > 441) 1
counw-ab O:/* countar r e r e t * / vl-ab-trap = 0.0; / * in teqracor r e r e t * / ep r i l on r .vl-ab-f/vl,absrev-f: c o r r u = r p i r l o n . t g - / (1 + epmilon) r rf (corrg,a.b r t-rmp) c o r r a - a b = t -srmgt/* correc t lnq f ac to r * /
1 / * i n r eg ra to r output over O t o p i / 2 * /
if ( c o u n t a ~ b -= 27) 1
ca r rg -ab = vl-ab-f corrg,.b; vl-ab-ave =(vl-ib-trmp - c o r r ~ A ) / (27 U-1 i f ( v l - ab jve 4 0.01 v l 3 - a v m - .vLabIzbavet/* average voltage * / vl-8b-trap = 0.0 ; /* i n t eg ra to r remet * /
1 / * i n t ep ra to r output over p i / 2 t o p i * /
i f (countq-ab =- 41) t
vl,.b,rve = ( v u - t t r p + c o r r s A ) / ( 7 2 u.n01; i f ivl,.b,ave < 0.0) v l a b ~ v e = -vl,lb,.ver/* averiqm voltrqm * / vL.b,crap - 0.0;/* i n t e g r a t o r m e e t * /
1 / * vol tage zero croa i inq detmction a,'
i f ( ( v U c g r e v - f v U c - f <- 0.0) 66 ( c o u n W c + 5 1 1 c o u a w & c 441 I
v14c - t r rp - O,Ot/* i n t eq r8 to r remet * / COUAW-~C = O ; / * counter remet * / epa i lon = - vlgc-f / v l g c g r e v - f t corr-pJc = s p i i l o n t juip/ {l + e p i i l o n ) r i f ( c o r r s J c > t ~ . a p ) c o r r 3 - b ~ = uw;/* c o r n c t i n g f a c t o r */
1 / * i n t eg ra to r output over O t o p i / l * /
i f ( coun lpJc 72) t
c o r r ~ A c = vue-f corr-pJict v l ~ c , r v a = i v l b ~ c r i p - c o r r s J c 1 / (32 U-1 r i f (vl4c-ave < 0.0 1 vlgc-rve = -vlJc,rve; / * avoragr vol tage * / v u e - t r a p = 0.0;/* incoqra tor n i e t * /
1 / * intmqrator output ovmr p i / l t o p i * /
i f t c o u n t g A c -= 4 1 ) (
v U u v m - (v l4c , t r ao + corn-) / (22 Ln-1 r
i f (v1Jc-ave < 0.0) v lhc-ave = - v l ~ c ~ v e r / * avaragm voltage * / v lgc - t r ap - 0.0; / * i n t w r a t o r n i e t */
I / * voltage zaro cror r ing da t ac t i on ./
i f ((vl-clprev-f * v l - cc f <= 0.0) 66 (couow-ca > 5 1 1 countg,c& 4 4 ) ) 1
v l - c ~ t r a p - O . o r / * intmqrator r e i e t * / C O U I l t q , C I = O ; / * countmr remet * / ap r i l on - ~ v l ~ c ~ f / v l , c 4 p r e v ~ f 1 co r rg , ca - api i lon u.aip/ 11 - *** 1 lonl r i f tcorrg,c& s t - 8 ~ ) co r rg , ca - t,a.mp;/* corrictLng fac tor * /
I / * i n t aq ra to r output over O t o p i / 2 * /
i f icounw-ca =- 12) (
c o r r g , c i 0 v l - c ~ f co r rg , ca t v l - c ~ a v a = ( v l - c ~ c r r p - co r rg , ca i / (22 t ~ u n p l t i f ( v l - c ~ a v e c 0.01 v l - ccave = - V I - c ~ a v e r / * averaqe voltage * / v f - c ~ t r a p = 0.0;/* i n t a q r a t o r rmiet * /
1 / * i n t aq ra to r output over p i / l CO p i * /
i f (countg-ca == 41) (
vl-ccave = ( v l - c ~ t r a p r c o r r g , c a ) / (32 t - ~ m p l ; i f (vl,c&ave * 0 . O ) v l - c ~ a v e = .vl,crcave; / * averagm voltage * / vl,c&,trap = O . O t / * i n t e q r a t o r r eae t * /
1 / * voltage zero cror r inq de t ec t i on * /
i f ((v2-abgrev,f - v2-rb-L c- 0.0) 6& ( c o u n t u . 5 1 1 count- ab > 441 1 I
cowit-a-& - O z / * counter r e i e t * / v2-&b,trap = 0.0; / * i n t a g r a t o r r e i a t * / ep r i l on = - v 2 , a b - f / v 2 ~ b ~ r e v , f r c o r r ~ b = apailon tdraip/(l + a p r i l o a ) : i f .icorr-a-ab > t j r m p ) corr-r,ab u u a g : / * co r r r c t i nq t ac to r * /
1 / * i n t eq ra to r output ovat O t o p i / 2 * /
i f (counr,La.b == 27) (
corr -cab - v2-ab,f - corr-&-ab; v2-ab-ave - tv2-ab-crap - corr,cL.bJ/ t 22 t - rw ; i f (v2-ab,ave c 0. O } v2-ab-rve = -v2,ab,avei / * avetaqe voltage * / v 2 A t r . p = O . O r / * i n t a g r a t o r r e i e t * /
1 / * i n t aq ra to r output ov8r p i /2 t o p i * /
rf (c0unt-a-a.b == 41) [ .
va>-ave = (va&-trap - c o r r - U ) / (22 9 t ~ u n p ) r i f (v2,rb,rve * 0.0) v23b-ave = -vl,ab-nvmt / * rveraqe vol t rqe * / vl,.b,trap = 0.01/* f n t o q r i t o r r e i a t * /
I / * vol tage zero crorainq de t ec t i on * /
i f ( (vl-bcgrev-f vl3rc-f <= 0.0) i r t c o u n U c r 5 1 1 coun-c . 44 J (
v24c-trap = 0.0:/* i n t o g r r t o r teret ./ count ,cPc = Ot/* counter r e i e t */ e p i i l o n - . v 2 b ~ f l v 2 A c j r . v , f ; corr-mJc - epi i lon c a m p / (1 - mgailon) t i f i c o r r - O c ~ a m p ) c o r r d = U m p t / * corrac t ing f ac to r * /
1 / * i n t ag ra to r output over O t o p i / 2 * /
i f (CouaLLbc 0- 22) I
c o r r - U c = v l h c f 9 c o r r a c ; v09c-rve =(vlgc,trap - c o r r - U c I l ( l 2 9 LJamp) : i f ( v 2 J c ~ v e < 0.0) v 2 A c ~ v i - - v l A ~ v e t / * averagm voltage */ v24c-trap = O . o r / * i n tmqr i t o r r o r a t */
1 / * i n t eq ra to r output over p i / 2 t o p i * /
i f t c o u n ~ a - b c == 41) [
- - v2Jcdve - (v2Jc-trrp - c o r r a c ) / (22 u.sp) r i f iv2Jc-rve c 0.0) v2gc-rve = -v2hc-avmi/* rvmrrqm voltage * / v U c - t r a p = O.or/* in tmqrr tor -mat */
1 / * vo l t rge zero c ro r i i ng de t ac t i on ./
i f ((v2,cwr.v-f v 2 , c e <O 0." - " '---r?*&ca + 5 I t c o w u c r > 44) 1 (
v 2 , c ~ t r a p - O.or/* i n t a g r a t o r n i a t */ c o u a t - ~ c a - O;/* couatmr rmaat * / opailon - - v U & f / v L c q p r . v 3 t
c o r r - ~ c a = a p i i l o n t,samp/(l + e p r r l o n l t i f ( c a r + - ~ c a , c-aungl c o r r - ~ c a = t-8-r / * c o r t a c t r n g t r c r o r * /
1 / * i n t e g r i t o r outpuc over O to p i / 2 * /
i f ( c o u n t - ~ c r -= 22) L
corr-ccc* = v l - c ~ f c o r r - i c r t v 2 , c ~ a v e = (v2,ca-t t r p - corr-r-ra i / (22 c,iumi : i f (v2,c&~vm < 0.0) v 2 - c ~ r v a - -v2,c&-ivar / * rvoraqm voLt4ai * / v a - c ~ t r a p - O.or/* i n t a g r a t o r r i r e t * /
1 / * i n t e q r r t o r outpuc o v e r p i / 2 t o p i * /
i f ( c o u n t - ~ c a == 41) L
v 2 - c ~ a v e - t v 2 - c ~ t r r p + corr-cc.) / l22 c,aupl a rf ( v a - c ~ r v a c 0.0) v 2 - c ~ a v e - - v 2 , c ~ b v a r / * a v a r i q a vo l tage ./ va-ca-crrp - O . O r / * i n c e p r a t o r ris8t * I
1 / * i n t a q r a t i o n ur rng t r i p e r o i d a 1 r u l e * /
vl-ab-trap vl-&,trip + ( v l - a b j r a v - f + vl-ab,f 1 / 2 t-8-r vl_bc,trap = vlJc-trrp + ( v l b c g r a v - f + v1Jc-f 1 12 c,r.sipr vl-ca-trap = v l - c ~ t r a p + (VI-cwriv,f vl,cr,f)/2 t-rmp: v 2 A - t rap = v2,ab-t r r p + (v2-abgrrv,f + v2-ab-f 1 / 2 t - 8 ~ t v2Jc-trrp v 2 A c - t r i p + ( v 2 q c g r a v - f + v2Ac-f 1 /2 t-irop; v 2 , c ~ c r a p v 2 - c ~ t r a g + (v2,c.grsv-f + v 2 - c ~ f 1 /2 t-m.nip;
/ * vol taqa d a v i a t i o n from r a f a r e n c i v i l u a * / vl-ab-err - tvl-ab-i&va - v-ref 1 / v - r d r v U c - a r r t v l h c - a v s - v-ref 1 /v-ref r v l s ~ a r r = ( v l - c u v e . v d e f 1 /v,rmf; v2-ab-err - (v2,&-avi - v3.t ) /v,ref r vLbc,err m (v2Jc-ave - v,taf) /v-rmf r v a - c ~ a r r = (va-c-vi - v-ref l /v,ref;
/ * phare d i f f e r e n c s batween rourcar * / phare-diff = countg-ab - cowit- ab; rf ( a b n o m =- 0)
1 / * tr&nafonQation CO a l p h i - b u t a frame * / v-al = 2 (vl-ab-f . 0.5 vl-bc-f - 0.5 v l - c ~ f 1 /3: vJam - 2 (e0.866 v1Jc-f * n 0 6 6 v l , c ~ f ) / 3 ~ v-ilbe - i q r t (v-al v-al + vJe vJel i / * rpace v e c t o r aba. v i l u r * / i f (v-alba c 3.0)
I / * a l t e r n a t a i o u r c v o l t a g a O.K. * / i f ( (~2-&-ar t * 0.1 r r -v2&-err < 0.1)
cr (v2,bc-err c 0.1 r r .vlAc,arr c 0.11 a6 ( v 2 , c ~ e r r c 0.1 Cc - v J , c ~ e r r * 0.111
i * p r f ~ o u r c . g t r - 0x000000001 / * p r f . arc. t h y r i i t o r r qa t rnq blocked * / p-to-• - I r / * t r m i f a r to a l te rna t . r o u r c e enable*/ a b n o m l z / e a b n o m 1 condi t ion d a t a c t a d * /
1 1
i f ( ALT-ON ( 1 (vl-ab-irr 0 .1 I I vl-ab-arr < -0.1) I I (vlJc,err r 0.1 I I v 1 4 c - e r r < .0.1) I I ( v l - c c a r r 0.1 I l v l - c l a r r c -0.11)
t / * ~ ~ 4 1 t r u a r f e r to a l t e r n a t a r o u r c r * / i f ( ( v 2 A - e r r < 0.1 CL -vl&-arr c 0.11
LL (v2Jc-arr < 0.1 66 -v7Jc,err * 0.11 CL ( v 7 , c ~ a r r * O. 1 r r - v l , c ~ e r r O - 1 1
[ * p r f , r o u r c e g t r = 0x00000000;/* p r f . rrc. t h y r i i c o r r q i t i n q b1ock.d * / L t 0 - a ' 1; abnom - 1;
1 t
1 / * check f o r n o m l o p a r a t i n g c o n d i t i o a i rmr tora t ion * /
i f ( n o m =- 0) i
i f (!ALT-ON CL (vL-ab-arr < 0.1 &C -vl-ab-err < 0.11 CL tvl-bc-err c 0.1 CL - v l _ b ~ e r r c 0.1)
-- c i ( v L - c ~ a t r c 0.1 r i - v l - c ~ e r r < 0.1) 1 (
* r l u o u r c i g t r = 0 x 0 0 0 0 ~ ~ ~ ~ ' ; ~ - a l t . a r c . t h y r i s t o r 8 qa t ing blocked * / ~ t o g - 1 ; / . t r u i r f e r back t o p re fmrr rd r o u r c a e n a b l e * / n o m = l t / * r m r t o r a t i o n of n o m l c o a d i t i o n bcmcted * /
1 I
/ * t r m r f e r t o a l t r n m t a r o u r c e * / i f (p-to-a -- 1)
1 i f (il-a < -0.11
( / * curmat ir n.qativ0 */
d-y - dwmy 1 OxOOOlOOOOt *altaourclgtr = d u n n y ~ / ~ qatinq riqnal to IFGA * /
1 elma if il^ > 0.1)
( / * current ii poiitive * / dunily - duinay 1 OxOOO0OOOOt * a l U o u r c w t r - duaray;/* qating iiqnaL to FPGA * /
1 if (ii1-a-f c= 0.03) LL (-il-L€ a= 0.03))
( / * currmnt zero crorrinq detectad * / duiry 0 duisy 1 0x00090000;
*alt-8ourc.gtr - duaisiy;/* qating aiqnrl ta FPGA ./ 1
if (il& -0.1) ( / * currmnc ii neqative * /
dumy - dunry 1 0x00020000; alt,iourcrgtr = dunimyr/* qatrng s ~ q n r l to FPGA * /
1 elre if ( i l 2 + 0.1)
i/* currrnt ir poritivm * / dusiy - dunmiy 1 Ox00100000r
* a l t ~ o u r c w t r - & u m y ; ; - qacrnq irqnal ta PPCA * / i
if ((119-f <- 0.031 && (-ilJ,f <= 0.03)) ( / * current zero croaiing delscted * / duaimy * duiany 1 OxOOl2OOOOt *alt,iourc.gtr = dumiiyr/* qrtinq riqnrl CO PPGA * /
1 if (il-c < -0.1)
( / * current ir neqative * / d w - dwny ( 0x000~00001 * a l t ~ o u t c ~ t r = dumiiyt/* qatinq signal ta FPGA * /
1 elre if (il-c r 0.11
( / * current ii poiitive * / duniy = dwmy 1 0x002000001 *alt-aourcagtr = duarny;/* qat~nq iignal to PPGA * /
t If ((il-c,f c= 0.03) &a (-il-c,f e- 0.03))
I / * current zero crorrinq detected * / d m 0 du- 1 0~00240000~ *altjourcagtr duaii~y;/* gatlnq iiqnrl CO ?PGA * /
1 if (dumy =- 0xO03tOOOO)
i O-to-a = O; / * tranifer cogletmd * / dwmy - 0x000000001 n o m = Or/* check for n o A l condition rarcoration mnable * /
I 1
/ * trmrfer back to prefrrrrd source * / if i ~ t o g -= 1)
f if (13,. -0.1)
f / - cutrent ir neqative O'
dunmiy - 4- 1 O ~ O O O ~ O O O O ~ *alt~ourc.gtr = duaiy;/* qattng rima1 to ?PGA * /
I elre i f (13-8 . 0.1)
I / * current ir poiitive * / dusry - dumy 1 0x000~0000; *aluourc.gtr - dumyt / * qatfnq rigaal to PFGA * /
1 if ( ( 1 2 ~ f <= 0.031 rr ( - i 2 ~ f <= 0.03))
( / O current zero crorrinq detected * / duary = dirrry 1 0x00090000~ *prf~ourcegtr dunay;/* qrtiaq riqnal ta ??GA * /
1 if ( 1 2 4 c -0.1)
f / * current ir neqative */ d u r r y l dirary 1 0x00020000~ *aluourc.gtr duaiytl* qatinq signal ta CPQA * /
else if ( 1 2 4 . 0.1) ( / * currant ii poiicivm */
d u r y = duiiy I 0x00100000; *rltJourc.qtr = d m ; / * g8tiog iiqnrl CO PPGA * /
I if ((i2.J-f 0.03) 64 ( - 5 - 3 0.03))
{ / * cur~rnt taro croiring &t.ctmâ */ d i u y * d\Piy 1 OrOOlJOOOO t
*prf,aourc.gtr = d m ; / * qa t inq i imrl to IIU *, I
i f (il-c c -0.11 I / * c u r r e n t i r noqative * /
dumy - du~rny 1 0x00040000; *a l t , iourc .g t r = duiinyr/* qacanq rrgnal C O t)CI O !
1 a l a e i f (i2-c > 0.1)
( / * c u r r a n t i r pos i t i ve * / duiimy = duniy 1 O~OOI00000r * r l u o u r c e g t r = d u r i y ~ / ~ q r t t n q i r q i u l CO P W ' 1
I I I ((i2-c,f *- 0.03) && (-iI-cJ 0 . 3 1 i )
( / * c u r r r n t zero croa i inq do t ec t i d * f
dunray = duaiaiy 1 0xO0240000r a p r f d o u r c w t r = duiaiiyr -ar nu i r q m l t o tW I
1
vl-abgrev-f = vl-ab-f r v U c g r e v - f = vlJc-f ; v l c w r e v - f V L C L ~ 1 va-abgrrv-f - v 7 A - f : v2Jcgrev-f - v2-b~-f i v2,cwrev-f = v 2 , c ~ f :
/ * counti,nq @ / COulltg*+* ; C O U ~ ~ J C + + ; COUll~t-Oc.++ ; ~ 0 U n ~ a b + + : count,a-bc*+ r COullt~LCa++ ;
t / * end of u i e r funct ion * /
/ * i n i t i a l i r r t i o n t unc t ion * / void ur8r-init (void) f
r u p l i n q g e r i o d - 189.3939 t * p r f - s o u r c a p t r OxOO3?OOOO r / * p t8 fe r r . d raurcr rwitch t u m d on * / * a l t - s o u r c e g t r - 0x00000000;/* rLterri.to rource iwitcb turnd o f f O /
duaray = 0x00000000; / * d w va r i ab l a f o r t.rporary &ta i t o r aqe * / vl-ab-ave - 2 .SU; v1Jc-rve = 2.50: Vl-CLbV8 2 .Sv? v u - a v o = 2.58; vlJx,rvo 2.58 : v 2 - c u v e 2.50; v j e f 12 .58 ; -
vl,rb,.rr 9 1.0; v U c - e r r = 1.0 : v l c c 8 r r = 1.0 t v-err = 0.0; u iar - in ter rupt = STS r
1
Phase (pegrees) 1 1
APPENDIX C File STS.CDF
ALTERA MAX+plusII Grpk Design File Implemented in FPCA EPF8820GC 192
Parameters of Experimental Induction Motor
Name-plate data of the induction motor used in experimcnts are as given below:
Rateci Voltage: 1 10 V (line-line, mis);
Rated Frequency: 60 Hz;
RatedCurrent:26A;
Rated Power: 5 hp (3.725 kW);
Number of Poles: 4:
Rated Speed: 1730 r.p.m. (full load).
Selected Base Values:
Voltage: VB = f i V,,,,,, (line-to-neutral) = 89.8 1 Y;
Frequency: oB = 2nf,led = 376.99 rud/sec.
kr ived Base Values:
Impcdance: 2, = V B / I , = 2.43351;
Power: SB = 3 / 2 V B l B = 4953JW;
Time: tg = 1 /mg = 0.00265 sec;
O Inductance: Lg = Vg/(18 4) = 6.48mH;
Flux: yB = V B / a B ;
Mechanical Speed: nB = CU,/ P p = 1 88.49 rdsec, P p - number of pole pairs;
Measured parameters of the induction motor in per unit system: -.
Stator Resistance: R, = 0.034 peu. ;
0 LeaLage Inductance: L, = 0.26 p.u.;
- Rotor Resistance: R, = 0.04 p.u.;
COR-Loss Resistancc: R, = 208.35 p. u.;
Con-Las Inductance: Lm = 2.66 peu.;
Measureâ magnetizing characteristic of the experimental motor is shown in Figure C 1
FIGURE Cl. Magnetizing Characteristic of the Experimental Induction Motor
APPENDIX E
Graphic Design FUe for PSCADIEMTDC Simulation
APPENDIX F
Data File for PSCADIEMTDC Simulation
0 0 0 c 3 0 . : 3 0 0 0 0 ? 0 0 0 0 0 0 0 0 0 0 0 0 I I 0 0 0 0 . . . . . . . c o o . > ' i .L . , adou . d d d d d d o o o ~ o o ~ o o o o