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TRANSCRIPT
NASA Contractor Report 3235
InSb Charge Coupled -In
Device - Z&Element Linear Imager
R. D. Thorn, T. L. Koch, W. J. Parrish, J. D. Langan, and S. C. Chase
CONTRACT NASl-14922 FEBRUARY 1980
https://ntrs.nasa.gov/search.jsp?R=19800010091 2020-03-19T12:51:41+00:00Z
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NASA Contractor Report 3235
InSb Charge Coupled Infrared Imaging Device - z&Element Linear Imager
R. D. Thorn, T. L. Koch, W. J. Parrish, J. D. Langan, and S. C. Chase Santa Barbara Research Center Goletu, Califortzia
Prepared for Langley Research Center under Contract NASl-14922
National Aeronautics and Space Administration
Scientific and Technical Information Office
1980
CONTENTS
Section Page
1 INTRODUCTION ..............................
2 DEVICE DESIGN AND FABRICATION ................
InSb Material Characteristics .....................
8585 Chip Design and Description. ..................
Process Description ............................
Mask and Process Modifications. ...................
3 TWO-ELEMENT InSb CCIRID .....................
Device Description. ............................
Gate Oxide Witness Evaluation .....................
CCD Gate Capacitance and Flatband Voltage ............
Surface Potential and Charge Storage Capacity ..........
Channel Stop Metal Bias Requirements ...............
Two-Element InSb CCIRID Operation. ................
4 ZO-ELEMENT InSb CCIRID .......................
Device Description. ............................
Gate Oxide Witness Evaluation .....................
Gate Capacitance, Flatband Voltage, and Surface Potential Diagram for 8585 Lot 8B. ............
Test Equipment Configuration .....................
Test Results .................................
5 DISCUSSION OF TEST RESULTS ...................
Charge Transfer Efficiency .......................
LTCVD Reactor Differences .................... .L.
Device Operating Temperature. ....................
Improvements in Photogate Yield ...................
6 APPLICATIONS FOR MONOLITHIC InSb CCD ARRAYS ....
Earth Resources Applications .....................
1-l
2-l
2-l
2-8
2- 12
2- 15
3-1
3-l
3-3
3-8
3-10
3- 13
3-18
4- 1
4-l
4-4
4- 14
4- 19
4-29
5-l
5- 1
5-10
5-11
5-20
6-l
6-l
iii
Section
7
CONTENTS (Cod)
Page
Meteorological Satellite Applications. ................ 6-3
Geological Applications ......................... 6-4
SUMMARY.. ................................ 7-l
REFERENCES ............................... R-l
iv
ILLUSTRATIONS
Figure
2-l
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2- 10
3-l
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3- 10
InSb CCIRID Wafers ............................
Interband Tunneling in MOS Structure ................
Interband Tunnel Current versus Surface Potential for InSb .............................
Monolithic InSb CCIRID Chip (SBRC 8585) .............
Cross Section Perpendicular to Channel for CCIRIDs on SBRC 8585 Chip ......................
I-V Characteristic of Implanted Planar InSb p-n Junction (T = 77 K, ND = 4. 5 X 1014/cm3; 2 volts/div; 10 pa/div) ...
Process Flow Chart for 8585 InSb CCIRID .............
SEM Photograph of Etched Diode Contact Window Showing Undercutting of Gate Oxide Layer .............
p-n Junction Contacts on 8585 Chip (Dimensions for ZO-Element Imager, in mils) ...................
SEM Photograph of Diode Contact Using Nested Oxide Etch Masks (Z-Element CCIRID No. 498-ZO-B5, Lot 8~, 4o”, 3500x). ...........................
Two-Element, 4o InSb CCIRID on 8585 Chip. ...........
Schematic Diagram of Two-Element and ZO-Element InSb CCIRIDs ................................
SBRC Capacitance Measurement System ..............
Low-Frequency and High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 4; Sample 486A-10A .......
Surface State Density of Gate Oxide Witness; 8585 Lot 4; Sample 486A-10A .....................
Surface Potentials for One Bit of 40 CCD ..............
Surface Potential versus Gate Voltage for 8585 Lot 4 ......
Effect of Surface Conditions on Breakdown Voltage of InSb Planar p-n Junctions ......................
Surface Effect, Intermediate Case ..................
InSb CCD Floating Diffusion Output (Showing Negligible Output Diode Leakage. ...................
Page
2-2
2-4
2-6
2-9
2-11
2- 12
2- 13
2- 16
2- 17
2- 18
3-l
3-2
3-5
3-5
3-7
3-11
3-13
3-15
3-16
3-17
V
ILLUSTRATIONS (Cont)
Page Figure
3-11
3- 12
3-13
3- 14
3-15
3-16
4- 1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
Output of Two-Element (3.i Bit) InSb CCIRID with Ten Input Pulses (Device No. 442-14-G2) . . . . . . . . . . . . .
Output of Two-Element (34 Bit) InSb CCIRID with Single Input Pulse (Device No. 442-14-G2) . . . . . . . . . . . . .
Output of Two-Element (3; Bit) InSb CCIRID No. 442-14-Dl with Six Input Pulses . . . . . . . . . . . . . . . . .
Output of Two-Element (3$ Bit)- InSb CCIRID No. 442- 14-Dl with Ten Input Pulses . . . . . . . . . . . . . . . .
Output of Two-Element (3i Bit) InSb CCIRID No. 442-14-G2 without Fat Zero and with Parameters Adjusted for Maximum Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . .
Two-Element InSb CCIRID No. 442- 14-Dl Operating in Optical Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ZO-Element InSb CCIRID . . . . . . . . . . . . . . . . . . . . . . . . .
ZO-Element CCIRID Timing Diagram. . . . . . . . . . . . . . . . .
High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 1) . . . . . . . . . . . . . . .
High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 2) . . . . . . . . . . . . . . .
Low-Frequency and High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 1, Dot3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Surface State Density by Quasistatic Technique of Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 1, Dot3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Surface State Density by Quasistatic Technique of Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 1, Dot9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 4) . . . . . . . . . . . . . . .
Hysteresis of Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 2, Dot 11) . . . . . . . . . . . . . . . . . . .
3-19
3-20
3-23
3-23
3-27
3-29
4-2
4-3
4-6
4-7
4-7
4-8
4-9
4- 10
4- 10
vi
ILLUSTRATIONS (Cont)
Page Figure
4- 10
4-11
4-12
4- 13
4- 14
4-15
4-16
4-17
4- 18
4- 19
4-20
4-21
4-22
4-23
4-24
4-25
Low-Frequency and High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 11B; Sample 532-2A (Can 2, Dot 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 12
Surface State Density by Quasistatic Technique of Gate Oxide Witness; 8585 Lot 11B; Sample 532-2A (Can 2, Dots) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Surface State Density by Quasistatic Technique of Gate Oxide Witness; 8585 Lot 11B; Sample 532-2A (Can 2, Dot8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Hysteresis of Gate Oxide Witness: 8585 Lot 11B; Sample 532-2A (Can 2, Dot 3) . . . . . . . . . . . . . . . . . . . . . 4- 13
C-V Characteristics of Channel Stop, Buried, and Surface Metal Capacitors; Wafer 498-17; 8585 Lot 8B; Chip C5. . . . . 4- 16
Low-Frequency and High-Frequency C-V Curves for Surface Metal Capacitor; Wafer 498-17; 8585 Lot 8B; ChipC6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Surface State Density by Quasistatic Technique of Surface Metal Capacitor; Wafer 498-17; 8585 Lot 8B; Chip C6 . . . . . 4-17
Surface Potential versus Gate Voltage for Wafer 498- 17, 8585 Lot 8B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
General Test Configuration for 20-Element InSb CCIRID. . . . 4-20
20-Element InSb CCIRID in 40-Lead Dual-Inline Package, with Sapphire Window Sealed Over Well . . . . . . . . . . . . . . . 4-22
20-Element InSb CCIRID Mounted in Dual-Inline Package, Prior to Sealing of Sapphire Window . . . . . . . . . . . . . . . . . 4-22
CCD Array Test Set No. 2 . . . . . . . . . . . . . . . . . . . . . . . 4-23
Block Diagram of CCD Array Test Set No. 2 and Heli-Tran Cart Equipment. . . . . . . . . . . . . . . . . . . . . . . . 4-23
Sketch of Low-Temperature Cavity, Shields, and , Windows in Heli-Tran System . . . . . . . . . . . . . . . . . . . . . 4-25
Transmission Curve for 2.65-pm Narrow Bandpass Filter, Pyrex Plate, and Germanium Outer Window . . . . . . . . . . . . 4-27
Output of 20-Element InSb CCIRID No. 498-17-A3 with Ten Pulses Applied to FZ Input; CTE = 0. 992 f 0. 002 . . . . . 4-30
vii
ILLUSTRATIONS (Cont)
Page Figure
4-26
4-27
4-28
4- 29
4-30
4-31
4-32
4-33
4-34
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
Output of 20-Element InSb CCIRID No. 498-17-A3 (Retest, Four Months after Packaging); CTE = 0.9955f0.0005. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output of 20-Element InSb CCIRID No. 522-20-B4 with Signal Pulses Applied to FZ Input; CTE = 0. 994 f 0. 001 . . . .
20-Element CCIRID No. 498-17-A3 Operating at 60 K in Multiplexing Mode with Chopped IR Signal Input . . . . . . . .
20-Element CCIRID No. 498- 17-A3 Operating at 40 K in Multiplexing Mode, TINT > NBTc . . . . . . . . . . . . . . . . .
20-Element CCIRID No. 498-17-A3 Operating a 77 K in Multiplexing Mode, TINT > NBTc . . . . . . . . . . . . . . . . .
20-Element CCIRID No. 498-17-B2 Operating at 37 K in Multiplexing Mode, TINT > NBTc . . . . . . . . . . . . . . . . .
Measured D* of 20-Element CCIRID 498- 17-B2 in Multiplexing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
InSb CCIRID Timing Diagram for Demonstration of Time-Delay-and-Integration Mode (TINT = Tc) . . . . . . . . .
TDI Operation of ZO-Element CCIRID 498- 17-B2 . . . . . . . . .
Calculated Inefficiency Range versus N,, for Parallel-Edge Surface State Loss . . . . . . . . . . . . . . . . . . .
Measured C-V Characteristics of InSb MOS Sample with Gate Oxide Deposited in Horizontal-Flow CVD Reactor. . . . .
Measured Flatband Voltage Distribution for Sample in Figure 5-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SEM Photo of LTCVD Si02 Granularity Resulting from a Horizontal CVD Reactor, Showing Mean Size of 1500A . . . . .
Charge Transfer Inefficiency Mechanism due to Trapping by Localized Surface Potential Variations . . . . . . . . . . . . .
Release of Trapped Charge from Trap in Region of Large Lateral Field. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculated CTE versus Mean Patch Diameter . . . . . . . . . . .
Dark Current in a 4@ CCD . . . . . . . . . . . . . . . . . . . . . . . .
4-3 1
4-32
4-40
4-40
4-41
4-42
4-44
4-45
4-46
5-2
5-5
5-5
5-6
5-7
5-7
5-9
5- 12
viii
ILLUSTRATIONS (Cont)
Figure Page
5-9 Clock Frequency and Integration Time versus Storage Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 15
5-10 Etch Pits on cl 1 l>B Face of CZ InSb Wafer after Etching to Reveal Defects (2X) . . . . . . . . . . . . . . . . . . . . . 5- 17
5-11 Etch Pits on CZ InSb Wafer at Higher Magnification (40X). . . 5-17
5-12 Cl 1 l>B Face of LPE InSb Layer after Defect Etching (Phase Contrast Photomicrograph) (40X) . . . . . . . . . . . . . . 5-18
5- 13 MOS Storage Time at 77 K for LPE InSb Layer . . . . . . . . . 5- 19
5- 14 8585 InSb CCIRID Transparent Gate Structure . . . . . . . . . . 5-21
TABLES
Table
2-l
2-2
2-3
3-l
4- 1
4-2
4-3
InSb Wafer Specification Summary ..................
8585 Chip Design Rules. .........................
8585 CCIRID Fabrication Steps ....................
Oxide Parameters, 8585 Lot 4. ....................
Nominal Design and Process Parameters for 20-Element InSb CCIRID .................................
Oxide Parameters, 8585 Lot 8B. ...................
Calculated Charge Transfer Efficiency ...............
Page
2-2
2- 10
2- 14
3-9
4- 1
4- 15
4-33
ix
SYMBOLS
Y
E
6 0
cS E ss x
r(x) 2 %As 4s c-2 A aper
AB
AD
ADK
AE
AFZ
AG
*.T
AS
At
4 BV
CCSM
‘FB
%s
‘IDL
GO COD
= parallel edge inefficiency parameter
inefficiency per transfer of CCD
free space permittivity, 8. 854 X lo- l4 f/cm
substrate permittivity, f/cm
inefficiency due to surface states
wavelength, pm
transmission of spectral filter at wavelength x
generation lifetime in depletion region, seconds
metal-semiconductor work function difference, volts
= surface potential, volts
= field-of-view (FOV), degrees
= blackbody source aperture area, cm2
= CCD bit area, cm2
= detector area, cm2
2 = area contributing to dark current, cm
= channel edge area, cm2
= area swept by fat zero charge, cm2
= gate area, cm2
= junction area, cm2
= total area swept by charge packet, cm2
= trap area, cm2
= voltage gain
= junction breakdown voltage, volts
= output diode to channel stop metal capacitance, farads
= flatband capacitance per unit area, f/cm2
= gate-to-source capacitance, farads
= ideal capacitance of MOS capacitor, farads
= CCD output capacitance, farads
= output diode capacitance, farads
X
Gox
CPAD
CSF
c s tray
CTE
;I
D
D :):
EB
Eg
ES
EY
fC F SC
A
H . slg
IR
I SC
JD
Jg
JT
k
KOX
L
m“i
n
N
NB
oxide capacitance per unit area, f/cm 2
pad capacitance, farads
source-follower input capacitance, farads
stray capacitance, farads
charge transfer efficiency (efficiency per transfer)
mean diameter of trap, cm
distance from blackbody aperture to device, cm
detectivity, cm Hz%/watt
field in bulk depletion region, volts/cm
bandgap, eV (joule)::
surface electric field, volts /cm
lateral electric field magnitude, volts/cm
CCD clock frequency, Hz
electric field in tunneling calculation, (volts/m)
reduced Planck’s Constant, 1. 0554 X 10 -34 joule second
signal irradiance at plane of array, watts/cm2
junction reverse current, amp
photodiode short-circuit current, amp
dark current density, amps/cm2
thermal generation current, amps/cm2
current density due to interband tunneling, amps/cm2 (amps/m21
Boltzmann’s Constant, 1. 38 x 1O-23 joule/K
oxide dielectric constant
CCD gate length, cm
effective mass, i = x,y,z, (kg)
number of transfers
number of detectors in TDI
number of CCD bits
:kThe interband tunneling calculations in Section 2 are facilitated through use of mks units, which are listed in parentheses in the list of symbols.
xi
ND
Nfc
NG
n. 1 nS N ss P
P
9
QA(T)
=
Z
7
=
Z
=
ZZ
=
=
=
=
=
=
=
QB
Qbb(T)
QD
Qfc
QFILT(V =
QFZ Z
QP =
QS =
Q . s1g Z
Qtrap =
RX =
T Z
TC =
TINT =
tOX =
TS Z
VBI Z
VFB =
VFT =
vFZ =
substrate net impurity concentration, cm -3
number of oxide charges per unit area = Qfc/q, cm -2
number of gates in CCD
intrinsic carrier concentration, cm -3
surface electron concentration, cm -3
surface state density, #/ cm2-eV
number of C.CD phases
interband matrix element, (joule-meter)
electron charge, 1. 6 x IO-19 coulombs
spectral radiant photon emittance of blackbody at temperature T, phot set-’ cmm2 pm-l
background photon flux at plane of array, phot/sec-cm2
radiant photon emittance of blackbody at temperature T, phot/sec-cm2
dark charge, coulombs
oxide fixed charge density, coulombs/cm2
radiant photon emittance of blackbody at temperature T trans- mitted by a specified filter, phot/sec-cm 2
fat zero charge, coulombs
stored charge density, coulombs/cm2
signal charge, coulombs
signal irradiance at plane of array, photlsec-cm 2
trapped charge, coulombs
responsivity at wavelength A, volts/watt
temperature, degrees Kelvin
CCD clock period, seconds
detector integration time, seconds
oxide thickness, cm
storage time, seconds
junction built-in voltage, volts
flatband voltage, volts
feedthrough voltage at output, volts
output voltage due to fat zero charge, volts
xii
VG
vn
VO
vR
VS W W
WA(T)
Wbb(T) =
WFILT(T) =
gate voltage, volts
noise voltage, volts
vs + VFZ, total Output voltage, Volts junction reverse bias, volts
output voltage due to signal charge, volts
CCD gate width, cm
depletion region width, cm
spectral radiant emittance of blackbody at temperature T, watts cm -2 pm-l
radiant emittance of blackbody at temperature T, watts/cm2
radiant emittance of blackbody at temperature T transmitted by a specified filter, watts/cm2
xiii
Section 1
INTRODUCTION
For new generations of infrared sensors in the 198Os, the development
of integrated focal plane arrays (FPAs) will allow considerable improvements
in sensor performance while reducing the weight, volume, and power require-
ments of the FPA and associated subsystems. An optimal type of integrated
FPA is a charge-coupled infrared imaging device, or CCIRID, which combines,
monolithically, detector elements and charge transfer devices for multi-
plexing or other signal processing functions in a common, infrared semi-
conductor material. Such CCIRIDs may be configured in either linear or area
(two-dimensional) arrays.
Monolithic integration of detectors and CCDs in an intrinsic IR semi-
conductor material is an attractive approach for next-generation line and area
IR arrays. The monolithic intrinsic structure offers higher operating tem-
perature and quantum efficiency compared to its monolithic extrinsic (Si:X)
counterpart having the same cutoff wavelength, but gains these advantages
without the need for the hundreds or thousands of individual interconnections
required in the hybrid IR array concept, a sandwich of an intrinsic detector
array and silicon CCD chip. Because the intrinsic or fundamental absorption
is utilized, potentially high quantum efficiencies may be realized with suitable
device design, and optical crosstalk effects, particularly important in dense
arrays, will be small.
The long range objective of this work is to develop this new concept in
monolithic infrared imaging. The semiconductor material used in this de-
velopment is indium antimonide (InSb), an excellent choice for a CCIRID with
photon detection capability in the I- to 5. 5-pm spectral region. The imme-
diate goal is to fabricate prototype InSb CCIRIDs that will be used to establish
applications and operational characteristics of the infrared imaging sensors.
The monolithic infrared CCIRID imagers being developed on this program are
l-l
Section 2
DEVICE DESIGN AND FABRICATION
InSb MATERIAL CHARACTERISTICS
InSb Wafers
Starting material for CCIRID processing was n-type InSb grown by
M. C. P, Electronics Limited (England) and distributed by Metal Specialties,
Inc. , Fairfield, Connecticut, The InSb ingots, grown by the Czochralski
technique, were cut into wafers oriented to within *” of the (111) plane, and
subsequently final-polished to a thickness of 635 pm. The (111) B face was
used throughout this program for device processing. The wafers used for
CCIRID processing were undoped (n-type) with a net carrier concentration
at 77 K ranging from 6 X 1013 to 2 X 1014/cm3, as determined by Hall
measurements. The wafers utilized during the program had dislocation
densities (as measured by etch pit density on the A face) ranging from 0 to
1000/cm2. Later in the program the E. P. D. specification was tightened to
sz 100/cm2.
The wafers were shaped (by M. C. P. ) to a uniform diameter of 3. 2 cm,
followed by cutting of a nonoriented flat. The uniform diameter and flat
allow the slices to be handled conveniently in conventional processing equip-
ment and are necessary for pattern orientation in the projection mask aligner
that is used. An ultrasonic cutting tool was first used to shape the InSb
wafers, but edge chipping led to the present technique of shaping by means of
a diamond hole cutter. Figure 2- 1 shows, on the left, an InSb wafer that has
been shaped and final-polished on the B-face, ready for CCIRID processing;
and on the right, a completely processed wafer. Approximately 50 8585 chips/
wafer are obtained on the 3. 2-cm diameter slices.
A summary of the InSb material specifications is given in Table 2- 1.
2-l
Figure 2-l. - InSb CCIRID Wafers.
Table 2-l. InSb Wafer Specification Summary
TYPE
DOPANT
DIAMETER
FLAT LENGTH
TH I CKNESS
PARALLELISM
FLATNESS
LINE DISLOCATIONS
ETCH PIT DENSITY
ORIENTATION
SURFACE POLISH
EDGE CHIPS
CARRIER CONCENTRATION ND (77 K)
ELECTRON MOBILITY k (77 KI
CZOCHRALSKI SINGLE CRYSTAL n-TYPE
UNDOPED
32 f 0.25 mm
21.17 f 0.25 mm
635 f 25 pm
FACES PARALLEL TO WITHIN 25 pm
FLAT TO WITHIN 5 pm WITHIN 28 mm CENTRAL DIAMETER
<6 mm IN LENGTH
11DD/cm*
WITHIN 112O OF (111)
CO.1 pm FINISH. B FACE (5 pm FINISH, A FACE
12 PER WAFER FACE
5.0 x 1013 TO 2.0 x 1014/cm3
2525, COO cm*/volt-set
2-2
Interband Tunneling Considerations
Several factors influence the choice of ND. The most important is
tunnel current which motivates use of low carrier concentration material.
It is generally realized that, for materials with bandgap below about 0. 2 eV,
interband tunneling presents a potentially important factor in device design
and performance. InSb with its 0. 228 eV energy gap represents a borderline
case where tunneling is usually considered to be unimportant in, for example,
InSb PV detectors where the impurity concentration of the substrate is suf-
ficiently low to prevent tunnel diode characteristics and where the detector
is operated with zero applied bias. However, the relatively high fields
resulting at the surface when deep depletion conditions are established in an
InSb CCD or CID can produce significant tunnel currents, particularly .when
the impurity concentration is high. For a given surface potential, the max-
imum surface electric field increases as LID and, since the tunnel current
density varies exponential with this electric field, a strong dependence of
tunnel current on ND results.
This tunneling current has been considered in detail by Anderson’.
Referring to Figure 2-2, which shows an MOS structure with n-type substrate
biased into a deep depletion condition, tunneling from the valence to the con-
duction band is possible for electrons with energy between E,, and EC,.
After introduction of several approximations which, however, do not intro-
duce errors of more than a few percent for tunnel current densities 5 0. 1
amp/cm2, the tunnel current may be written in the form
(2-l)
2-3
Figure 2-2, - Interband Tunneling in MOS Structure.
where
a QL -G b s#, - Eg/2 ’
(2-2)
Eg is the bandgap, F,, is the electric field and A the reduced Planck’s Con-
s tant. The effective mass is isotropic in InSb with
-=- (2-3)
where i = x, y, z and P is an interband matrix element which, for InSb, is
equal to
P = 1.440 X lO-28 joule-meter. (2-4)
2-4
Evaluating the constant terms in equation (2- 1):
q fill = 7r3Jzt12 2P
= 2. 084 x 1041 coul/joule2-set-m
and
IT
c2-2fiqh
= 5. 563 X lo7 volts/meter
for Eg = 0. 228 eV = 3. 6526 x 10d2’ joule, allows rewriting (2-l)
JT -2
9
($ exp (- C2a/FsJ
(4 + (CZm/Fsc)t
(2-5)
(2-b)
as
(2-7)
To express JT with $, as the independent variable, use is made of the rela-
tion:
where
c3 = &,/f,) . (2-9)
Substituting (2-2) and (2-8) into equation (2-7) leads to the final result:
JT(@s) 2 c1c3 (9ds - 2,“’ exp I- 2 (q#s - $r) (2-l0)
2-5
I-.
InSb tunnel current density versus surface potential for four values of
impurity concentration ND, calculated using equation (2-lo), is plotted in
Figure 2-3. The tunnel current is expressed as a carrier flux density (log
scale) on the left-hand ordinate, and a current density on the right-hand
ordinate. The extreme variation with ND is apparent. At Iti,, 1 = 2 volts, for
example, the tunnel current varies 21 orders of magnitude between 2 x 1014
and 2. 5 x 1015/cm3 carrier concentrations. For the latter value of ND, JT
increases rapidly as ti,, only slightly exceeds the bandgap Eg. This is anal-
ogous to the rapid increase in reverse current of a backward diode. For ND =
2 x 1014/cm3, however, surface potentials of several volts are possible before
appreciable tunneling occurs.
It is now necessary to relate the results of Figure 2-3 to limits on CCD
operation. Although several relationships between dark current, clock fre-
quency, and CCD performance can be developed, the most straightforward
approach is to compare the tunnel current, JT, with the thermally-generated
current J in the device. g
The particular criterion applied is to determine the
surface potential at which JT = Jg.
SURFACE POTENTIAL /$',I (volts)
Figure 2-3. - Interband Tunnel Current versus Surface Potential for InSb.
2-6
.
With appropriate processing to minimize surface generation, it has
been shown’ that thermal generation in InSb MOS devices at 77 K is deter-
mined by bulk current sources and, in particular, by generation within the
volume of the depletion region. This current is given by
J g = TW = ni - -_ 9 7% %
(2-11)
where T g
is the generation lifetime in the depletion region. T g
has been
obtained from Zerbst-plot analysis of InSb MOS capacitance-time plots, and
is typically 0. 2 usec. Using this value in equation (2- 1 l), the thermal gen-
eration currents have been plotted in Figure 2-3 for the two extreme values
of ND considered. Since Jg aas, the th ermal currents are nearly hori-
zontal lines on the log plot of Figure 2-3.
The surface potentials at which JT = Jg are: \@,I = 1 volt for ND =
2.5 x 1015/cm3; Iti,,\ = 11. 4 volts for ND = 2 x 1014/cm3; and intermediate
values for ND between these two cases. These potentials represent the upper
limit to surface potential in a CCD fabricated on InSb of that impurity con-
centration. Consider, for example, an InSb CCD fabricated on ND = 2. 5 X
1015/cm3 material . Assume that a clock voltage is applied to a CCD gate
with a magnitude so as to instantaneously establish an empty-well surface
potential exceeding the potential at which JT = Jg. For example, take ]t,!~,\ =
2 volts, point A in Figure 2-3. At this potential, tunnel current exceeds the
thermal generation rate by four orders of magnitude, and the minority car-
riers generated will rapidly accumulate at the interface until the surface
potential is reduced to 1 volt (point B), at which point the normal thermal
process is resumed. Therefore, for this particular impurity concentration,
attempts to clock the CCD so as to produce Iti,/ > 1 volt under any gate will
produce large tunnel currents which will quickly return the potential to 1 volt.
For the low concentration ND = 2 X 1014/cm3, a wide range in CCD surface
potentials (about 11 volts) is possible before the tunneling process begins.
2-7
Since charge storage capacity is directly related to maximum surface
potential, as ND is increased progressively smaller charge capacity results
until charge transfer ceases completely (the specific limiting impurity con-
centration depending on whether the CCD is 2# or 4@). Based on these calcu-
lations, which have been verified by experimental determination of the onset
of tunneling in InSb MOS capacitors, material with ND no higher than 2 x
10 14/cm3 was used for device fabrication. Resulting CCD charge capacities 6
are in excess of 10 holes. Since tunneling is a basic quantum mechanical
limitation, it is not unique to InSb, and comparable tunnel currents occur in
other direct gap materials having the same bandgap.
8585 CHIP DESIGN AND DESCRIPTION
In earlier work” 2 shift registers were fabricated in InSb to demon-
strate the feasibility of CCDs in this material. These made use of the then-
available processing technology, one based on gold metallizations and SiO
dielectric layers. Due to the relative difficulty in etch delineation of these
materials, device dimensions were limited. CCDs with 50-ym and 25-urn
gate lengths were fabricated for which CTEs of 0. 9 and 0. 975 per transfer,
respectively, were measured. A further limitation was encountered with the
on-chip p-n junctions, which were formed by a mesa technique; the non-
planarity of the diodes prevented their reduction to the required size and
reduced yields in the dielectric deposition steps.
In this program, a new InSb CCIRID chip was successfully fabricated .
based on an improved process which eliminates the limitations inherent with
the earlier techniques. This process includes planar junction formation and
an aluminum and Si02 material system which is amenable to state-of-the-art
delineation techniques.
The monolithic InSb chip is designated the SBRC 8585; a photomicro-
graph of a die from a completed wafer is shown in Figure 2-4. The principal
device on the chip is a 20-element CCIRID (center). Smaller complementary
2-8
Figure 2-4. - Monolithic InSb CCIRID Chip (SBRC 8585).
devices are two- and four-element CCIRIDs, which differ in design details,
and a four-element TDI array with tapered register. The balance of the chip
contains MOS capacitors and gate-controlled diodes for process diagnostics.
The various devices are numbered in Figure 2-4 as follows:
1. 20-element linear imager
2. 4-element linear imager
3. 2-element linear imager
4. 4-element TDI array
5. Monolithic Gated Charge Integrator (GCI)
6. Test devices
Device numbers 1, 3, and 4 are all 4@ devices, with 12. 5-urn (0. 5-mil) gate
lengths in the cases of 1 and 4; device 3 has 10. O-pm (0. 4 mil) gate lengths.
Device number 2 is a 28 structure with 12. 5-urn gate lengths. The test
2-9
devices consist of three capacitors with different gate metal - either channel
stop, buried, or surface metal. There are, in addition, two gated diodes to
aid in evaluating process parameters. The 8585 chip dimensions are 2388 urn
(94 mils) by 2896 pm (114 mils). The design rules for the 8585 chip are shown
in Table 2-2.
Table 2-2. - 8585 Chip Design Rules.
DIMENS ION MINIMUM DIMENSION ON SBRC 8585 (mils)
CHANNEL STOP WIDTH 0.20
ALUMINUM LINE WIDTH 0.20 (ANY LEVEL)
AL-TO-AL GAP (ANY LEVEL) 0.20
SM-TO-BM OVERLAP 0.125
GATE LENGTH 0.40
CONTACT WINDOWS 0.3 X 0.8
SOURCE-DRAIN IMPLANT WIDTH 2.0 FOR ARRAY DIODES
A schematic cross section perpendicular to the channel for the CCIRIDs
on the 8585 chip is shown in Figure 2-5. The design/dimensions of the 20-
element CCIRID are specified here, but the design of all the devices on the
8585 is similar. The 20-element CCIRID incorporates an array of 20 MOS
detectors. The accumulated detector charges are transferred laterally into
an opaque InSb shift register by means of a surface metal transfer gate (GT).
A separate detector array rather than detection in the CCD channel provides
greater flexibility since detector integration times may be varied indepen-
dently of CCD clock frequency. The MOS photogates are 35 by 32. 5 urn on
50-urn centers and are biased via a common bus bar (G,). 75i of evaporated
titanium was used as the semitransparent photogate material. The IR trans-
mittance of the thin Ti gate structure was measured to be 38% including
2- 10
2&i SPUTTERED z lmO8, Al 6.M. I
:Kd SPWERED .M.I
hv
ZCd SPUTTERED SiQ P-l . .^ - ma Ima
xklA.AI IL. ,. , lCO3A LTCVD SiQ
SiO;,
SiQ
KM. I. I
1B.M. I.)
Figure 2-5. -Cross Section Perpendicular to Channel for CCIRIDs on SBRC 8585 Chip,
reflection losses associated with the oxide layers above and below it. Ti was
used for convenience and an improved transparent gate structure having lower
loss is being developed.
The 20-bit shift register is a 4@, surface channel, overlapping gate
CCD. The gate oxide of the CCD is lOOOK of Si02 grown on the InSb wafers
by low-temperature chemical vapor deposition (LTCVD) using silane and
oxygen at - 200°C. An additional 5OOi thick layer of SiO2 is sputter deposited
over the LTCVD SiO2 layer, which passivates the gate oxide and serves as a
transition layer between the LTCVD oxide and the other oxide and aluminum
layers in the CCD structure, which are all sputtered. Aluminum gates and
oxide contact cuts are delineated by chemical and plasma etching, respec-
tive ly. The gate length on the 20-element device is 12. 5 pm.
The 8585 chip incorporates planar p+ -n junctions formed by ion implan-
tation of beryllium for FZ input and charge output. The availability of a
compatible junction technology may enable additional features to be incor-
porated in future chip designs such as overload protection or ac-coupled
detector inputs. The implanted InSb junctions have sufficiently high.break-
down voltage and low leakage for use in infrared CCD devices. Their break-
down voltage increases as ND -1 and is greater than 5 volts for the impurity
concentrations considered. Figure 2-6 shows a 77 K I-V characteristic for
a Be-implanted diode on InSb with ND = 4, 5 X 1014/cm3, with breakdown
2-11
Figure 2-6. -1-V Characteristic of Implanted Planar InSb p-n Junction (T = 77 K, N X 1014/cm3; 2 volts/div 10 ua/?liv;l. 5 ; .
voltage of 8 volts. The forward and reverse currents of the implanted InSb
junctions have been analyzed and found to follow the usual theory for abrupt
junctions, with recombination-generation current dominating at 77 K. At
1 -volt reverse bias, the 77 K reverse current density is 5 x 10s7 amp/cm2.
This low leakage permits use of the Be-implanted junctions as the output
diode in a floating diffusion output circuit.
PROCESS DESCRIPTION
A total of fourteen mask levels is used to fabricate the 8585 CCIRID
devices. The block diagram of Figure 2-7 illustrates the processing steps
for the 8585 InSb CCIRID chip. The processes designated in Figure 2-7 are
explained according to process step, layer designation, process description,
and the process control methods used in Table 2-3.
As can be seen in Table 2-3, processing of the CCIRID devices requires
the use of five different metal depositions: sputter deposition of aluminum
for the channel stop, buried, surface and pad metal layers; and the use of
thermally-deposited titanium for the semitransparent gates. The insulating
layers in the CCIRID structure require five different oxide depositions.
2-12
ALIG
NM
ENT P
ATTE
RN
IM
PLAN
T P+
G
ATE
INSU
LATO
R
CH
ANN
;L S
TOP
PRO
CES
S PR
OC
ESS
MEl
AL P
RO
CES
S (A
PI
L SO
UR
CE/
DR
AIN
PR
OC
ESS
II)
(SD
) (C
II (c
sl
1 M
ASK
1 M
ASK
SiO
2 D
EPO
SITI
ON
D
EPO
SIT A
l: 1
MAS
K
I
CH
ANN
EL ST
OP
DIO
DE
CO
NTA
CT
TRAN
SPAR
ENT G
ATE
BUR
IED
MET
AL
INSU
LATO
R PR
OC
ESS
, (C
SII
b PR
OC
ESS
PRO
CES
S PR
OC
ESS
(DC
1 rrG
l (B
MI
DEP
OSI
T Si
O2:
2 M
ASKS
2
MAS
KS
DEP
OSI
T TG
; 1 M
ASK
DEP
OSI
T Al;
1 M
ASK
, t
BUR
IED
MET
AL
SUR
FAC
E MET
AL
BUR
IED
MET
AL
SUR
FAC
E MET
AL
INSU
LATO
R PR
OC
ESS
II)
PRO
CES
S C
ON
TAC
T PR
OC
ESS
CO
NTA
CT P
RO
CES
S IB
MI)
(SM
I (B
MC
) (S
MC
I D
EPO
SIT
SiO
2: 1
MAS
K D
EPO
SIT A
l; 1M
ASK
DEP
OSI
T Si
02:
1 M
ASK
1 M
ASK t
PAD
MET
AL
PRO
CES
S (P
M)
DEP
OSI
T Al:
1MAS
K t-4
FIN
AL
PRO
CES
S EV
ALU
ATIO
N
Figu
re
2- 7
. Pr
oces
s Fl
ow
Cha
rt fo
r 85
85
InSb
C
CIR
ID.
Table 2-3. 8585 CCIRID Fabrication Steps
PROCESS STEP
A: AL I GNMENT PATTERN
SOURCE/DRAIN p+ IMPLANT
B: GATE INSULATOR
c: CHANNEL STOP METAL
CHANNEL STOP INSULATOR OR FIELD OXIDE
DIODE CONTACT
TRANSPARENT GATE
BURIED METAL
BURIEI! METAL INSULATOR
SURFACE METAL
SURFACE MElAL INSULATOR AND BURIED CONTACTS
SURFACE METAL CONTACTS
PAD METAL
D: FINAL PROCESS EVALUATION
STEP IESIGNATION
AP
SD
GI
cs
CSI OR FO
DC
TG
BM
BMI
SM
BMC
SMC
PM
PROCESS DESCRIPTION
ETCH BASIC ALIGNMENT MARKS INTO SUBSTRATE
ION IMPLANT p+ BERYLLIUM THROUGH PHOTORES I ST PATfERN
DEPOSIT SILICON DIOXIDE GATE INSULATOR
SPUTTER DEPOSIT ALUMINUM METALLIZA- TION AND ETCH
SPUTTER DEPOSIT SILICON DIOXIDE INSULATOR AND ETCH
ETCH INSULATORS TO IMPLANTED InSb SURFACE AND FORM DIODE CONTACT
THERMALLY DEPOSIT TlTANlUM THROUGH PHOTORESIST MASK
SPUTTER DEPOSIT FIRST ALUMINUM CCD GATE METALLIZATION AND ETCH
SPUTTER DEPOSIT BURIED, AND SURFACE GATE INSULATOR AND ETCH CONTACT WINDOWS
SPUTTER DEPOSIT SECOND ALUMINUM CCD GATE METALLIZATION AND ETCH
SPUllER DEPOSIT SURFACE METAL SlLlCOh DIOXIDE INSULATOR AND ETCH BURIED METAL GATE CONTACTS
ETCH SURFACE METAL GATE CONTACTS
SPUTTER DEPOSIT ALUMINUM AND ETCH BOND PADS
MECHANICAL AND ELECTRICAL INTEGRITY DETERMINED BY MICROSCOPIC INSPEC- TION, ELECTRICAL PROBE TESTS, SURFACE C-V TESTS. AND DIODE C-V TESTS. SCANNING ELECTRON MICROSCOPE FOR HIGH-MAGNIFICATION INSPECTION OF MULTILAYER STRUCTURE, VOLTAGE CON- TRAST EVALUATION, AND VOLTAGE BREAK- DOWN STUDIES
PROCESS CONTROL METHODS
MICROSCOPIC INSPECTION FOR SIZE AND EDGE DEFINITION.
MICROSCOPIC INSPECTION OF STAINED WITNESS SAMPLES.
CAPACITANCE VERSUS VOLTAGE TO CHARACTERIZE ELECTRICAL PROPERTIES OF SILICON DIOXIDE - INDIUM ANTIMONIDE INTERFACE, INCLUDING: SURFACE STATE DENSITY. STORAGE TIME. FLAT BAND SHIFT. HYSTERESIS AND CAPACITANCE.
SURFACE PROFILOMETER MEASUREMENT OF THICKNESS. MICROSCOPIC INSPECTION OF GEOMETRY AFTER ETCHING.
GEOMETRY AFTER ETCHING; THICKNESS MEASUREMENTS.
GEOMETRY AFTER ETCHING; ELECTRICAL SHORT PROBE TESTS: 77°K DIODE PROBE TESTS.
GEOMETRY: TRANSMISSION. ABSORPTION. AND REFLECTIVITY OF WITNESS SAMPLES.
GEOMETRY AFTER ETCHING: THICKNESS MEASUREMENTS.
GEOMETRY AFTER ETCHING: THICKNESS MEASUREMENTS.
GEOMETRY AFTER FICHING; THICKNESS MEASUREMENTS.
GEOMETRY AFTER ETCHING: THICKNESS MEASUREMENTS OF INSULATOR.
GEOMETRY AFTER ErCHING.
GEOMETRY AFTER ETCHING; THICKNESS MEASUREMENTS.
2- 14
These include the deposition of LTCVD SiO2 for the gate insulator to obtain
the required low surface state density. The LTCVD SiO2 layer is sealed
with an overcoating of sputtered SiO2. Sputtered SiO2 is also used for the
channel stop, buried metal and surface metal insulating layers.
The process utilizes positive photoresist (Shipley AZ1300 series) and
2:l reduction projection mask aligning to delineate the CCD devices. Etching
of the aluminum gate patterns is done chemically while contact cuts through
the oxide layers are etched with a plasma etcherlasher.
MASK AND PROCESS MODIFICATIONS
The original 8585 mask design had some features which were found to
be incompatible with the actual processing sequence for fabricating the
CCIRIDs as it developed during the program. These design changes led to
new photomasks being fabricated for the channel stop insulator, surface
metal insulator, and diode contact levels.
The first mask change required was to separate the channel stop metal
contact window cuts from the channel stop insulator etch process (CSI). In
the CSI etch step, the total thickness of the oxide is reduced in the CCD
channel region. In this operation only a fraction of the oxide is removed and
no absolute stop point (i. e. , an underlying metal layer) is reached. The CSI
step is intended to reduce the oxide thickness in the channel so as to decrease
the clock voltage magnitudes required to operate the CCD. A result of the
CSI etch is that some oxide remains in the channel stop metal contact window.
By adding a new mask designated CSC, these contacts are now separately
etched through to the metal stop to assure continuity.
The second mask change required separation of the BMC and SMC con-
tact window cuts in place of the original SMI etch mask. This change was
found to be necessary because of the different oxide thicknesses involved.
The oxide overlying the surface metal is 0. 2 pm thick while the oxide over
the buried metal is 0. 4 pm thick. When both sets of contact cuts were etched
2-15
simultaneously with the original mask, the surface metal contact cuts were
severely overetched while clearing the buried metal contact cuts.
CCIRID wafers which were processed early in the contract were found
to have a high number of “open” p-n junctions (input and output diodes) which
were due to various degrees of contact degradation. This degradation varied
from oxide lifting around the contact windows, to windows which appeared
visually acceptable but were electrically open. Junctions tested for contact
continuity at room temperature showed contact resistances which ranged
from > 1000 MO (opens) to w 4Ofi. When cooled to 77 K, all were found to
either open or show very poor forward characteristics.
The scanning electron microscope (SEM) was used to determine why the
diode contacts were opening. The SEM photograph shown in Figure 2-8 illus-
trates the origin of the contact failures. The photograph clearly shows that
while the overlying aluminum conductor is continuous over the upper oxide
d I
N 0.1 mil I -
Figure 2-8. -SEM Photograph of Etched Diode Contact Window Showi?g Undercutting of Gate Oxide Layer.
2- 16
edge, it is discontinuous at the bottom edge indicating that the oxide layer is
undercut at the InSb/SiO2 interface. This was found to result from differ-
ential etch rates of the LTCVD Si02 gate insulator and the overlying sputtered
SiO2 field oxide. For the early wafer lots the diode contact windows were
formed by etching through both oxide layers to the p-n junction surface in a
single etching operation. The reason for this etch variation is that the
LTCVD Si02 etches faster than the overlying sputtered Si02 (approximately
25Oi/min versus 90i/min, respectively. This variation in etch rate allows
the gate oxide to etch faster laterally than the field oxide layer, thus creating
an undercut profile at the lower oxide edge. This edge profile is shown
schematically in Figure 2-9(A).
CONTACT METAL
(Al PREVIOUS JUNCTION (61 NEW CONTACTS WITH NESTED CONTACT GEOMETRY OXI DE ETCH MASKS
Figure 2-9.- p-n Junction Contacts on 8585 Chip (Dimensions for 20-Element Imager, in mils).
The solution to the diode contact problem required fabricating a new
photomask which is identical to the original diode contact window mask except
that the window dimensions are smaller by 0. 10 mil per side, as shown in
Figure 2-9(B). The process was changed so that following the channel stop
metal delineation process, the original mask is used to etch contact windows
through the gate oxide. Then the field oxide is deposited and the new smaller
contact windows are etched. The “nested” etch masks result in a window
geometry illustrated schematically in Figure 2-9(B). Since each oxide layer
is etched separately, the lateral undercutting which occurs does not effect the
2-17
overall contact window. A SEM photograph of a typical contact processed
with the nested oxide etch mask procedure is shown in Figure 2-10, showing
continuous Al metal coverage of the window edges. Since implementation of
the nested contact process, the yield of good diode contacts has exceeded 90%.
With these mask and process changes having been made, testable InSb
CCIRIDs were produced beginning with 8585 Lot 4. The following sections
describe the test results.
v ~0.25 mil I I--
Figure 2- 10. - SEM Photograph of Diode Contact Using Nested Oxide Etch Masks (2-Element CCIRID No. 498-20-B5, Lot 8B, 40”, 3500X).
2-18
Section 3
TWO-ELEMENT InSb CCIRID
DEVICE DESCRIPTION
The first device on the 8585 chip successfully processed and tested was
the two-element, 4@ InSb CCIRID. This CCD is at the center right in Fig-
ure 2-4. It is a smaller version of the 20-element CCIRID and is basically
similar to it in design. The two-element device was included on the chip to
take advantage of its higher yield due to its smaller device area, optimizing
the possibility of obtaining CCD data from the 8585 chip as early as possible.
A photomicrograph of the two-element CCIRID is shown in Figure 3-l.
The CCD register is at the center of the photograph and the two dark square
regions to the right of the CCD channel are the MOS detectors (photogates).
The input and output p-n junctions are at the top and bottom of the photograph,
respectively.
Figure 3- 1. -Two-Element, 4@ InSb CCIRID on 8585 Chip.
3-l
The schematic diagram for the two-element CCIRID is shown in Fig-
ure 3-2. The schematics for the two-element and 20-element CCIRIDS are
identical and this figure will be referenced again in Section 4. The shift
register in the two-element array is an overlapping-gate, 46 device with 14
clocked gates (3-l/2 bits, 4 gates/bit). The first clocked gate is @2 and the
last clocked gate is @3. The fat zero input (which can be also used to elec-
trically input signal charge into the register) consists of a diode (VID), an
input buried gate (VIB), and an input surface gate (VSc). The output ele-
ments consist of a diode, a buried metal output gate (VOG), and a floating
gate (@F) which may be optionally used.
.
'RST "REF
e,
"OG
?
Figure 3-2. -Schematic Diagram of Two-Element and 20-Element InSb CCIRIDs.
Either the output p-n junction or the floating gate can be used for
charge detection; in testing to date, the former approach has been taken,
using the output junction in a floating diffusion output circuit. The circuit
utilizes two 3N163 p-channel enhancement-type silicon MOSFETS, mounted
in the flatpack adjacent to the InSb chip, for the source follower and switch
transistors shown in Figure 3-2. An identical arrangement was used for the
20-element evaluation described in Section 4. All CCDs on the 8585 chip,
3-2
including the two-element device, also have a floating clock output option.
Operating with the floating diffusion output, the isolated gate @F, which lies
between a $1 and @3 gate, was tied to its appropriate phase (82) and clocked
normally.
The device has two photogate detectors biased through a common bus
(tip) and a surface metal transfer gate (@T). The photocharge from the
detectors enters the register through two ports in the channel stop metal
. beneath @4 gates. The ports are one and three bits away from the output;
i. e. , there is an empty (isolation) bit between detector inputs. This differs
from the 20-element CCIRID which has one CCD bit/detector. The CCD gate
length in the two-element device is 10 pm, slightly smaller than that in the
20-element device (12. 5 urn). With these exceptions the device layouts are
identical.
GATE OXIDE WITNESS EVALUATION
Several two-element CCIRIDs were tested from wafer number+ 442- 14,
8585 Lot 4. Each wafer lot includes a witness wafer for evaluating the gate
oxide characteristics after deposition but prior to subsequent CCD processing,
and p-n junction characteristics. The gate oxide witness for 8585 Lot 4 was
sample number 486A- IOA. The witness is processed simultaneously with the
CCIRID wafers up through sputtering of the 5OOi Si02 overlayer. In the
deposition of the first device metal layer (the channel stop metal layer) the
CCIRID wafers are removed from the system after 5002 of Al is deposited.
The witness wafer remains to receive a total of ZOOOK for ease of wirebonding
to the test capacitors. In this manner the witness undergoes identical process
conditions through the first gate level. The witness wafers are drawn from
the inventory of wafers not suitable for CCIRID processing (e. g. , those with
*The device identification system used throughout this report is as follows: Each CCD chip is identified by a seven-digit number as: XXX-XX-XX. The first three numbers represent the InSb ingot number; the second two the wafer number; and the last pair (alphanumeric) identifies the particular chip or die.
3-3
scratches or too high an impurity concentration). The 2OOOi of aluminum on
the witness wafer is photoetched into a pattern of ZO-mil diameter dots. After
dicing into groups of nine dots, chips are mounted in TO-5 packages which
adapt to specially-designed MOS capacitor evaluation dewars.
The witness capcitors are evaluated for flatband voltage, surface state
density, and other parameters pertinent to the CCIRIDs. To allow rapid
accumulation of the necessary C-V and other MOS diagnostic data, a com-
puter-aided surface analysis system has been used in this program. A survey
to determine the optimum N ss measurement technique for InSb and other
infrared semiconductors, resulting in selection of the quasi-static technique,
and design and setup of the automated C-V system, was accomplished on a
related contract (FO4701-76-C-0174). The system has been continually
improved and its capabilities expanded under SBRC’s Two-Dimensional
Infrared Array IR&D Project. Its present configuration is shown in Fig-
gure 3-3. In addition to its principal output, N,, versus surface potential,
software for N,, measurement by the conductance method, substrate impurity
concentration calculation, and C-t data acquisition and analysis has been
implemented. Not shown in Figure 3-3 are a PAR 135 Electrometer, an HP
33 10A Function Generator, and a Tektronix 7403N Oscilloscope which are
used in obtaining the quasi-static (low-frequency) capacitance characteristics
and the pulsed capacitance (C-t) data.
Figure 3-4 shows the measured low-frequency and high-frequency C-V
characteristics (dashed curves) for one (typical) capacitor from the Lot 4
witness sample. The solid curve is the ideal low-frequency C-V character-
istic calculated by the computer for the particular impurity concentration and
oxide capacitance of the witness sample. The oxide capacitance from the
accumulation region of the curve is 43pf giving CGxw = 43pf/2. 03 X 10 -3cm2
= 2. 12 X 10e8f/cm2. The measured thickness of the LTCVD SiO2 plus
sputtered overlayer was 165Oi giving for the calculated dielectric constant of
the witness gate oxide:
3-4
‘ER I I
H-P P825A COMPmER
WITH OPTIONAL PLUG-IN ROMS :
1. MATRIX. 98211A
’ DEWAR I 2. STRING-ADV ..- _^_.__ PROGRAMMING. L-------J YWlz1w
SHIELD 3. PLOTTER. GEN. 110. EXTENDED
I/Q 982144
Figure 3-3. - SBRC Capacitance Measurement System.
1.0
0.9
0. 8
0. 7
0.6 25 0
G 0.5
G
2178 11-7 486A-10A CAN1 DOT11 12116/77 ACC - INV
0.4
I
MAX DEPLETION WIDTH = 7.48E-05cm
0.3 DOPING DENSITY = 5.44E l&m-3
cox = 4.2% Olpf 0.2
AREA = 2. 03E-03cm2
0.1
I -2.0 -1.0 0.0 1.0 2.0 3.0
GATE VOLTAGE
Figure 3-4. - Low-Frequency and High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 4; Sample 486A-10A.
3-5
KOXW = Coxw tOXW = 3 95
FO (3-l)
in excellent agreement with the expected dielectric constant of SiO2.
The flatband capacitance can be obtained from the C-V computer pro-
gram or the equation
CFB - = cox
(3-2)
which gives CFB = 0. 87 CCx for the witness sample parameters. For the
capacitor of Figure 3-4, the flatband voltage is -1. 0 volt. Average VFB of
all samples was -1. 15 volts. The net fixed charge density at the interface
may be then calculated as
Nfc = Qfc/q’. CCxw (-VFB)/q = + 1. 5 X 101’ charges/cm’ (3-3)
This low fixed (positive) charge density is characteristic of the LTCVD SiO2 -
InSb interface, and leads to relatively low clock voltage requirements for the
CCIRIDs. Note that the calculation (3-3) assumes zero metal-semiconductor
work function difference (@MS). Taking handbook photoelectric work functions
for Al and InSb indicates that @MS may be as large as -0. 5 volt, but our data
indicate that it is closer to zero (photoelectric work functions must be
viewed as an estimate only of the actual work function difference in an MOS
structure). The work function difference is expected to be negative, however,
leading to an even lower Nfc than calculated in (3-3).
Referring again to Figure 3-4, the dispersion of the measured high-
frequency capacitance curve relative to the ideal curve, and the small dip in
the measured low-frequency curve, both indicate that N,, is relatively high.
Figure 3-5 shows the results of the quasi-static calculation of N,,, showing
a midband value of 1012/cm2-eV. The LTCVD SiO2 for 8585 Lot 4 was
deposited in a vertical-flow configuration reactor, and this surface state
density is to date typical of this particular reactor. CVD reactor comparisons
3-6
1016 b
Fig ure 3- 5.-
2178 11-7 486A-10A CAN1 DOT11 12116177 ACC - INV
MAX DEPLETION WIDTH = 7.48E-05cm
DOPING DENSITY = 5.44E 14cmv3 I
\ \ : \ /I \ / \ /’ \ /
\ / \ / .x -= ‘---- / / -= -=,--- / --_---- ---_ ---_-- /-- \ -LF-HF
\ \
. -o IiF-- ~-.---AEc & -0.05 0.00
SURFACE POTENTIAL
Surface State Density of Gate Oxide Witness; 8585 Lot 4; Sample 486A-10A.
and a more detailed discussion of InSb gate oxide characteristics will be
found in Section 5 and cited references.
Finally, although the witness sample dots were not stressed to de-
struction to determine ultimate breakdown strength, all dots withstood 20
volts bias, or 1.2 X 106 v/cm. Scaling this result to the nominal oxide
thicknesses under the BM and SM of the CCD (275Oi and 475Oi respectively)
these gate levels should withstand biases (with respect to substrate) of 33
and 57 volts respectively. This assumes no process-related degradation of
oxide quality.
3-7
CCD GATE CAPACITANCE AND FLATBAND VOLTAGE
After completion of CCD processing, three MOS capacitors on each 8585
die are available for evaluation (see Figure 2-4). These capacitors are on
the channel stop metal, buried metal, and surface metal levels so that the
characteristics of each gate level may be determined. Flatband voltages of
each gate level are measured to determine starting points for setting the
clock voltages. The oxides beneath each of these three capacitors undergo
the same processing conditions (e. g. , etching) as their corresponding oxide
levels in the CCD structures. Therefore, the capacitors provide an accurate
measure of the CCD gate characteristics.
The oxide parameters for 8585 Lot 4, determined from the test capac-
itors, are tabulated in Table 3-l. Listed are the measured characteristics
for the three gate levels along with the gate oxide witness sample. Row (a)
in the table lists the nominal oxide thicknesses (total) under each gate level.
The thicknesses for the various layers in the CCD are determined by Dektak
stylus profilometer measurement of a step etched through the oxide layer.
To provide a substrate which is inert to the oxide etch for accurate oxide
thickness determination, single-crystal sapphire substrates are used for
these witness parts. The density and thickness of the SiO2 sputtered on the
sapphire may differ slightly from that deposited on the InSb wafers; conse-
quently, these thicknesses are “nominal” but close to the actual thicknesses
on the InSb.
Row (b) in Table 3-l gives the measured capacitance per unit area
determined from the capacitor C-V curves and the known area of each dot.
Using the dielectric constant (3. 95) determined for the gate oxide witness
sample and assuming:: it is constant for each SiO2 layer in the CCD, the
oxide thicknesses may be calculated from the measured capacitances in
row lb). The values so obtained should agree well with the nominal thick-
ZzThis is a valid assumption based on independent measurements of the dielectric constant of our sputtered Si02 films in MIM structures.
3-8
Table 3-1. Oxide Parameters, 8585 Lot 4,
(a) NOMINAL OXIDE
(cl DIELECTRIC CONSTANT
if) FLATBAND CAPACITANCE (CFBbX)
(g) MEASURED VFB (volts)
(h) Nfc kharges/cm2)
486A-10A 442-14 442-15 442-14
1650 1 1650 1 2750 1 4750 )
2.12 x 10-8 2.13 x lO-8 1.36 x lO-8 7.79 x 1O-9 I I
-- I 1640 I
2580 I
4490 I
I I I -- l -0.6 I -6.2 I
-5.5 I
I i I I 0.87 / 0.80 ( 0.87 1 0.92 1
, 1 I I
-1.15 ( -0.8 1 -2.0 ( -4.0 1
tl.5 x 1011 +1.1 x 1011 +1.7 x 1011 +1.9 x 1011
nesses in row (a). These are listed in row (d) and are seen to be quite close
to the nominal values.
The flatband capacitances and measured flatband voltages for the CCD
gate levels are listed in rows (f) and (g) of Table 3-l. Using equation 3-3,
Nfc was calculated for each level [row (h)] and is seen to be in the 1 to 2 X
lo1 l/cm2 range consistent with the gate oxide witness sample. It should be
noted that, for the LTCVD SiO2-InSb interface, we have found 4 that the
flatband voltage can be shifted either positive or negative by biasing the gate
with respect to substrate prior to and during cooldown of the device to 77 K.
These bias stress studies indicate the fixed charge results from injection
from the semiconducto.r into the oxide. However, once cooled to 77 K, the
3-9
fixed charge remains constant under normal operating biases. The flatband
voltages and corresponding fixed charge values given in Table 3-1 were
measured with the gates floating during cooldown, rather than with any bias
applied. In the InSb CCD testing throughout the program, the device ter-
minals were also floated during cooldown so that the “intrinsic” fixed charge
levels listed in Table 3-l are the values that apply to the device as tested.
SURFACE POTENTIAL AND CHARGE STORAGE CAPACITY
Having determined the CCD oxide parameters given in Table 3- 1, the
surface potential versus gate voltage relationships may be calculated for the
8585 Lot 4 devices. The relationship between the surface potential t/~ S’ stored charge Q,, and appli-ed gate voltage VG is
1 $,=v+vo-v. l+Z 2 ( 1
where V =VG-VFB+- Cox
(3-4)
(3-5)
and VO L -Fsq ND /
C&X. (3-6)
COx is the oxide capacitance/unit area appropriate to the gate being con-
sidered.
To define nomenclature, Figure 3-6 shows one bit of an overlapping-
gate, 4@ CCD. Consistent with Figure 3-2, @I and 03 are surface gates and
02 and @4 are buried gates. On the 8585 chip, the surface and buried gates
are equal in area as shown in Figure 3-6. The surface potentials are shown
in Figure 3-6 appropriate to the one-quarter of the clock period during which
time the charge is stored beneath the buried @2 gate. We consider here
simple 4(6 clocking but other clocking modes are possible such as simulated
2@ or 4@ double-clocking.
The clock voltages applied to the surface gates (81, @3) are VG1 and
VG2 and to the buried gates (02, 04) VG3 and VG4. (These are identified in
3-10
' '@SE t
3@SBE
Figure 3-6.- Surface Potentials for One Bit of 40 CCD.
the 20-element CCIRID clock diagram in Section 4, Figure 4-2. ) The high
or “on” voltages are V,-2 and VC4 with VC2 < VCl and VC4 < VC3’:‘. The
surface potential notation used is that the subscripts refer to B = buried
gate, S = surface gate, E = empty, F = full, and the superscripts 1, 2, 3, 4
denote the potentials appropriate to clock voltages VCl, VC2, VC3, and VC4
respectively.
Referring to Figure 3-6, the Q2 gate is on (clock voltage VG4) and the
other three gates are clocked off. 01 and 03 are therefore at their off surface
potential ‘&SSE and are empty-. The buried gate @4 is also empty, at potential
3$ SBE. When no charge is being transferred in the CCD, the potential under
@2 is 4+?SBE. The criterion for maximum charge storage in the CCD is
evident from Figure 3-6 and occurs when
4G SBF = %SE (3-7)
Any less-negative surface potential under gate “2 resulting from additional
charge stored will clearly produce spillover across the @l and g3 gates. The
maximum charge that can be stored under G2 is therefore
%Signs and notation appropriate to a p-channel CCD are used throughout. When considering the inequalities, recall that gate voltages and surface potentials are negative for a p-channel device in normal operation.
3-11
= COXB la SSE - 4* SBE (3-8)
Considering in a similar manner the fraction of the clock period during
which the charge is stored beneath a surface gate (e. g. , @3) one obtains for
the maximum charge storage
Qps (maxI 2 Coxs SSF - 2@SSE
2 Coxs 3dJ SBE - 2a SSE (3-9)
Equations (3-8) and (3-9) show that the charge storage capacity may be
estimated for a given set of clock voltages from the empty-well surface
potentials of the buried and surface gates. Using equations (3-4) through
(3-b), with Qp = 0, the Gs versus VG curves appropriate to 8585 Lot 4 were
calculated and are plotted in Figure 3-7. These curves give the surface
potential beneath the gate when empty for any applied VC.
A further criterion for simple 4@ clocking and for the case of equal
gate area is
Q,B (max) = Q PS b--x) (3- 10)
which using (3-8) and (3-9) leads to
(3-11)
where ‘J) SSE sz 3d~~~ z 0. For lot 4, COXS/COXB = 0. 57,
i. e. , the buried gate empty-well potential must be 0. 57 of the surface gate
empty-well potential for the CCD to correctly transfer its maximum charge.
This criterion is shown in Figure 3-7 as a set of dashed lines connecting the
buried and surf ace gate as curves.
The calculated curves of Figure 3-7 are compared to experimentally-
determined clock voltages later in this section.
3- 12
-14
-12 -
-10 -
-8 - z e _
22 -6 -
-4 -
-2 -
00.
No = 2x 1014km3
KOX = 3.95
(5 = 1.576pflcm
S&I CLOCKING
, L.. I I I I I I I
-2 -4 -6 -8 -10 -12 -14 -16 -18 VG, volts
0
Figure 3-7. - Surface Potential versus Gate Voltage for 8585 Lot 4.
CHANNEL STOP METAL BIAS REQUIREMENTS
Both the two-element and 20-element devices were evaluated using the
floating diffusion output circuit shown previously in Figure 3-2. To use this
type of circuit successfully, the output p-n junction must have sufficiently
low leakage so as not to discharge the output node capacitance once it has been
preset to its reference level VREF. The combination of planar InSb p+-n
junctions of good quality which result from the Be ion implantation procedure,
along with gate control of surface potential around the junction perimeter,
allows this requirement to be met.
In the 8585 mask design, a channel stop metal level is incorporated in
the CCD structure which overlaps three of the four sides of the input and
output p-n junctions. The channel stop metal serves the combined functions
of charge confinement within the CCD channel and junction leakage optimiza-
tion through gate-controlled diode action. For both effective channel-stopping
and optimum junction characteristics, a near-zero surface potential is
. 3-13
required (i. e. , flatband conditions) at the channel edges and around the
perimeter of the p-n junctions. Since the n-type side of the p-n junctions is
lightly-doped, oxide charge in the gate oxide can readily produce non-zero
surface potentials, either accumulating or depleting (or in the extreme case,
inverting) the n-region, depending on the sign of the charge. Such surface
conditions can markedly affect diode leakage characteristics in a material
such as InSb. Applying bias to the channel stop metal of appropriate polarity
to balance the oxide charge will restore flatband conditions to the n-region
and optimize junction leakage and breakdown.
Analysis of the forward and reverse current-voltage characteristics of
the implanted Be junctions in InSb has shown5 that, at 77 K, the leakage is
dominated by generation-recombination current at small bias voltages. For
reverse bias voltages (VR) in excess of approximately 1 volt, the reverse 1
current IR departs from the IR Z VR 2 dependence expected for G-R current,
and instead enters a “soft” breakdown region where the current increases as
a superlinear function of VR. Current in the soft breakdown region arises
from both tunneling and avalanche mechanisms for the substrate impurity
concentration range of interest and, as such, is quite sensitive to any local
enhancement in electric field. For example, the electric field may be in-
creased relative to that associated with the ideal plane (not planar) junction
depletion region by junction curvature effects, material defects and inhomo-
geneities, and non-ideal surface conditions. The soft breakdown region
spans several volts and is the region of interest here since junction biases
exceed 1 volt for many CCD device requirements, including the output junc-
tion.
The soft breakdown current in gated InSb junctions is observed to vary
with gate bias in a consistent and qualitatively explainable manner. The
influence of gate bias on a p+- n junction is diagrammed in Figure 3-8, show-
ing the three generalized conditions that can be obtained. Figure 3-8(A)
shows the extreme case of the n-region inverted, corresponding to a large
negative gate voltage. Leakage is increased in this case due to an increased
3-14
VG << 0
(A) n-REGION INMRTED (B) INTERMEDIATE CASE
VG >> 0 Low Bv Q AREGIONS
\ jn-lnSb \
r
(0 p+-REGION INVERTED
Figure 3 -8. - Effect of Surface Conditions on Breakdown Voltage of InSb Planar p-n Junctions.
effective junction area for G-R current generation. Figure 3-8(C) shows
the other extreme case of p+- region inversion corresponding to a large
positive gate voltage. The resulting junction depletion regions for both cases
are shown in the figure. For p+- region inversion, case (C), extremely low
breakdown voltage (BV) can result due to the high field regions established,
identified in the figure. In the absence of a gated structure, conditions
identical to (A) and (C) in Figure 3-8 can occur if a large negative or positive
Qfc is present in the gate oxide.
As has been shown, Qfc is positive but small in magnitude for the
LTCVD SiO2 - InSb MOS process, so that the extreme inversion cases of
Figure 3-8(A) and (C) do not occur. The intermediate case of Figure 3-8(B)
is therefore of interest, corresponding to small gate bias or equivalent small
oxide charge densities.
The intermediate case surface effect is shown in more detail in Fig-
ure 3-9. Band diagrams are also given in this figure corresponding to the
bias conditions in the soft breakdown region. In the bulk region away from
the surface, the field in the depletion region EB increases approximately
linearly with reverse bias VR according to the equation given in Figure 3-9(A).
3-15
(A) BULK REGION
VR + VBI EB= WB -((vR + VBI)
EF
1 @‘D 1” /%vBl)
Es= VR + VBI
WS
(B) SURFACE ws - 1 I
= (VR
Figure 3-9. - Surface Effect, Intermediate Case.
The higher the base doping ND, the higher will be the field for a given VR,
As the field EB increases, additional tunneling of electrons from the pf to
the n-region occurs as shown in the band diagram of Figure 3-9(A), in
addition to increased avalanche current. Bulk-junction dominated breakdown
voltages in the absence of surface effects can be up to 10 volts for InSb
diodes at 77 K, with appropriate substrate doping. Since the definition of
breakdown voltage is arbitrary, the criterion used throughout the program
is BV = VR at IR = 10 pa, for a junction area of 5 X 10s4 cm2.
The current in the soft breakdown region can be influenced by surface
conditions, however, as shown in Figure 3-9(B). Here a positive Qf, or
equivalent positive gate voltage will induce an accumulation layer on the n-
side of the junction with surface electron concentration ns. The field at the
surface Es, therefore, will be higher than in the bulk by the factor (ns/ND)f
for the same applied VR, and increased breakdown current will flow around
the perimeter of the junction at the surface.
Summarizing, the soft breakdown characteristics of InSb planar p+-n
junctions are influenced by the charge Qf, in the gate oxide. The positive
3-16
Qfc present in the LTCVD SiO2 oxide accumulates the lightly-doped n-side
of the junction and gives rise to increased breakdown current relative to that
of the bulk junction. Negative gate bias restores the optimum surface poten-
tial at the surface, and this function is accomplished by the channel stop
metal.
Prior to clocking the two-element CCIRIDs, the output circuit was
biased up and the optimum channel stop voltage (Vcs) determined. The out-
put timing and waveform are shown schematically in Figure 3-10. Since the
last clocked gate is q53, @RST is timed to preset the output node to voltage
f c = 1W kHz
Vf(fF = -1.4 volts
DEVICE NO. 442-14-D
UPPER TRACE VCs= 0
LOWER TRACE Vcs= -1.15 volts
Figure 3- 10. - InSb CCD Floating Diffusion Output (Showing Negligible Output Diode Leakage).
3-17
VREF slightly in advance of @3 turning off. When @3 turns off, charge is
transferred across the output gate (at dc level VGG) to the output junction,
increasing its potential toward zero. The oscilloscope photograph in Fig-
ure 3- 10 shows the source-follower output voltage (V,) during the period of
time when the output junction is floating. The upper trace is for the channel
stop unbiased, V,, = 0; i. e. , no bias has been applied to eliminate the accu-
mulation layer beneath the channel stop metal. This corresponds to the
condition in Figure 3-9(B), and the additional leakage current is decreasing
the output node voltage toward zero as evident from Figure 3-10. The lower
trace in Figure 3-10 shows the elimination of this surface leakage by negative-
biasing the channel stop metal to slightly above its flatband voltage. This
channel stop bias effect was observed reproducibly on all the InSb CCDs
tested during the program.
TWO-ELEMENT InSb CCIRID OPERATION
The shift register of the two-element CCIRID was first operated
independently of the detectors by biasing the transfer gate @T and photogate
@P off, and applying signal pulses to the fat zero input. @T and tip were
biased to near their respective flatband voltages rather than held at zero so
that these gates were not in accumulation.
Figure 3- 11 shows the output of device 442- 14-G2 with ten signal pulses
appli’ed to the FZ input. All clock voltages and test conditions are listed in
the figure. Because of the availability of compatible planar p+-n junctions
in InSb, the FZ input structures on the InSb CCIRIDs are similar to conven-
tional Si CCD inputs, and it is not necessary to rely on surface avalanche
breakdown or tunneling for signal and FZ charge input. To input the signal
charge, the input diode was held at zero volts (i. e. , tied to substrate); the
signal pulses were applied to the input buried gate VIB; and the input surface
gate V,, was held at a dc potential. When the input buried gate is turned on,
3-18
fc = 200 kHz. 46
T = 60K
VID =o
vsc = -12.2 Volts
Ql = -5 to -16 volts
452 = -5.5 to -11 volts
43 - -5.5 to -16 volts
44 = -4 to -11 buns
VOG = -7.0 Volts
VEF = -2.0 Volts
+RST = -1 t0 -10 Volts
VOD = -10.5 Volts
VSS = +5.0 volts
VCS = -1.5 volts
h = -3.0 volts
*P = -2.2 volts
” = 14 Transfers
CTE = 0.994~0.cnl1
VFZ = 5mv
Figure 3- 11. -Output of Two-Element (3* Bit) InSb CCIRID with Ten Input Pulses (Device No. 442-14-G2).
the first clocked gate (@2) is off+, and the input p+ region supplies holes to
the well beneath the input surface gate. The input buried gate was turned
off, and @2 turned on to complete the input cycle. The input structures on
the 8585 devices are also capable of being clocked in a fill-and-spill sequence,
which gives superior control over input charge; however, due to other pri-
orities this was not investigated during this program.
The upper trace in Figure 3-11 shows the signal pulses applied to VIB
and the lower trace the source follower output voltage V,. In this and all
other oscilloscope photographs of the CCD outputs in this report, V, is shown
without further amplification, filtering, or sample-and-hold. The output in
Figure 3-11 is correctly delayed by 3; clock periods. CTE was calculated
using the usual measurement of trailers and loss in the leaders. For the
multiple pulse train of Figure 3- 11, the CTE obtained was 0. 994 f 0. 001.
--~ --
:kFor the case described here, the pulse applied to VIB leads ciock @2 and does not overlap it. Charge was also input with the VIB pulse in phase with @2.
3-19
Figure 3-12 shows the output of the same device with a single pulse applied
to the FZ input. Measurement of CTE from Figure 3-12 yielded CTE =
0.996 f 0.0003.
f c = 200 kHz. 44
T = 60 K
VID = 0
vsc = -11.9 volts
41 = -6 to -16 volts
@2 = -5 to -11 volts
@3 = -5.5 to -16 volts
44 = -3 to -10.5 volts
VOG = -6.7 Volts
VREF = -2.0 volts
bRST = -1 to -10 volts
Voo = -10.5 volts
VSS = +5.0 volts
“CS = -1.5 volts
@JT = -3.0 volts
@P = -2.2 volts
n = 14 Transfers
CTE = 0.996 f 0.0X13
vFZ = 5mv
Figure 3- 12. -Output of Two-Element (32 Bit) InSb CCIRID with Single Input Pulse (Device No. 442-14-G2).
For reference purposes, the equations used to calculate CTE from the
output pulse trains are collected here.
Method 1 6
For a single charge packet input into the CCD register, the inefficiency
per transfer F may be calculated from the relation
n< = B/A (3-12)
where n = number of transfers
A = magnitude of principal output
B = magnitude of first trailer
3-20
Assuming no charge loss, the efficiency per transfer (CTE) is then
CTE = 1 - < (3-13)
Method 2
For multiple charge packets (i. e. , pulse train) input into the CCD, if
B’ = magnitude of the first output pulse
A’ = maximum value of the signal output
then
CTE = (~liAl)l’~ (3-14)
A sufficient number of charge packets must be input to determine the true
maximum value A’.
Method 3
Again for multiple charge packets, if
6j = charge deficits in leaders, normalized to maximum signal output
61 = charge in trailers, J
normalized to maximum signal output
and denoting the sums of the normalized charge deficits and trailers as
then it can be shown that
sL = ST2 (CTE)” n’ [ 1 (l-f)“+1
- nc (l-6)” - (l-c)“+1
1-25 1-F (3- 15)
3-21
Solving for c:
SL sT cE!z-*-
SL + n ST + n (3-16)
The charge transfer efficiency and the dominant mechanisms affecting
it are discussed in greater detail in the Discussion of Test Results, Section 5.
Figures 3-11 and 3-12 are representative of the two-element devices tested.
Figures 3-13 and 3-14 show FZ input-output transfer characteristics for
another two-element CCIRID, No. 442- 14-Dl. The optimum CTE for these
devices was obtained with a 10 to 15% FZ charge.
The observed clock voltages are in reasonable agreement with the
calculated surface potential versus gate voltage diagram, Figure 3-7. The
empty-well surface potentials corresponding to the clock voltages of Fig-
ure 3-13, device 442-14-Dl, for example, are plotted on the @SBE and $SSE
curves in Figure 3-7 and labelled “Dl. ” The -4 to -8 volt clocks on $2 and
@4 swing the surface potential (&SSE) from about -1 to -4. 4 volts. The clock
voltages on the surface gates, -7 to -14 volts, swing $JSSE from - 1. 4 to -6. 7
volts. The criterion for equal surface- and buried-gate charge capacity
expressed by equation (3- 11) is seen to be closely satisfied.
Under the clock conditions of Figure 3- 13, the CCD should be capable
of transferring a maximum charge calculated from equation (3-9):
QPS (max) = (7. 79 x 10e9) (-1. 2 + 6. 7)
= 2. 67 x 101’ holes/cm2
The storage area of the two-element CCD is 0. 4 x 4 mils = 1. 03 Y 10m5 cm2
giving a charge capacity of 2. 75 x 106 holes.
Considering in a similar manner the clock voltages of Figure 3- 11
(Device No. 442-14-G2), the empty-well surface potentials are also plotted
in Figure 3-7 (points “GZ”). The balance between 4+S~E and 2&SSE in this
case is not as close as for device Dl. The maximum charge capacity for
these conditions is
3-22
VIB
VO
“IB
VO
fc = 2W kHz. 4@
T = 63 K
VI0 =O
vsc = -12 volts
@l = -7 to -14 volts
@2 = -4 to -8 volts
@3 = -7 to -14 volts
64 = -4 to -8 volts
VOG = -7. 5 volts
VREF = -1.5 volts
@RST = -1 to -10 volts
VDD = -10.5 Volts
vss = +5.0 volts
vcs = -1.0 volt
@T = -4.7 volts
@P = -0.2 volt
Figure 3- 13. - Output of Two-Element (3$ Bit) InSb CCIRID No. 442- 14-Dl with Six Input Pulses 5
f c = 2M) kHz. 4$
T = 54 K
I
VID = 0
“SC = -13.3 volts
= -8 to -16 volts
$3 = -7 to -15 volts
94 = -4.8 to -8 volts
VOG = -8.0 volts
VREF = -2.0 volts
@RST = -1 to -10 volts
“DD = -10.5 volts
@T = -4.7 volts
@P = -0.2 Volt
Figure 3-14. - Output of Two-Element (3* Bit) InSb CCIRID No. 442-14-Dl with Ten Input Pulses.
3-23
CCD capacity of 3 2~ 106 holes. The expected output voltage for this charge
input is
v 0
= (0. 9) (2. 1 x lo-l31 = 18 9 mv
10 x 10-12 .
The observed total output voltage was VFz + V, = 5 + 11 mv = 16 mv, in
reasonable agreement with the calculation. VFZ = 5mv was found experi-
mentally to be the typical FZ level required to maximize CTE. It represents
approximately 12% of the CCD charge capacity.
Further evidence that the input circuit was limiting the two-element
output voltage magnitudes in Figures 3- 11 through 3-14 was provided by the
facts that: (1) larger (30-mv) output voltage swings were obtained when
adjusting clock and input voltage parameters for maximum output amplitude
but neglecting CTE; and (2) an output voltage of 25 mv was observed with the
photogates biased and viewing an infrared flux, with the CCD clocks 81 - @4
set at the same voltages which gave the smaller output levels when inputting
with the FZ gates.
Figure 3-15 shows the larger output level observed for device No.
442-14-G2 when the parameters were adjusted to peak V, rather than opti-
mize CTE. VFz = and V, = V, = 30 mv. Comparing the parameters of
Figure 3-15 to those of Figures 3-l 1 and 3-12 reveals that the only signifi-
cant change was an increase in the low level of e1 and @3 from approximately
-5. 5 to -8 volts, with high levels remaining at - 16 volts. This increases the
off surface potential (‘&SSE) under @l and @3 from -0. 5 to -2. 1 volts. (Fig-
ure 3-7). This change simultaneously results in increased charge storage
in the CCD and an increased quantity of charge introduced by the input cir-
cuit. The calculated maximum charge capacity increases from 3 X lo6 to
3. 9 x lo6 holes. This occurs because some additional charge can be stored
under the surface gates on either side of the buried gate which is clocked
“high. ” (This represents an intermediate condition between conventional 4@
clocking and “double clocking”). More charge is introduced at the FZ input
because under this clock condition the first @3 gate, in addition to the first 62
3-26
f c = 200 kHz. 4
T = 60 K
VID = 0
v.jc = -11.9volts
1 = -8 to -16 volts
2 = -5 to -11 volts
3 = -8 to -16 volts
4 = -3.2 to -10.5 volts
v,,G = -6.7 Volts
VREF = -2.0 volts
RST = -1 t0 -10 VOkS
VDD = -10.5 Volts
4s = +5.0 volts
vcs = -1.5 volts
@T = -3.0 volts
@P = -2.2 volts
VFZ = 0
Figure 3 - 15. -Output of Two-Element (3* Bit) InSb CCIRID No. 442- 14-G2 without Fat Zero and with Parameters Adjusted for Maximum Output Voltage.
gate, fills to a 2-volt level when VIB is turned on. This adds a quantity of
input charge equal to 1. 2 X 10 -13
coul, giving a calculated total output voltage
in this case of
v = (0.9) (2. 1 X lo-l3 + 1. 2 x 10-13) = 29 0 10x 10-12
. 7 mv
in good agreement with the observed output magnitude in Figure 3-15. The
CTE is lower for this set of clock conditions, approximately 0. 98.
More testing is needed, in particular studying in detail the change in
CCD output with variations in each input gate voltage level, to quantify and
improve the input circuit operation. In particular, fill-and-spill and other
input circuit clocking methods must be investigated. The basic operability
of the two-element shift register that was verified, however, served the
purpose for which it was intended, that is, a stepping-stone to the larger
3-27
20-element CCIRID. The device demonstrated for the first time compati-
bility among the implanted diode, LTCVD Si02, and sputtered A1/Si02 pro-
cesses. As has been described in this section, the clock voltages were close
to expected values (Figure 3-i’), and the output voltage levels were consistent
with a 10 pf output capacitance and the calculated input charge levels. In
these tests, however, it is believed that the register was not operated up to
its maximum charge capacity.
The operation of the two-element CCDs was not evaluated over a wide
range of clock frequency. One device, No. 442-14-Dl, was operated at
f, = 1 MHz and T = 80 K. The CTE measured at this clock frequency was
0. 992 f 0. 001.
One of the two-element CCIRIDs, No. 442-14-Dl, was operated in the
optical mode. The output is shown in Figure 3- 16. The top trace is the
photogate clock, and the trace below it the transfer gate. The period of the
transfer gate pulse, in this case 300 psec, determines the integration time
(Tint)- The CCIRID was viewing an 800 K blackbody through a cold 2. 65-pm
spike filter (photon flux calculations for the dewar and filter used are given
in Section 4). The uppermost output waveform is for the blackbody aperture
blocked; below it, with the IR flux incident on the CCIRID. When illuminated,
the output shows a 16-mv signal, a zero, and then a lo-mv signal pulse. The
signal pulses are from the detectors nearest and farthest from the output,
respectively, and the zero between them arises from the isolation bit.
Since the transfer gate may be clocked independently of the CCD clocks,
the integration time may be set up for any of three conditions: (1) TINT =
NBTC (the condition for repetitive multiplexing) where NB is the number of
CCD bits/line; (2) TINT> NBTC (integration time exceeds line readout time);
and (3) TINT = TC (TDI). The range of useful integration times under a given
set of test conditions depends on the sum of background and signal photon
flux; the device storage capacity; and competing dark current processes.
3-28
-TINT -I
TINT= 300 US
WITH IR
TINT = 500 ps
WITH IR
f C = 2M) kHz. 4#
T = 62 K
VI0 =o
‘IB = -2.0 volts
vsc = -11.5 volts
fh = -9.5 to -13.5 volts
* = -4 to -7 volts
b3 = -4 to -13.5 volts
+4 = -5 to -8 volts
VOG = -7.7 volts
hEF = -2.0 volts
6~s~ = -1 to -10 volts
VOO = -10.5 volts
vss = +5.0 volts
vcs = -1.5 volts
Figure 3-16. - Two-Element InSb CCIRID No. 442- 14-Dl Operating in Optical Mode. Array Viewing 800 K Blackbody through 2. 65-pm Spike Filter.
3-29
Because the two-element CCIRID is short (NB = 3)+, and the signal (and back-
ground) photon flux levels resulting from the narrow-band spike filter were
low, an integration time longer than 3Tc was necessary to achieve measur-
able signal output levels, i. e. , condition (2) above was used rather than the
repetitive multiplexing condition (1). In Figure 3- 16, the top and middle
output waveforms are for TINT = 60 TC = 300 psec, and the lower output for
TINT = 100 TC = 500 ysec. Alternatively, TC could be increased to achieve
any desirable TINT for a given NB. The general testing approach used in this
phase of the program was to set up and optimize clocks and biases for a given
f, (using the FZ input), and then maintain this constant f, while increasing
integration time (TINT > NBTc).
The reduced amplitude of the second detector output seen in Figure 3-16,
which at first might be ascribed to transfer inefficiency, is believed to be due
to a defective (low-resistance) photogate with only a small contribution from
transfer 10s s. A processing problem led to a high incidence of shorted or
low-resistance photogates on both the two-element and 20-element devices
processed during this program. The identification of this problem and its
proposed solution is discussed in Section 5. A considerably smaller reduc-
tion in the second detector output would result from transfer loss with the
CTEs measured for the two-element CCIRIDs. Taking a conservative value
of CTE = 0. 990, the relative magnitudes of the first and second outputs
should be (0. 99)4 and (0. 99)12, respectively, since the detector charges
undergo 4 and 12 transfers to reach the output. The second detector output
signal should therefore be 0. 922 of the first, compared to the observed ratio
of 0. 625 for TINT = 300 pSeC. Even a CTE as low as 0. 98 only reduces the
second detector output to 0. 851 of the first. Further evidence of a defective
photogate is that the ratio of the second to the first output does not remain
constant as the signal is increased, as seen in the bottom output trace of
‘::There are 3 bits from detector 1 to the output but 32 bits from the FZ input to the output. A similar situation holds for the 20-element CCIRID: there are 20 bits from detector 1 to the output; 20* bits from FZ input to the output.
3-30
Figure 3- 16. The second output saturates at 10 mv, while the first output
continues to increase.
Further evaluation of the two-element CCIRIDs was not carried out,
since ZO-element devices from another wafer lot became available for eval-
uation at this point. With the smaller two-element CCIRIDs, however, the
first proof of the improved fabrication process was obtained along with the
first demonstration of readout of InSb MOS detectors with an InSb CCD shift
register.
3-31
Section 4
20-ELEMENT InSb CCIRID
DEVICE DESCRIPTION
The design and fabrication of the 20-element InSb CCIRIDs have already
been discussed in Section 2. Figure 2-5 and Table 2-3 provided the details
of the 4@, overlapping gate CCD structure and the process sequence for the
20-element arrays, respectively. For reference purposes, Table 4-l sum-
marizes the nominal design and process parameters for the device. Each
device component, e. g. , starting material, photogates, channel stop, etc. ,
has been discussed in greater detail in the previous sections. Figure 4-l
is a photomicrograph of a 20-element CCIRID after completion of processing.
The dark squares are the photogate detectors; directly above them in the
photograph is the CCD channel. Considerable chip area in this developmental
device is taken up by clock bus lines and bonding pads. This would not be the
case for an area CCIRID array, the architecture of which would be designed
to minimize the ratio of clock line and pad area to active (detector plus CCD
channel) area.
Table 4- 1. - Nominal Design and Process Parameters for ZO-Element InSb CCIRID
DETECTORS DETECTOR SIZE DETECTOR SPACING CCD DESIGN NUMBER OF CCD BITS CCD GATE LENGTH CHANNEL WIDTH SUBSTRATES GATE OXIDE OXIDE THICKNESS, BURIED METAL OXIDE THICKNESS. SURF METAL CCD STORAGE CAPACITY CHANNL STOP ON-CHIP JUNCTIONS OUTPUT OUTPUT CAPACITANCE
OUTPUT JUNCTION MOSFET INPUT STRAY
MOS PHOTOGATES 35pm x 32.5pm mum 44 p-CHANML 2D!4 12.5pm lD5pm n -TY
gE CZ InSb, ND
ICOI ZxlOk,
LTCVD SiO2
4500x 5 x 106 CARRIERS BIASED FIELD PLATE Be-IMPLANTED p+-n FLOATING DEFFUSION
TOTAL
0.3 pf 1.9 pf 3.9 pf
1 6.1 pf
<2x 1014/cm3
4-1
Figure 4- 1. - 20-Element InSb CCIRID.
The schematic diagram for the 20-element array is identical to the two-
element device and was shown in Figure 3-2 of the previous section. There
are 82 clocked gates in the shift register (20 l/2-bits) and, similar to the
two-element device, the first clocked gate is @2 and the last clocked gate is
@3. Input and output circuit gates and nomenclature are also identical.
Figure 4-2 gives the timing diagram for the 20-element CCIRID, with
the photogate and transfer gate periods shown as required for the detector
multiplexing mode TINT r NBTc. On the right-hand side of Figure 4-2, the
voltage levels are identified as they are referred to in the text.
Beginning with @l through @4, these are the shift register clocks
appropriate to a 4@ CCD. The “on” time of the clocks (i. e. , at voltages VG2
and VG~) may be varied from Tc/4 ( simple four-phase clocking) to Tc/2 (4@
double clocking); the latter is illustrated in Figure 4-2. Finite fall time on
the @l though @4 clocks is also shown in Figure 4-2; although a detailed study
was not carried out in the program, some amount of fall time (typically TC/8)
was observed to optimize device performance.
4-2
DETECTOR BIAS +p
TRANSFER PULSE ‘+T
$2
CCD CLOCKS
@3
REGISTER OUTPUT
“RST
SAMPLE S/H Offl
SIGNAL CHARGE INPUT
vlB
-‘Tl
-vT2 -VGl -vG2
-vc3 -‘G4
-VGl -‘G2
-vG3
-‘G4
-‘RSTl
-v RST2 - DET OUTPUTS
I
1 u Ll
-‘IBl
-vlB2
Figure 4-2. - 20-Element CCIRID Timing Diagram (For Detector Multiplexing Mode TINT 2 NBTC)’
The output circuit voltages are VOG, @RST, VREF, VDD, and VSS.
All are dc except for @RST, the clock on the gate of the reset MOSFET; its
timing is shown below ($4 in Figure 4-2. During the time that the last clocked
gate @3 is at its on voltage vG2, @RST is switched to VRST2 = - 10 volts. This
turns the reset transistor on and presets the output diode to voltage VREF.
Just prior to a3 being lowered to its off voltage VG1, the reset transistor is
turned off by switching gRST from VRST2 to VRSTl = - 1 volt, which leaves
the output node floating. As 83 goes low, whatever charge it contained is
pushed out of the @3 well, across the VOG gate, into the output diode poten-
tial well. The resulting output voltage V, is shown schematically in Fig-
ure 4-2, below GRST.
When @RST is switched from VRST2 to VRSTl and vice versa, a para-
sitic feedthrough voltage results at the output, identified as VFT in Fig-
ure 4-2. The CCD output signal V, rides on this feedthrough pedestal as
4-3
shown in the figure. The feedthrough voltage VFT is directly proportional to
the gate-to-source capacitance (C,,) of the reset transistor. For the discrete
3N163 MOSFET, Cgs = 0. 7 pf resulting in a relatively large feedthrough volt-
age. The feedthrough voltage is
VFT = VRST2 (4- 1)
giving approximately VFT = 0. 7 volt for the two-element CCIRID (Co = 10 pf)
and 1. 2 volt for the 20-element device (Co = 6 pf). The feedthrough magnitude
did not present a problem in the measurements since it was within the dynamic
range of the electronics. It is generally desirable, however, to keep VFT as
small as possible and this is accomplished by keeping Cgs low. This may be
achieved by incorporating a screen gate in the reset transistor and/or by
keeping the gate-source overlap area small such as by self-aligned geometry.
The other waveforms in Figure 4-2 relate to operation either with de-
tectors or electrical input and will be discussed in conjunction with the test
results.
GATE OXIDE WITNESS EVALUATION
Twenty-element CCIRIDs from two lots were tested during this contract,
8585 Lot 8B and 8585 Lot 11B. Almost all data obtained as of this writing are
for devices from Lot 8B, and both of the 20-element arrays delivered under
this contract came from this lot; consequently, it is the better characterized
of the two lots. The gate oxide witness samples for Lots 8B and 1 IB were
486B-25C and 532-2A, respectively, and data for both will be given. Witness
sample gate oxide processing was identical to that of the CCIRID wafers as
was discussed in Section 3.
8585 Lot 8B (Witness Sample 486B-25C)
To obtain a representative sample size, four dies from the Lot 8B
witness sample 486B-25C were packaged in TO-5 headers for low-background
C-V evaluation, identified as cans 1 though 4. At this point in the program,
4-4
there was concern about what effects the standard substrate contacting pro-
cedure had on the MOS characteristics, if any. Consequently, the standard
procedure -- an indium solder contact, a known ohmic contact to n-type InSb
but one requiring exposure to -160”~ -- was used on cans 1 and 2, and a
conductive epoxy contact on cans 3 and 4.
The LTCVD Si02 gate oxide for 8585 Lot 8B (and 11B) was deposited in
a horizontal-flow configuration reactor (AMS 2600), instead of the vertical-
flow configuration AMS 1000 reactor used for the gate oxide deposition for
8585 Lot 4. These two reactors produce significantly different MOS chara-
teristics on InSb, which is discussed further in Section 5. The horizontal-
flow reactor results in a midband Ns, in the low loll cm-2-eV-1 range as
measured by the quasistatic method, compared to -1012 cmW2-eVW1 for the
vertical-flow reactor. As will be shown later in this report, the measured
low-frequency (or quasistatic) capacitance curves, from which N,, is calcu-
lated, are influenced by the lateral inhomogeneity of the gate oxide and the
N ss values determined represent an upper bound to, but not the true, surface
state density. As part of a 1978 Independent Research and Development pro-
ject, detailed measurements of the surface state loss peaks by the conduc-
tance method showed that N,, is in fact 1O1’ cm-2-eV-1 or less for good
samples produced with the horizontal-flow reactor.
In the horizontal-flow reac tar, the reaction tends to be more homo-
geneous than that in the vertical-flow reactor:::, which produces a less desir-
able Si02 deposit in terms of its mechanical and chemical properties: it is
less dense and has a faster etch rate. Consequently, the two reactor types
presented a tradeoff for CCIRID processing. Lots 8B and subsequent lots
used the horizontal-flow reactor to gain the advantage of the lower surface
state density, while the other properties of the oxide were known to be non-
optimum.
:::This statement is true for the specific platen temperature (220°C) and gas flow rates used, and not for the two reactor types in general.
4-5
I
Figure 4-3 shows high-frequency (1 MHz) C-V curves for the seven
20-mil diameter capacitors in ca’n 1 from sample 486B-25C. With the excep-
tion of dot 4, the flatband voltages are tightly grouped with VFB = -0. 2 f 0. 08
volts. All capacitors were biased to -20 volts without breakdown (1. 4 X lo6
volts /cm).
40 I I I I I I I I I
DATA ID NO. 5-812634-6 DATE 5-19-78 SAMPLE 4&B-25C-1
30- A=2.03x10e3cm2 F = 1 MHz
VG, volts
Figure 4-3. -High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 1).
Figure 4-4 shows similar curves for can 2 of the same witness wafer,
but on an expanded voltage scale and for all 11 pins of the TO-5 package. The
nine-capacitor pattern consists of seven 20-mil diameter dots without guard
rings (pin numbers 2, 3, 4, 8, 9, 10, and 11) and two smaller-diameter dots
(pins 5 and 12) with guard rings (pins 1 and 6). The capacitor area listed in
the figures (2. 03 X 10m3 cm2) applies to the seven unguarded dots. The mean
flatband voltage of the eleven capacitors in can 2 is -0. 055 volt with a standard
deviation of 0. 09 volt. For both can 1 and 2, the oxide capacitance is about
39 pf.
Figure 4-5 shows the measured low- and high-frequency C-V curves
(dashed curves) for one capacitor in can 1, compared to the ideal (solid)
low-frequency curve. Comparison with Figure 3-4 in the previous section
4-6
40 .-- -1 I ' I I I I I I I I
DATA ID NO. 5-812635-l DATE 5-19-78 3--/
SAMPLE 4&B-25C-2 z-
::I 30 A 2.03 x IO-3 cm2 11 8 F = 1 MHz
I-;
0 I I J I I L I I -6 -4
I I -2 0 +2 l 4 l 6
VG, volts
Figure 4-4. - High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 2).
0.8 -
0.7 -
0.6 -
z? ‘u 0.5- _..._...___..__..._... -..-....-...-....-
0.4 - MAXIMUM DEPLETION WIDTH - 7.68 x 1O-5 cm
0.3 - DOPING DENSITY - 5.13 x 1014 cme3
0.2 - Cox * 3.92 x 101 pf _
AREA = 2.03 x lo3 cm2 0.1 -
2636 486B-25C CAN1 DOT3 5-19-78 ACC - INV I I I I I
-3 -2 -1 0 +1 +2 GATE VOLTAGE
Figure 4-5. -Low-Frequency and High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 1, Dot 3).
4-7
shows the improved characteristics of the horizontal-flow reactor gate oxide.
The measured high-frequency characteristic in Figure 4-5 shows little dis-
persion from the”idea1 curve and, since the flatband voltage is very near zero,
essentially overlies it, indicating a low surface state density. The measured
low-frequency characteristic in Figure 4-5 shows a larger magnitude (and
more symmetrical) dip compared to Figure 3-4, also consistent with lower
N ss, but the curve still departs significantly from the ideal (N,, = 0) low-
frequency curve. This departure is in fact due to the lateral nonuniformity of
the horizontal-flow LTCVD Si02. Figure 4-6 shows the apparent surface
state density calculated from the measured low-frequency curve of Figure 4-5,
assuming that the low-frequency curve is solely being influenced by the sur-
face-state capacitance C,, (proportional to N,,) and not by other non-ideal
effects such as lateral inhomogeneity. Note that two curves are plotted, one
labeled “LF” and the other “LF-HF. ” The “LF” curve is calculated by com-
paring the measured to the ideal low-frequency curve; the “LF-HF” is ob-
tained by comparing the measured low-frequency and high-frequency curves.
1016 2636 A%B-25C CAN1 DOT3 5-19-78 ACC - INV
MAXIMUM DEPLETION WIDTH . 7.68 x 10m5 cm
DOPING DENSITY = 5.13 x 101%m-
-LF
i
i
\?, 5. -..,
'-1, I':, 1::.
E” -0.20 -0.15 -0. IO -0.05 0 EC +o. 05 SURFACE POTENTIAL
Figure 4-6.- Surface State Density by Quasistatic Technique of Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 1, Dot 3).
4-8
Good agreement between the two curves over most of the surface potential
range serves to self-check the calculation. Midband N, s from Figure 4-6 is
4 X lOI cm-2-eV-1 and, as stated, this represents an upper bound to the
actual surface state density of 8585 Lot 8B. Figure 4-7 plots the quasistatic
determination of N,, for another capacitor in the same package, showing
similar results.
lOI5 ~~ ! 2637 4&B-25C CAN1 DOT9 5-19-78 ACC - INV 2637 4&B-25C CAN1 DOT9 5-19-78 ACC - INV
. .-LF i +I; 1014 r
k c ! 7 2 i
Y E 1013 - 0 !
1 i z : .i
*. ..-'
1012 1012 : 'h, 'I '...-LF-HF
::. :-: .:. .- .::: . . . . . **.
_ MAXIMUM DEPLETION WIDTH = MAXIMUM 7.&x 10-5;;" . .
DOPING DENSITY - 4.88 x lOl4 cmm3 DOPING DENSITY - 4.88 x lOl4 cmm3
101’ 101’ ’ ! I ! I I I I I I I I I I I E, -0.20 il.15 -0 10 -0.05 0 EC 0.05
SURFACE POTENTIAL
Figure 4-7. - Surface State Density by Quasistatic Technique of Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 1, Dot 9).
Figure 4-8 shows the C-V curves for the seven unguarded capacitors in
486B-25C can 4. The flatband voltage is zero and the uniformity is seen to
be excellent. Note that the apparent oxide capacitance is lower (31 pf instead
of the 39 pf for cans 1 and 2). This is an artifact associated with a high-
resistance substrate contact, resulting from the conductive epoxy bond used
for this can. The conductive epoxy contacts were found to be unreliable at
cryogenic temperatures.
Finally, Figure 4-9 shows the hysteresis in the C-V characteristics for
sample 486B-25C; all capacitors displayed identical hysteresis and the dot in
4-9
40 I I I I I I I
DATA ID NO. 5-812647-l DATE 5-31-78 SAMPLE 4&B-25C-4
30 - A = 2.03 x 10e3 cm2 F = 1 MHz
2, 3. 4. 11
= M-
u’
10 -
O -20 I I I I I I I I I I
-16 -12 -8 -4 0 +4 VG, volts
Figure 4-8. - High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 4).
40- , I I I I
DATA ID NO. 5-8/2635-2 DATE 5-19-78 SAMPLE 4%B-25C-2
30 -A 2.03 x 10e3 cm2 F = I MHz i,
3 20 -
10 - zG -
’ -6 I I I I I I
-4 -2 0 42 +4 VG, Volts
Figure 4-9. -Hysteresis of Gate Oxide Witness; 8585 Lot 8B; Sample 486B-25C (Can 2, Dot 11).
4-10
Figure 4-9 is representative. Gate oxides have been deposited in the hori-
zontal-flow CVD reactor for which hysteresis is totally absent; however,
sometimes relatively small hysteresis results as in the case of this particular
deposition. The flatband shift in Figure 4-9 is AVFB = 0. 2 volt. The solid
curve is the positive-to-negative gate voltage sweep, and the dotted curve is
the negative-to-positive return sweep.
8585 Lot 11B (Witness Sample 532-2A)
The characteristics of the witness sample for 8585 Lot 11B are shown
in Figures 4-10 through 4-13. The flatband voltages ranged from zero to
slightly positive (+ 0. 3 volt). The dips in the measured low-frequency capac-
itance curves (Figure 4- 10) are close in width to the ideal curve. An anom-
alous feature shown by this witness sample, however, is the presence of a
secondary slope in the measured high-frequency curve extending from VG = 0
to -2 volts, in the weak inversion region. It is also reflected in the low-
frequency curve (Figure 4- 10). Figure 4-11 shows that the secondary slope
in the high-frequency C-V curve corresponds to a localized band of apparent
surface states centered about 0. 05 eV above the valence band edge. Although
the quasistatic calculation of surface state density becomes very inaccurate
and should not in general be accorded any quantitative credibility near the
band edges, there is a distinct plateau in the N,, curve of Figure 4- 11, where
N ss s 5 X 1012 from Gs = -0. 13 to -0. 17 volt, which is clearly absent in the
previously discussed samples, Figure 3-5, 4-6, and 4-7. This is of unknown
origin and occurred for several depositions for a time before and after the
date of this sample (and lot) gate oxide deposition. Figure 4- 12 shows the
quasistatic surface state density for another dot from the same sample; the
N ss hump is likewise present (note the change in N,, scale). Midband N, s
(again an apparent value) is 2. 0- to 2. 5 X 101’ cm-2-eV-1, lower than that of
the witness sample for 8585 Lot 8B.
The anomalies in the curves of Figure 4- 10 through 4- 12 have not been
observed recently. It should be pointed out that, in the earlier stages of the
LTCVD Si02 process development, secondary humps and/or dips in the
4-11
0. P - 0. P -
0.8 - 0.8 - . . .
0.7 - 0.7 -
x0.6 - x0.6 - uo uo ‘u ‘u
0.5 - 0.5 - :
.:’ 0.4 - 0.4 - ,....’
,_..” __..”
0.3 - 0.3 - . . .._..........-..-.. _ .._.-.-...-. _..-- - ..-....,_...... .’ MAXIMUM DEPLETION WIDTH = 1.43 x lo-’ cm
0.2 - 0.2 - DOPING DENSITY = 1.32 x 1014 cmm3-
cox = 4.94 x IO’ flf AREA = 2.03 x 10m3 cm2
0. 1 - 0. 1 - 2752 2752 7-10 532-2A CAN2 DOT3 E-lo-78 ACC - INV 7-10 532-2A CAN2 DOT3 E-lo-78 ACC - INV
I I I I I I I I -5 -5 -4 -4 -3 -3 -2 -2 -1 -1 D D +1 +1 +2 +2 +3 +3
GATE VOLTAGE GATE VOLTAGE
Figure 4- 10. - Low-Frequency and High-Frequency C-V Curves for Gate Oxide Witness; 8585 Lot 11B; Sample 532-2A (Can 2, Dot 3).
;! LF--
?. LF-HF +
i. I . .
i i .:* :
: ’ . .’
I ..rr . . . . . .
. .
“15k 2752 7-10 532-2A CAN2 DOT3 a-10-78 ACC - INV
MAXIMUM DEPLETION WIDTH = 1.43 x 10m4 cm
DOPING DENSITY = 1.32 x 1014 cm-3
. .: 1011 ! I I I I I I
E, i3.20 -0.15 -0.10 -0.05 0 EC +0.05 SURFACE POTENTIAL
Figure 4- 1 I.- Surface State Density by Quasistatic Technique of Gate Oxide Witness; 8585 Lot 11B; Sample 532-2A (Can 2, Dot 3).
4-12
10’6
MAXIMUM DEPLETION WIDTH = I.40 x 1Om4 cm
DOPING DENSITY - 1.39 x 1014 cms3
E z
1Dl2
1011
1010 E” -0.20 -0.15 -0. 10 -0.05 0 0.05
SURFACE POTENTIAL EC
Figure 4- 12. -Surface State Density by Quasistatic Technique of Gate Oxide Witness; 8585 Lot 11B; Sample 532-2A (Can 2, Dot 8).
10
L,, I I I I I I I I I I -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2 4 6 8
VG, idts
Figure 4-13.-Hysteresis of Gate Oxide Witness; 8585 Lot 11B; Sample 532-2A (Can 2, Dot 3).
4- 13
I
low-frequency C-V characteristics and slope changes in the high-frequency
curves were observed in vacuum baking studies to correlate with absorption
of water. They could be reversibly removed and restored by vacuum baking
at 1OO’C and re-exposure to atmosphere, respectively. It is possible, there-
fore, that such contamination was present in Sample 532-2A (no vacuum
baking studies were made).
The hysteresis of the witness sample No. 532-2A is shown in Fig-
ure 4-13, with the solid and dashed curves corresponding to the same sweep
directions as in Figure 4-9. Two return (dashed) sweeps are shown, from
vG = -6 vol ts and -20 volts. The flatband voltage shifts are AVFB = 0. 2 volt
and 0. 5 volt for these two bias extremes.
GATE CAPACITANCE, FIATBAND VOLTAGE, AND SURFACE POTENTIAL DIAGRAM FOR 8585 LOT 8B
After completion of processing of 8585 Lot 8B, wafer probing, and
dicing, three chips were mounted in TO-5 packages for evaluation of the
channel stop metal, buried metal, and surface metal capacitors. These
chips were from wafer 498- 17, which also yielded several ZO-element
CCIRIDs. The oxide parameters for lot 8B, determined from these capac-
itors, are listed in Table 4-2.
The nominal oxide thicknesses (determined from sapphire witness sub-
strates) are listed in row (a) of Table 4-2 and the measured gate capacitances
in row (b). The capacitances per unit area of the channel stop, buried, and
surface metal levels are seen to be very close to those of 8585 Lot 4 (com-
pare to Table 3-l); however, the nominal oxide thicknesses associated with
each level of Lot 8B are thinner than in the earlier lot, indicating that the
dielectric constant is lower. This reduction is due to the less dense Si02
layer grown in the horizontal-flow configuration CVD reactor. Row (c) in
Table 4-2 gives the dielectric constant associated with each gate level, cal-
culated from the data in rows (a) and (b). It is seen to increase from 3. 31
for the channel stop metal to 3. 74 for the surface metal. The (average)
4- 14
Table 4-2. Oxide Parameters, 8585 Lot 8B
GATE OXIDE WITNESS
WAFER NO. 466B-25C
la) NOMINAL OXIDE THICKNESS 6%
1395
Ibl MEASURED COX If/cm21
1.94 x 10-B
lc) DIELECTRIC CONSTANT::: 3.06
td) FLA$t3”c;“I CAPACITANCE j o, B75
kl MEASURED VFB -0. 1 ,“olts,::.::’
(fl Nfc kharges/cm21 I
+1.2 x 10’0
CHANNEL BURIED SURFACE STOP METAL METAL METAL
498-17 498-17 498-17
1395 2370 4420
2.10 x 10-8 1.31 x 10-8 7.50 x 10-9
3.31 3.51 3.74
0.774 0. 846 0. 91
-1.3 -1.4 -0.56 -1. 6 -1.77 -0.86
+1.7 x 1011 +1.1 x 1011 +2.6 x lOlo
‘:‘CALCULATED FROM lal AND (bl
-:,-UPPER NUMBER FOR POSITIVE TO NEGATIVE VG SWEEP, LOYMR NUMBER VICE VERSA
dielectric constant increases in this manner since the ratio of the sputtered
SiO2 thickness to the LTCVD SiO2 thickness increases as the CCIRID struc-
ture is built up.
The measured flatband voltages are given in row (e) of Table 4-2. The
flatband voltages are low as was the case for the ear1ie.r Lot 4. The asso-
ciated fixed-charge densities (again assuming zero metal-semiconductor
work function difference) are listed in row (f). Whereas Nfc was relatively
uniform for Lot 4 and its witness sample (Nfc = + 1. 1 to 1. 9 X 10 11 /cm2),
for Lot 8B two of the gate levels (channel stop and buried metal) have a
similar Nfc - 10 11 /cm 2 while the witness sample and surface metal show
Nfc in the low 101’/cm2 range. This variation is undoubtedly due to upper-
level processing variables but at this time we have insufficient statistics to
correlate the effects of upper-level process steps on Nfc. The result, as
relates to the operating voltages for Lot 8B, is that the flatband voltage of
the surface metal is lower than that of the buried metal, opposite to the
situation that would be normally obtained with a uniform Nfc for all gate levels.
4-15
.I
. ..
In row (e) of Table 4-2, two VFB values are listed for the three CCD
gate levels corresponding to negative-going and positive-going gate voltage
sweeps, reflecting the gate oxide hysteresis. Figure 4- 14 shows the mea-
sured C-V curves for the three gate levels on one test capacitor chip (Chip C5).
Figure 4- 15 reproduces the computer plot of the measured low- and high-
frequency, compared to the ideal, C-V curves for the surface metal capacitor
on test chip ~6. Figure 4- 16 is the apparent surface state density calculated
from Figure 4-15. Midband Nss is 4 x 101l cm-2-eV-1 which is identical to
the Lot 8B witness sample, Figures 4-6 and 4-7.
The fact that the apparent surface state density and hysteresis of the
witness capacitors and the test capacitors on the completed CCIRID wafers
are essentially identical allows the conclusion that the upper level fabrication
process is to first order not affecting the InSb MOS characteristics. Some
flatband voltage shifting is evident, which is not surprising considering that
numerous dc and rf sputtering and rf plasma etching operations are involved
in the upper level processing. For all lots to date, no annealing operations -
2D, 1 I ’ M DATA ID NO. 6-M/2734-2
- DATE 1-21-78 SAMPLE 498-17-C5
16 -A = 1.868 x lo3 cm2 -40 F = 1 MHz
12 - (Left-Hand Scale) -30
= J
a- -20
O-6 I I I I I I I
-4 -2 0 2 4 63 VG, volts
Figure 4- 14. -C-V Characteristics of Channel Stop, Buried, and Surface Metal Capacitors; Wafer 498- 17; 8585 Lot 8B; Chip C5,
4- 16
0.4 - MAXIMUM DEPLETION WIDTH = 1.41 x 1O‘4 cm
0.3 - DOPING DENSITY 1.36 x = 1014 cme3
= 0.2 - cox 1.46 x 101 pf
AREA = 2.03 x 1O-3 cm2
0.1 - 2740 86 498-17 C6 5M a-3-78 ACC - INV
1 --~I 1 I I -4 -3 -2 -1 0
GATE VOLTAGE
I +1 +2
Figure 4- 15. - Low-Frequency and High-Frequency C-V Curves for Surface Metal Capacitor; Wafer 498-17; 8585 Lot 8B; Chip ~6.
2740 55 498-17 C6 5M a-3-18 ACC - INV
; ; & \ :* 5 ‘\
;; ' -LF-HF
'0 : : 'I :3
1:. *::. . .*-
. .- ;'
.: . . . . . . . . . . . *- -*. . . . . . . ...*.... -
.:'
MAXIMUM DEPLETION WIDTH = 1.41 x 10e4 cm
DOPING DENSITY = 1.36 x 1014 cme3
1011 ! 1- I I I I E, -D.M -D. 15 -0.10 -0.05 0 EC +o. 05
SURFACE POTENTIAL
Figure 4-16.- Surface State Density by Quasistatic Technique of Surface Metal Capacitor; Wafer 498- 17; 8585 Lot 8B; Chip C6 a
4- 17
were performed either during or after completion of the upper level pro-
cessing. Future studies to correlate C-V characteristics with each upper
level process step are required, along with investigation of intermediate or
post-anneal steps to more accurately control flatband voltages of each gate
level in the completed CCIRIDs.
Using the parameters in Table 4-2 and equations (3-4) through (3-6),
the surface potential plot for 8585 Lot 8B was calculated and is given in
Figure 4- 17. The substrate impurity concentration, CGXBM, and COXSM
are very nearly the same for lots 4 and 8B, and the slopes of the I,!~ versus
VG curves in Figures 4-17 and 3-7 are similar. However, since the surface
metal flatband voltage in Lot 8B is small, the eSSE curve in Figure 4- 17
overlaps the GSBE curve. Because the device is 4@ and does not require any
built-in flatband voltage differences, device operation is not in any way
affected by this.
-14
-12 -
-10 -
-a - VI = P -
’ 4,-
-4 -
-2 -
ND = 1.36 X 1014/cm3
RFACE METAL
"FB -1. a VOID -0. 9 volt
0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 VG, volts
Figure 4- 17. - Surface Potential versus Gate Voltage for Wafer 498- 17, 8585 Lot 8B.
4-18
TEST EQUIPMENT CONFIGURATION Y
General Configuration
The general configuration that was used for testing the 20-element InSb
CCIRIDs is shown in the block diagram of Figure 4-18. The array was tested
in a specially-designed cryogenic dewar based on a Heli-Tran liquid helium
transfer sys tern+. The dewar, block A in Figure 4-18, contains: a cold
stage with socket to accept CCIRID flatpack; low-temperature cavity sur-
rounding the device: cold spectral bandpass filter; FOV restriction; inter-
mediate temperature shield; and an intermediate temperature stage. A
buffer/driver circuit is mounted on the intermediate temperature stage.
Clock waveforms and dc voltages necessary to drive the CCIRID, block
B in Figure 4-18, were provided by commercially-available pulse generators
and adjustable dc supplies. Two test sets were used during the course of the
program, denoted as Test Sets 1 and 2. Test Set No. 1 is a rack-mounted
set of pulse generators and dc supplies which provides all needed waveforms
to operate the device. The rack includes a custom-built timing generator
which provides properly-timed pulses for triggering the waveform generators.
Set 1 does not contain any additional electronics for sampling or further
processing of the CCIRID output waveform. When operating with Set 1, the
device output waveform at point C in Figure 4- 18 was displayed on an oscil-
loscope, or alternatively, at point D at the output of an offsettable voltage
amplifier. Test Set 1 also includes a blackbody source and variable-speed
chopper for optical evaluation of the CCIRIDs. This test set was used for
most of the device testing in the program: for clock voltage/waveform opti-
mization; for CTE measurement; and for optical mode evaluation. Set 1 does
not include sample-and-hold (S/H) and other electronics plus computer inter-
face necessary for noise or detectivity (D:::) measurements. This equipment,
block E in Figure 4-18, is incorporated in SBRC’s CCD Array Test Set No, 2,
:zHeli-Tran Sys tern, manufactured by Air Products and Chemicals, Inc. , Allentown, PA.
4- 19
a---
Figure 4 .- 18.- General Test Configuration for ZO-Element InSb CCIRID*
CLOCKS AND
POWER SUPPLIES
HELITRAN
55” FOV
DEWAR
r m--B
7 CHOPPER
\20-ELEMENT CCIRID i
2.65j~m SPIKE FILTER
1 COMPUTER 1 j
SAMPLED OUTPUT
d---J i I L
@I ----------------- A
described later in this section, which also includes its own set of clocks and
power supplies, block B.
The 20-element InSb CCIRID chips (with 3N163 MOSFETs) were mounted
in 40-lead dual-inline flatpacks for testing in the Heli-Tran dewar. SBRC
has standardized on the 40-lead DIPS for various CCD array programs where
the lead count is sufficient to accommodate the input/output requirements.
The particular flatpacks used were purchased from the 3M Company, Elec-
tronic Products Division, St. Paul, Minnesota, Part No. SZ-80220-AC,
Multilayer Ceramic Dual-Inline Package, 40-lead, bottom-brazed.
4-20
During testing at SBRC, to facilitate optical inspection and chip access,
the flatpacks were not provided with a window over the package well. The
delivered CCIRIDs were provided with a 0. OlO-inch thick sapphire window
epoxy-sealed over the well of the package. Window sealing was carried out
in a nitrogen dry box. A photograph of a 20-element array mounted in the
40-lead DIP, with the sapphire window sealed over the well, is shown in
Figure 4- 19. Figure 4-20 shows a closer view of the InSb chip and MOSFETs
in the flatpack well, prior to bonding of the sapphire window.
CCD Array Test Set 2
The CCD Array Test Set No. 2 was used for D+ measurements de-
scribed later in this section. A photograph of this test station in its original
configuration is shown in Figure 4-21. The test console contains: a black-
body source and chopper; clock waveform generators; dc power supplies; a
time mark generator; signal monitoring equipment; and test electrical gen-
erators to operate and test a wide variety of CCD arrays in both linear and
area configurations. The helium storage dewar, transfer line, and Heli-
Tran dewar resting on the blackbody source can be seen in the right-hand
side of Figure 4-2 1. At the left of the Figure 4-21 is an HP9825 minicomputer
which has been replaced with an HP21 MXE Minicomputer system since the
photograph was taken.
A block diagram of the complete test station is shown in Figure 4-22.
It is composed of: the IR source; the minicomputer system and interface
equipment; the test console shown in Figure 4-21; monitoring oscilloscope;
Heli-Tran dewar; and Heli-Tran Cart equipment.
In the CCD Test Console, timing signals, including a master clock, are
generated by a switch-programmable timing generator, which supplies con-
trol signals to the: clock sources; CRT display; sample-and-hold; and
analog-to-digital converter. Clocking pulses for driving the CCD are formed
by nine Tektronix PG508 pulse generators capable of 50-MHz operation. Rise
and fall times are adjustable as well as upper and lower pulse levels up to
f 20 volts. DC bias voltages are generated by twelve HP6215A adjustable
4-21
Figure 4- 19. - 20-Element InSb CCIRID in 40-Lead Dual-Inline Package, with Sapphire Window Sealed Over Well,
I .
.?.
I ,.
. .I
.
Figure 4-20.- 20-Element InSb CCIRID Mounted in Dual-Inline Package, Prior to Sealing of Sapphire Window.
4-22
Figure 4-21,-- CCD Array Test Set No. 2.
HELI-TRAN CART EOUIPMENT TEST CONSOLE EOUIPMENT
__________ ~
L-!YzYYASSEMBLY II ADAPTER
f L.-.- -.- .-.-.-. J L ---_ t-
---------I I I
I BLACK- BODY
MONITOR TEKTRONIX
i
7704A
Figure 4- 22. - Block Diagram of CCD Array Test Set No. 2 and Heli- Tran Cart Equipment L
4-23
regulated supplies. These are referenced inside the test adapter for each
test configuration. A high-speed sample-and-hold/analog-to-digital converter
is provided to digitize the CCD output to 13-bit resolution. Conversion time
for each sample is less than 1 psec so that sample-and-hold feedthrough of
the signal pulse will not occur during digitization. Digitizer outputs are con-
nected to the computer via an optically isolated data bus. A thumbwheel
channel selector is provided on the sample-and-hold panel to route the output
of any single-array element to a panel jack for signal, noise, or spectrum
analysis. The high-speed A/D converter, which has a 900-nsec converstion
time, allows continuous and complete digital conversion at approximately a
l-MHz word rate.
The highlights of the HP MXE minicomputer are:
1. High-speed 192-k byte core memory
2. Dual 15-M byte storage discs
3. “Smart” Terminal . The terminal, HP2648A, contains prepro- grammed statistics packages as well as intermediate storage data.
Heli-Tran Dewar
The Heli-Tran dewar was developed for rapid device cooldown and
warm-up, and variable temperature control. The system consists of the
following:
1. Helium storage dewar
2. Coaxial transfer tube
3. Cooling head
4. Active temperature controller
5. Digital cold stage readout
Liquid helium:: is extracted from the storage dewar via the coaxial transport
tube and flows through the heat exchanger in the cooling head. A portion of
the boiloff is used to cool the outer section of the transport tube; the rest is
+Other cryogens can also be used resulting in different temperature ranges of operation.
4-24
exhausted. Inside the cooling head, shown in Figure 4-23, a control thermo-
couple and heater assembly are part of the active temperature control loop,
and an additional thermocouple is provided for digital temperature readout.
REMOVABLE HELIUM
300 K VACUUM
HEAT EXCHANGER. CONTROL TEMPER- INTERMEDIATE ATURE SENSOR, AN TEMPERATURE SHIELD CONTROL HEATER PROTECTION RESISTORS
AND OUTPUT DRIVE ELECTRONICS
InSb CCIRID IN N-PIN FLAT PACK
SPECTRAL ND FILTER ‘\LOW TEMPERATURE CAVITY
AND/OR APERTURE (4.2 TO 300 K1
STOP FOR VARIABLE LOW BACKGROUND
BACKGROUNDS GERMANIUM WINDOW
Figure 4-23. - Sketch of Low-Temperature Cavity, Shields, and Windows in Heli- Tran Sys tern.
Manually-controlled warm-up heaters are provided for rapid heating.
The remainder of the cooling head is similar to a small dewar with a cold
stage, on which the test device is located, separated by an intermediate
stage. The cold stage accommodates the 40-pin dual in-line package and
includes terminations and protective networks for each pin. The intermediate
stage contains buffer/driver electronics and an interconnecting plated shield
flat cable. The same type of cable is used to connect the test device to three
19-pin interface connectors.
Helium consumption after cooldown is approximately l/2 liter per hour
with normal heat loads. Typical cycle times (heat to 300 K, change sample,
reevacuate and retool) are less than 1 hour.
4-25
Photon Flux Calculations
Optical evaluation of the 20-element CCIRIDs was carried out with low
photon flux levels provided by a cooled 2. 65-pm narrow bandpass filter
mounted in the entrance window of the low-temperature cavity (Figures 4-18
and 4-23). This cavity and filter are thermally connected to the cold stage
and reach array temperature. Sandwiched above the 2. 65-pm narrow band-
pass filter was a l-inch diameter Pyrex glass plate which served to block
any longer-wavelength passbands that the filter might have. The outer window
of the dewar (Figure 4-23) was an 0. 040-inch thick uncoated germanium plate.
The measured transmission T(x) of the combination of narrow bandpass
filter, Pyrex plate, and germanium outer window is shown in Figure 4-24.
Signal photon flux was provided by the blackbody set at 800 K. The total
radiant emittance from a blackbody at this temperature is:
wbb = UT4
= (5. 6697 x lo-l2 watt cme2 Ks4)T4
= 2. 322 watts/cm2 at 800 K
or in terms of photons:
(4-2)
Qbb = o’T3
= (1. 52041 X IO11 set-’ cm-’ Kw3)T3
= 7. 785 X lOI phot/sec-cm2 at 800 K (4-3)
The transmitted radiant emittance passed by the filter combination, WFILT
and QFILT, was calculated in the usual manner by integrating the 800 K
spectral radiant emittance with the filter transmission curve of Figure 4-24:
WFILT (800 K) = WA (800 K)T (X)dh J-
= 1.068 X 10m2 watt/cm2 (4-4)
4-26
0.3
I I I I I I I I
FILTER + PYEX + Ce WINDOW
Figure 4-24. - Transmission Curve for 2. 65-pm Narrow Bandpass Filter, Pyrex Plate, and Germanium Outer Window.
QFILT (800 K) = / QA (800 K) T(h)dX
= 1. 416 x lOI phot/sec-cm2
where WA =- “,: (ec2’AT - $-’ wcmm2pmm1
& = 3 kc2’*T _ 4-l phot set- ‘cmw2~mw1
Cl = 3. 7415 X lo4 wcm-‘pm4
c2 = 1. 43879 x lo4 pm K
cl’ = 1. 88365 x lO23 set - lcm-2 C*m3
(4-5)
(4-6)
(4-7)
and A and T are in units of pm and K, respectively. Comparing (4-4) to
(4-2) and (4-5) to (4-3) shows that the filter/window combination attenuates
the blackbody radiant emittance by the factors Wbb/WFILT = 217 and
QbblQ FILT = 550.
4-27
The signal irradiance on the detector array depends on the blackbody
aperture area (Aaper ) and distance (D) from the aperture to the plane of the
array:
Hsiga Q. = (wFILT> QFILT)Aaper Sl!z lTD 2 (4-8)
where either WFILT or QFILT is used appropriate to whether energy or
photon units are desired. For Test Set 1, D = 11. 06 cm and the blackbody
aperture diameters range from 0. 380 to 0. 0140 inch. Substituting in equa-
tion (4-8), Qsig could therefore be varied from 2. 70 X 1014 down to 3. 66 X
1011 phot/sec-cm2, or equivalenty Hsig from 2. 03 X 10e5 to 2. 76 X low8
watts /cm2. For Test Set 2, D = 11. 0 cm and apertures range from 0. 200- to
0. 0125-inch diameter resulting in a comparable range of signal flux levels.
These are peak, rather than rms, signal flux levels. Figures and data in the
following sections give the value(s) of Qsig or Hsig, calculated using equa-
tion (4-8), corresponding to the blackbody aperture(s) used in the measure-
me nt.
The background photon flux incident on the array originates from the
300 K background viewed by the array through the 2. 65-ym bandpass filter
and field-of-view (FOV) restriction. The FOV in the dewar is established by
the aperture in the intermediate temperature shield and is 55’. We first
calculate QFILT (300 K) using the spectral radiant photon emittance of a
300 K-blackbody and T’(X) in the integral of equation (4-5). The transmission
T’(h) is in this case higher by a factor of two compared to the signal flux cal-
culation because the germanium outer dewar window is at ambient temperature
and does not attenuate the background radiation. The result is:
QFILT (300 K) = /
QA (300 K) T’(h)dh
= 3.3 x 1012 photlsec-cm2 (4-9)
4-28
The background photon flux QB on the array is then calculated using
*B = QFILT ( 300 K) sin2 (R/2) (4-10)
where 0 is the FOV. For R = 55’ the result is QB = 7 X 1O1l phot/sec-cm’.
Because of the possibility of radiation leaks, the background flux in the
dewar was checked by mounting a photovoltaic InSb detector of known area
and responsivity into a 40-lead flatpack and installing it in place of a CCIRID
in the dewar. The calculated short-circuit current I,, of the photodiode
corresponding to QB = 7 X 10’ ’ phot/sec cm2 was 3 namp. After temperature
stabilization of the low-temperature cavity and intermediate shield in the Heli-
Tran dewar, the measured I,, of the test photodiode ranged from 2. 0 to 5. 1
n-v, in reasonable agreement with the calculation, the latter current cor-
responding to 1. 2 X 1012 phot/sec cm2. Based on the calculations and mea-
surements, the background for the measurements is nominally stated as
1 X 10” phot/sec cm2.
TEST RESULTS
Electrical Input
For clock optimization and determination of CTE, the shift registers of
the 20-element CCIRIDs were first operated independently of the detectors by
biasing off the transfer gate and photogate, and applying signal pulses to the
fat zero input. The bottom waveform in Figure 4-2 shows the voltage applied
to the input buried gate, illustrating the case of three charge packets being
input. As with the two-element arrays, VID and VsC were set to dc voltages
for electrical input operation.
Figure 4-25 shows the output of device No. 498- 17-A3 with ten voltage
pulses applied to the FZ input. Twenty zeroes precede the first output pulse
confirming proper operation of the shift register. This CCIRID was delivered
to NASA in October 1978 as 20-element Serial No. 1. The output of Fig-
ure 4-25 is representative of device operation during the final testing, after
4-29
fC = 100 kHz
T - 68 K
50 psecldiv vcs = -0.1 volt
“T = -1 volt
@P = -2 volts
VFZ = 5 mv
Figure 4-25. - Output of ZO-Element InSb CCIRID No. 498-17-A3 with Ten Pulses Applied to FZ Input; CTE = 0. 992 * 0. 002 c
sealing the sapphire window to the flatpack. CTE as determined from both
single and multiple charge packets introduced into the CCD was calculated to
be 0. 992 f 0. 002.
In February 1979 device 498-17-A3 was retested at SBRC with resulting
outputs shown in Figure 4-26; the output for ten charge packets is reproduced
in Figure 4-26(a) and that for a single charge packet in Figure 4-26(b). CTE
was calculated to be 0. 9955 f 0. 0005.
Testing of several other 20-element shift registers from wafer 498-17
indicated that device A3 is typical in terms of CTE. CTE for all the devices
tested, and with various clock conditions, ranged from 0. 990 to 0. 996.
One 20-element array from the later lot 8585-IIB, No. 522-20-B4,
was bonded and similarly tested for CTE. Output waveforms for this device
are shown in Figure 4-27. A comparable CTE was calculated from the output
pulse trains for this CCD, CTE = 0. 994 * 0. 001.
Good agreement was observed among the CTE values as calculated by
the three methods discussed in Section 3; i. e. , equations (3-12), (3-14), and
4-30
5vl div
5vldiv
20 mvldiv
vlB
500 psec I div
la) TEN INPUT PULSES
fC
T
VID
vsc
@l
+2
“3
@l
500 psecldiv
(b) SINGLE INPUT PULSE
= 10 kHz
= 63 K
=o
= -7.8 volts
= -0.8 to -2.6 volts
= -3 to -7 volts
= -0.6 to -2.0 volts
= -3 to -7 volts
VOG
“FEF
QRST
“DD
4s
vcs
*T
QP
= -4.4 volts
= -1.0 volt
= -1.5 to -9.5 volts
= -10 volts
= +5 volts
= -1.2 volt
-0
=o
5vldiv
5v I div
20 mvldiv
Figure 4- 26. - Output of 20-Element InSb CCIRID No. 498-17-A3 (Retest, Four Months after Packaging); CTE = 0. 9955 f 0. 0005 D
4-3 1
fC = 125 kHz
T = 72 K
“ID = 0
“SC - -11.2 volts
2vldiv *1 = -9.2 to -13.2 volts
3 = -5.0 to -7.7 volts
% = -8.4 to -12.4 volts 20 mvldiv *4 = -5.2 to -9.2 volts
“OG = -6.5 volts
VEF = -1.7 volt
*ST = -1 t0 -10 VOltS
“DD = -10 volts
“ss = +5 volts
“cs = -2.8 volts
@T = -4.4 volts
QP = -2.5 volts
Time Uncalibrated
(c) SINGLE INPUT PULSE
Figure 4-27. - Output of 20-Element InSb CCIRID No. 522-20-B4 with Signal Pulses Applied to FZ Input; CTE = 0. 994 * 0. 001.
(3- 16). The uncertainties listed along with each CTE value give the total
range in the CTEs determined by the three methods, for the device operating
under the given set of test conditions. CTE calculated by each method for the
output waveforms in Figure 4-26 and 4-27 is listed in Table 4-3 as an example.
The absolute accuracy of the CTE values depends on the accuracy with
which the pulse heights can be measured on the oscilloscope. Estimating the
worst-case errors in determining the pulse heights, the resulting accuracy
in determining the CTE varies by the method employed as follows:
4-32
Table 4-3. - Calculated Charge Transfer Efficiency
LWlCE NC FIGURE EQUATION
498-17-A3 II
II
II
4-26 (a) 4-26 (al 4-26 (al 4-26 (bl
3-14
3-16. leaders
3-16, trailers
3-12
4-27 (al 4-27 la) 4-27 (al 4-27 Ibl
4-27 (bl
4-27 (bl
4-27 (cl
3-14
3-16, leaders
3-16, trailers
3-14
3-16, leaders
3-16, trailers
3-12
CTE
0.9%
0.996
0.995
0.995
0.994
0.994
0.993
0.994
0.994
0.995
0.995
Equation Accuracy of GTE
3-12 *o. 0007
3-14 *o. 0013
3- 16 *0.0007
(4-11)
CCD Output V,oltage and Charge Capacity
The output voltages observed for the ZO-element CCIRIDs were approx-
imately a factor of two higher than the levels for the two-element devices, in
both the electrical and optical modes of operation. Assuming equivalent
charge storage capacity per unit area for the two devices, a larger output
voltage was expected for the 20-element array because 1) its CCD gate area
is 30% larger than that of the two-element CCD, and 2) its output node capac-
itance Co is smaller due to a change in wirebond arrangement in the flatpack.
Rather than using a spare lead of the Dual-Inline package as in inter-
mediate tie point for the wirebonds between the output diode pad on the InSb
chip and the two 3N163 MOSFETs, as was done for the two-element arrays,
a small Ti-Au coated glass chip was mounted in the flatpack well to provide
this tie point for the ZO-element devices. This gold-coated chip is visible in
the lower left-hand corner of the flatpack well in Figure 4-20. A wirebond
first connects the output diode pad to the gold-coated chip; two additional wire-
bonds connect the gold-coated chip to the gate and drain pads of the source-
4-33
follower and switch transistors, respectively. The tie point was found to be
necessary because the output diode pad on the InSb chip is not large enough to
reliably accept two wirebonds. The capacitance of the gold-coated chip to
ground is much smaller than that of a floating lead of the flatpack and its
mating socket and provides a more favorable tie point.
The total CCD output capacitance (Co) was calculated for the 20-element
CCIRID using the known dimensions of the 8585 output diodes, gates, and pads
and the characteristics of the 3N163 MOSFETs. The output capacitance is the
sum of several terms:
(4- 12)
where COD = junction capacitance of output diode
CPAD = capacitance of metal lead to output diode plus bonding pad
‘SF = source-follower input capacitance
%s = gate-to-source capacitance of switch transistor
‘CSM = output diode to channel stop metal capacitance
C stray = stray capacitance
The p+-n junctions in InSb produced by Be ion implantation have been
shown by capacitance-voltage measurements to be abrupt, one-sided junctions
obeying the familiar relationship:
(4- 13)
For Es = 17. 8Eo, ND = 2 X 1014/cm3, VBI = 0. 2 volt and VR = 0, equa-
tion (4- 13) yields CCD/AJ = 1. 123 X 10m8 f/cm2. The output diode is 1. 9 x
2. 0 mils or 2. 45 x 10e5 cm2 resulting in COD = 0. 28 pf. Note that COD de-
creases as the square root of the reverse bias VR, but COD does not decrease
significantly from the VR = 0 value for the reverse biases used.
The output diode bonding pad and metal lead interconnecting the junction
contact with the pad comprises the largest capacitance contributing to Co.
This contribution will be essentially absent in subsequent InSb CCIRID designs
4-34
utilizing integrated output circuits. The pad and its metal lead are delineated
on the buried metal level. (Th e overlying insulator is subsequently etched
over the buried metal output diode pad and contacted by pad metal. ) The
bonding pad area is 5 X 5 mils or 1. 61 X low4 cm’, and the area of the metal
line leading to the output diode is 7. 2 X 10m5 cm2 giving a total area of 2. 33 X
loo4 cm2. The cumulative oxide thickness under the buried metal pad and
lead is (for 8585 Lot 8B) 335Oi (the oxide in this region is not etched as it is
in the CCD channel), resulting in
C KOXEoAPAD
PAD = tPAD
= 2. 24 pf (4- 14)
The dielectric constant KCX in this calculation has been interpolated from the
data in row (c) of Table 4-2.
The silicon 3N163 MOSFETs contribute the CSF and C gs
capacitances.
From the manufacturer’s (Siliconix, Inc. ) data sheets, the source-follower
input capacitance CSF was calculated to be 1. 9 pf including the effect of
Miller Feedback with l-A, 2 0. 1. Also from the data sheet, Cgs = 0. 7 pf.
The output diode to channel stop metal capacitance, CCSM, arises from
the necessary overlap of the p+ region by the CSM, which is 0. 2 mil on the
8585 layout. The effective perimeter is 6. 8 mils giving an overlap area of
8. 8 X 10m6 cm2. From Table 4-2, the capactiance is 2. 1 X lo- f/cm2 8 re-
sulting in CC-M = 0. 2 pf. The capacitance of the output diode to the buried
metal output gate, resulting from a small overlap area, is much less than
CCSM and is neglected.
Stray capacitance, arising from the wirebonds and gold-coated chip
(bond tie point) is estimated as - 1 pf based on previous experience. Summing
the contributions to Co gives 6. 32 pf. We take 6 pf to therefore represent
a reasonable estimate of Co.
The gate area of the 20-element CCD is 0. 5 X 4. 2 mils or 1. 35 X
10m5 cm2 compared to 1. 03 X 10s5 cm2 for the two-element device.
4-35
Combined with the lower estimated capacitance, the output voltage levels of
the 20-element array should be higher by the approximate factor (1. 35/ 1. 03)
x (10/6) = 2. 18 if the CCD charge capacity is the same. This is in good
agreement with observed output voltages for the two devices. The maximum
observed output voltage swing with electrical input was 60 mv for the 20-
element CCIRIDs compared to 30 mv for the two-element device. Corre-
sponding values for optical input were 50 mv and 25 mv, respectively. Using
equation (3-17), a 60-mv output swing with Co = 6 pf corresponds to a charge
Q voco --- q- 0. 9q
= 2. 5 x IO6 holes (4-15)
Investigation of the correlation between charge capacity estimated from
the surface potential diagram (Figure 4-17) and that calculated from the mag-
nitude of output voltage [equation (4- 15)1 h as not yet been carried out in detail
over the range of clock conditions. A calculation was made under the one
set of clock conditions for which V, = 60 mv, device No. 498- 17-A3, which
indicated agreement to within 6%, confirming the general validity of the sur-
face potential diagrams and the calculations leading to equation (4- 15).
With regard to the interband tunnel current calculations of Section 2,
study of the surface potentials corresponding to the clock voltages recorded
throughout operation of the various devices (both two-element and 20-ele-
ment) -- referring to the potential diagrams Figures 3-7 and 4-17 -- indicated
that proper CCD operation was maintained with empty-well surface potentials
under either buried or surface metal gates, or both, in the range of -6. 0 to
-8. 3 volts, averaging -7. 0 volts. Increasing a particular clock voltage an
additional 1 or 2 volts beyond this point produced no change, but beyond this
the dynamic range at the output was observed to decrease. Whether the
additional charge for the high clock levels results from thermal mechanisms,
tunneling, or avalanching remains to be ascertained from detailed studies in
this bias regime. In the interim, apparent freedom from substantial inter-
band tunneling out to Ps = -8 volts is consistent with the calculations leading
4-36
to Figure 2-3. Such a calculation must be considered as a first-order
approximation to the actual situation in the device for at least three reasons:
1. Anderson’s development considers fields only in the x-direction, i. e. , such as for a capacitor or gate of infinite extent in the y- and z-directions. In an actual CCD, even with all other conditions being ideal, electric fields exist both in the y- and z-directions as well: tangential fields at the channel edges, and tangential fields established between gates during the transfer operation. Consider- ably more detailed calculations are required to include all the fields in a dynamic CCD model and to relate them to possible tun- neling and/or avalanching mechanisms, but it is possible that these fields can be higher than that in the x-direction considered in Fig- ure 2-3.
2. It is discussed in Section 5 that the MOS flatband voltages, up to this point in the report discussed as a precise value VFB, are for the present devices characterized by a mean flatband voltage VFB and a near-Gaussian distribution about the mean. This has several effects. In terms of the empty-well surface potentials associated with CCD operation, the effect translates to an average QssE and G with corresponding distributions about these mean surface potentials. If for example E = -8 volts, some regions beneath the buried gate may have local surface potentials of -9 volts or -7 volts; the former regions will have a higher tunnel current density than that associated with the average $. This effect like- wise complicates the first-order calculation in Section 2.
3. Material imperfections or inhomogeneities if present can create locally-higher electric fields with effect similar to (1) and (2).
Optical Input: Multiplexing Mode
The photogates and transfer gate of the 20-element CCIRID being inde-
pendent of the CCD shift register allows the device to be operated in either a
multiplexing or TDI mode, as was discussed in Section 3. Most device oper-
ational testing during this contract used the former clocking mode. The top
two waveforms shown in Figure 4-2, the @p and @T clocks, are appropriate
to the multiplexing mode where either TINT = NBTC = 20TC for repetitive
multiplexing (integration time equal to readout time) or TINT > 20TC for
integration times exceeding readout time.
Referring to Figure 4-2, the CCIRID photogate tip is clocked to voltage
VP2 (approximately -5 volts for wafer 498-17) during the integration period
to form the collecting deep depletion regions beneath the semitransparent
4-37
gates. At the end of an integration time, the accumulated signal charges in
all twenty detectors are transferred simultaneously into the register by turn-
ing on the transfer gate in phase with CCD phase @4 (the detector input ports
are under the 64 buried metal). The detector signal charges are then trans-
ferred out of the CCD at rate f,. The first output signal is from the detector
nearest the output (arbitrarily denoted detector No. 20) and, 20 clock periods
later, the last output signal from detector No. 1. If TINT = NBTC, succes-
sive samples from detector Nos. 20, 19, etc. , will follow without intervening
zeroes; when TINT > NBTC, the output pulse train will be followed by a
number of zeroes until the transfer gate initiates the transfer and readout
cycle again. This latter is the case for the output pulse trains illustrated in
this section. Trailers will be seen following the output pulse train established
by the register’s CTE. The output signal pulses originating from each de-
tector in the array may then be sampled by a S/H circuit once each integra-
tion time or integral number of integration times; for example, detector
No. 20 is shown being sampled and held in Figure 4-2,
After establishing CCD clock levels @l - @4 for optimum CTE using
electrical input, for most devices tested only very small changes, if any,
were needed in one or more clocks to optimize the output pulse train in the
optical mode of operation. With @l - @4 set at their levels determined from
the electrical input test, and with no change in output circuit parameters
(vOG> @RST) VREF), the test pulses were first removed from the input
buried gate by setting VIB2 = VIB1. Then Qp was set at a dc level a few volts
more negative than the buried metal flatband voltage, and @T was pulsed from
V T1 z surface metal flatband voltage to VT2, 3 or 4 volts more negative than
vT1, as starting parameters. For a given signal photon flux level, integra-
tion time, and temperature, @p and @T were then adjusted for maximum
signal magnitude and uniformity, while at the same time examining and
minimizing dark current with the blackbody aperture covered.
Fat zero charge can be introduced into the register either optically or
electrically. Background flux Q, introduces an optical FZ charge which
4-38
increases linearly with QB and integration time. Because of the relatively
10~ QB = 1012 phot/sec cm2 and the range of integration times explored in the
present tests, the optical FZ was negligible and the FZ input was utilized.
With VID = 0, the dc levels of VIB and VsC were adjusted to leak in the small
(- 10%) FZ level to minimize the output pulse train trailers.
A final remark with respect to the clock diagram of Figure 4-2 is that
improved operation was obtained by clocking the photogate op from VP2 to
VP1 as shown although detector signals were observed with Gp held at a dc
voltage VP2. @T is first switched from VT1 to VT2 followed by @p being
dropped from Vp2 to Vpl. This creates a push-clock, instead of a drop-
clock, transfer mode where the charge is pushed out of the photogate, into
and across the transfer gate, and thus into $4, when @p switches from Vp2 to
VPl.
Operation of ZO-element CCIRID No. 498- 17-A3 in the multiplexing
mode is shown in Figures 4-28 through 4-30 for three different temperatures,
integration times, and CCD clock frequencies. In each figure, the oscillo-
scope photograph on the left is with the array illuminated by the blackbody
(Q sig is listed in each figure), and on the right, with the blackbody aperture
blocked. In Figure 4-28, the IR signal was chopped with the chopper running
at a low frequency fchop c< TINT- ‘; . zn the other two figures the chopper was
not running, giving a dc signal flux. The top two waveforms in each photo-
graph are the transfer gate and photogate clocks. In each case TINT > NBTC,
varying from 50 to 70 TC. In the figures, readout of all 20 detectors is
evident. The magnitude of the trailers correlates with the’CTE measured by
means of the electrical input. Although the array characteristics versus
temperature have not been systematically studied up to this point (TINT, f,,
QB, and T are all interdependent variables and a considerable characteriza-
tion effort will be necessary to establish performance versus temperature),
devices have been operated from the nominal temperature of 77 K to cl0 K.
At 77 K, dark current is seen in the output (Figure 4-30), and presently-
available devices show better performance at temperatures in the range of
4-39
Figure
Svldiv
Svldiv
20 mvldiv
I ml psec - WITH IR SIGNAL
T ,NT = 700 psec = 70 TC
Osig = 2.7 x 1014 phlsec cm*
'C = 1M) kHz
T = 60 K
V ID =’ V,B = -3.7 volts
“SC = -2.9 volt5
“1 = -2.4 to -4.4 volts
@2 = -4 to -9.2 volts
APERTURE BLOCKED
03 = -2.4 to -4.4 volts
@4 = -4 to -9.2 volts
“OG = -6.2 volts
“REF = -1.6 volt
@RST = -1 t0 -10 VOltS
“DD = -10 volt
“SS = +5 volts
“cs = -1.6 volt
4-28. - 20-Element CCIRID No. 498- 17-A3 Operating at 60 K in Multiplexing Mode with Chopped IR Signal Input.
b-2 ms-----l WITH IR SIGNAL
TINT = 5 ms = 50 TC
Qsig = 3.7 x 1013 ph I set cm2
‘C - 10 kHz
T =4OK
“ID = o
“IB = -3.7 volts
“SC = -2.9 volts
@l = -2.4 to -4.4 volts
62 = -4 to -9.2 volts
*3 = -2.4 to -4.4 volts
Figure 4-29. - 20iElement CCIRID in Multiplexing Mod
APERTURE BLOCKED
$4 = -4 to -9.2 volts
“OG = -6.2 volts
“REF = -1.6 volt
“RST = -1 to -10 volts
“DD = -10 volts
“ss = +5 volts
“CS = -1.6 volt
No. 498- 17-A3 Operating at 40 K
e, TINT ’ NBTC ’
4-40
b-400 llsec+ WITH IR SIGNAL
T ,NT = 1.2 ms = 60 TC
Qsig = 1.2 x 1014 ph I set cm2
‘c - 50 kHz
T - 77 K
“ID = 0
VIB = -3.2 volts
vsc = -4.5 volts
.+ = -2.8 to -9.5 volts
92 = -4.8 to -8 volts
+3 = -4 to -9.5 volts
APERTURE BLOCKED
“4 = -3.9 to -8.2 volts
VOG = -5.0 volts
“EF = -1.7 Volt
+RST= -1 to -10 Volts
VDD = -10 volts
V 5s = +5 volts
“CS = -1.1 volt
Figure 4- 30. - 20-Element CCIRID No. 498- 17-A3 Operating at 77 K in Multiplexing Mode, TINT > NBTC c
60 to 72 K, where most of the measurements have been made to date. The
lower-than-nominal operating temperatures are due to the typical device
storage times (a measure of dark current) on the wafers processed in this
contract being considerably shorter than the values predicted from material
parameters, as well as storage times measured on selected high-quality InSb
substrates. This situation has been correlated with substrate properties and
is discussed further in Section 5.
The output characteristic of another 20-element CCIRID from 8585
Lot 8B, 498-17-B2, is shown in Figure 4-31, with all test conditions listed
in the figure. In this case, the temperature has been reduced and the clock
frequency decreased to -1 kHz, allowing a relatively long integration time
4-41
5v I div
-WITH IR SIGNAL
20 mvldiv
-APERTURE BLOCKED
fC = 1.250 Hz
T = 31 K
v,D = 0
VIB = -2.ovolts
V sc = -8 volts
@l = -2.6 to -4.4 volts
9 = -3.4 to -7.0 volts
= *3 -2.7 to -5.0 volts
= 64 -3.7 to -6.9 volts
VOG = -5 volts
VREF = -1.4 Volt
“Rg= -1 to -10 volts
V DD = -10 volts
v ** = +5 volts
v(.. = -1.5 volts
I 16 ms I
TINT = 40 msec = 50 TC
Qsig = 3.7 x 1012 phlsec cm2
Figure 4-31.- ZO-Element CCIRID No. 498-17-B2 Operating at 37 K in Multiplexing Mode, TINT > NBTc.
T INT = 50 TC = 40 msec:::. This illustrates the very high responsivities that
can be obtained with integrating arrays such as the InSb CCIRID. The gen-
erally used figure-of-merit describing the responsivity of IR detectors is the
voltage responsivity
RI = H VS
sig AD (4- 16)
where RX is the responsivity at wavelength x in volts/watt, V, the device
signal output voltage, H sig the incident signal irradiance in watts/cm’, and
AD the detector area. Hsig corresponding to the blackbody aperture used for
Figure 4-31 is 2. 78 x 10s7 watts/cm2, and the detector area is AD = 1. 17X
10s5 cm2 giving
R2. 65 pm = 30 mv
(2. 78 x 10-7) (1. 17 x 10-5) = 9 X lo9 volts/watt (4- 17)
+This is not the longest integration time achievable at this temperature, but one conveniently set by the test set’s time mark generator for the particular clock frequency chosen here.
4-42
Integration time is, of course, specified by system design and cannot be in-
creased arbitrarily, but this calculation serves to illustrate that the InSb
CCIRID is a device with characteristically high voltage responsivity.
The normalized signal-to-noise ratio, or detectivity D*:, was roughly
estimated for device No. 498-17-B2 under the test conditions of Figure 4-31.
The detectivity at the peak wavelength Xp is calculated from the standard
equation for D’:: using 1/2TINT as the bandwidth:
D’:x = 2 P
(4- 18)
where the terms have been previously defined and V, is the noise voltage.
Since signal or dark current variation from element-to-element in the output
pulse trains could be repeatably measured on the oscilloscope to better than
2 mv, a first estimate of noise is V, 5 2 mv. Taking V, 2 30 mv and sub-
stituting in equation 4-18 gives
D:i:X 2 1. 1 x 1011 cm Hz+/watt P
For accurate Da measurements, array 498-17-B2 was shifted to CCD
Array Test Set 2. The voltage amplifier shown in Figure 4-18 (Av = 10) was
installed in the interface box for the 20-element array. Also a new time
mark generator for the 20-element CCIRID which was compatible with Test
Set 2 was required, which was designed and fabricated. On Te<t Set 2,
signal and noise were measured for each element using a synchronized
sample and hold amplifier. The sampled outputs were then digitized and
stored in the HP21-MX memory where signal, noise, and D::C calculations
were made. Thirty-two lines of signal (blackbody on) and 32 lines of back-
ground (blackbody off) data were taken and analyzed by the minicomputer to
find averages, variances (noise), and D+.
The results are plotted in Figure 4-32; test conditions are listed in the
figure. DZ$p ranged from 1.5 to 1.13 X lo11 cm Hz+/watt. The average
4-43
1012k TINT = 6 msec
I t = 5 kHz Hsig = 1.24 x 10m6 watts/cm2
-T = 55 K AD - 1.17 x lo-5 cm2
1010 20 18 16 14 12 10 8 6 1
DETECTOR NO.
Figure 4-32. - Measured D+ of 20-Element CCIRID 498- 17- B2 in Multiplexing Mode.
signal was 431 mv and the average noise 13. 75 mv (both with 10x voltage
gain). The average array D:~x is therefore P
D 9 = 1, 35 x 1011 cm Hz$/watt P
Optical Input: TDI Mode
Twenty-Element No. 498- 17-B2 was also operated with photogate and
transfer gate timing changed so as to simulate the time-delay-and-integration
mode of operation, thereby demonstrating the feasibility of using InSb CCIRIDs
for this on-chip signal processing function. In TDI, and where the CCD array
has one bit/detector as in the present case, the condition for TDI is TINT =
TC’ The period @T is therefore reduced to TC and is in phase with G4, as
shown in Figure 4-33. In a TDI sensor, the array is scanned across the
scene at a rate such that the image of a given scene element moves along the
array in synchronism with the movement of the charge packets in the CCD
register. As each charge packet reaches a gate with a detector input port
(84 in this case) once each clock period, @T transfers in another packet of
detector charge which adds to that already in the register. Repeating this
process N times, where N is the number of detectors in TDI, results in an
output signal N times larger than each individual detector output. Evaluating
a CCD array in the actual system TDI mode necessitates a precision scanning
optics system to scan a focused spot along the array.
4-44
DElECTOR BIAS &p
TRANSFER PULSE 4
44
43
‘RST
I VT .CVi = NVi
N REG I STER OUTPUT
vo
mnl-ll II IPI
Figure 4-33. - InSb CCIRID Timing Diagram for Demonstration of Time-Delay-and-Integration Mode (TINT = TC)a
The TDI mode can be simulated with floodbeam blackbody radiation to
show the addition of the individual detector signals using the timing diagram
in Figure 4-33. With the array illuminated uniformly with signal radiation,
the photogate is switched from an off to an on condition as shown in the top
waveform of Figure 4-33. This initiates charge integration by the detectors
and transfer of the detector charge into the register each TC. The resultant
output waveform is a pulse train shown at the bottom of Figure 4-33. The
first charge packet to reach the output is from detector 20, the second the
sum of 20 plus 19, the third the sum of 20 + 19 + 18, and so on, forming an
“ascending staircase” pulse train. The output voltage saturates at a voltage
V T = G”i, where the Vi are the individual detector outputs; if all Vi are
equal, then VT = NVi. The output pulse height remains at VT as long as @p
is biased on. When @p is switched off, the opposite process occurs and a
“descending staircase” of output pulses results. Twenty-element array
498-17-B2 operating in this manner is presented in Figure 4-34, showing
that the TDI addition process is correctly obtained in the InSb CCIRID.
This section has described the test data obtained under this contract
for the ZO-element CCIRIDs and their witness/evaluation devices. A few
devices have been operated over a range of integration times and tempera-
tures, and Dg: has been measured in the multiplexing mode for one device
4-45
Figure 4-34. -TDI Operation of ZO-Element CCIRID 498- 17-B2.
under one set of TINT/T conditions. It is evident that much additional test
and characterization of the 20-element arrays is required before their com-
plete operational data and performance capabilities are shown. This is
further underscored by the fact that the optical mode data were obtained from
only one wafer lot. The test results obtained to date, however, have been
sufficient to demonstrate the first successful design, fabrication and opera-
tion of a fully monolithic InSb infrared CCD array, and to prove the feasi-
bility of this concept.
Some of the factors which influence the current performance of these
arrays have been identified, along with means of improvement, and are dis-
cussed in the next section.
4-46
Section 5
DISCUSSION OF TEST RESULTS
CHARGE TRANSFER EFFICIENCY
Parallel-Edge Surface State Loss
During testing of the two-element InSb CCIRIDs described in Section 3,
the observed CTE of the CCDs was assumed to be attributable to the rela-
tively high fast surface state densities measured for the gate oxide witness
sample, i. e. , midband Nss of 10” cmm2-eV-l (Figure 3-5). Since the
majority of the surface states within the channel area are kept filled by the
fat zero charge, the inefficiency mechanism to be considered is that due to
parallel-edge surface state loss. The “parallel edges” refer to the small
areas along the edges of the CCD channel (parallel to the direction of charge
transfer) which do not benefit from the fat zero charge. The resulting in-
efficiency is given by
E yqkTNssRn(p+l)
ss = cOXA+sig
where y = AS - AFZ
AS
(5- 1)
(5-2)
AS = total area swept by charge packet (fat zero + signal)
A FZ = area swept by fat zero charge
P = number of phases in CCD
Because the surface potential at the edges of the channel does not increase
abruptly to its midchannel maximum value, the area AFZ filled by the FZ
charge is smaller than the geometric area of gate length times gate width.
When signal charge is transferred down the register, the sloping edges of the
well results in the signal charge sweeping a larger area AS = AFZ + AE,
where AE is an additional area along the channel edges. The factor y (5-2)
represents the ratio AE/AS, or the fraction of the total swept area in which
5-l
the surface states will contribute to transfer loss. y is a function of channel
width; it can become large for devices with very narrow channels, and is
small for wide-channel registers. The 8585 registers are relatively wide
(4 mils) for which y < 0. 1. Using equation (5-l) and temperature and signal
charge appropriate to the CTE measurements in Sections 3 and 4, the in-
efficiency F, s was plotted versus N,, in Figure 5-l. The cross-hatched area
in the figure represents a range from the probable upper bound Y = 0. 1 to a
lower bound y = 0. 025.
- Coxd&ig = 1.6 x 10m8 coulombslcm2
I I I I lmnlll I I 1 Ill..1 I I I I .#.J 1o-5 IO10
0.99999 10’1 1012 1013
SURFACE STATE DENSITY. N,, cmm2 -eV-*
Figure 5- 1. - Calculated Inefficiency Range versus N,, for Parallel-Edge Surface State Loss.
For N,, z 101’ cm-‘-eV-‘, the measured surface state density for
8585 Lot 4 with gate oxide deposited in the vertical CVD reactor, Figure 5- 1
predicts a surface state density-limited CTE in the range of 0. 991 to 0. 998,
in good agreement with measured values (Figures 3- 11 and 3- 12) about 0. 995.
5-2
It was, therefore, anticipated that the later lots 8B and 11 B, for which quasi-
static C-V measurements on their witness wafers indicated a lower midband
N ss in the 2 to 5 X lOl1 cm-‘-eV-’ range (Figures 4-6, 4-7, 4-l 1, and 4-12),
would result in somewhat improved CTE. Taking N,, 2 3 X loll cm-‘-eV-‘,
Figure 5-l shows that CTE would be expected to improve to a range from
0. 997 to 0. 9993 (an increase which would be clearly detectable in the mea-
surements) if surface state loss were the dominating mechanism. Evidence
was simultaneously being obtained which indicated that the N,, calcu1ate.d
from the QS C-V curves was artificially high as well, and that true N,, was
much lower than 1011 cm-‘-eV-‘, which offered the promise of even higher
CTE.
The measured CTE for the Lot 8B and 1 IB registers was, surprisingly,
not improved from the earlier lot, ranging from 0. 992 to 0. 9955 (Figures 4-25
through 4- 27). Although the model and assumptions leading to Figure 5- 1
could certainly lead to errors in quantitative calculation of CTE for a given
N SS’ a three-to-fivefold decrease in N,, should regardless produce detectable
changes. Concurrently with these measurements, evidence was being obtained
on SBRC’s Two-Dimensional IR Array IR&D Project (in which InSb surface and
gate oxide research is being conducted) indicating that the granularity of the
SiO2 layer deposited by low-temperature CVD was influencing the C-V char-
acteristics and complicating N,, analysis. These effects were particularly
pronounced for the horizontal-flow CVD reactor used for 8585 Lots 8B and
11 B. The question of whether this granularity might be influencing the CTE
for the horizontal reactor gate oxide devices was therefore examined.
Transfer Inefficiency Due to Lateral Surface Potential Fluctuation
As was discussed in Section 4, experimental evidence of the presence of
lateral nonuniformity of surface potential due to patchiness of the CVD Si02
oxide has been obtained. This effect displays itself in C-V diagnostics by a
broadening and shallowing of the low-frequency characteristic, which is to be
expected from the superposition of a variety of surface regions differing in
either oxide fixed charge or permittivity. This results in erroneous
5-3
determinations of the surface state density when capacitance methods are
used. A C-V characteristic for an InSb MOS sample produced in the hori-
zontal-flow reactor is shown in Figure 5-2, which illustrates this effect. The
result of the quasistatic C-V analysis for the data of Figure 5-2 indicates an
apparent surface state density in the high lOlo eV-lcrnm2 range. However,
inspection of the measured low-frequency C-V curve reveals a symmetrical
appearance compared to the ideal which indicates the presence of lateral non-
uniformity. This effect masks the true surface state density as has been
shown by Castagne, et al’. A measurement of the flatband voltage distribu-
tion by the method of Chang 8 is shown in Figure 5-3 using the high- and low-
frequency data of Figure 5-2. This distribution can also be calculated7 from
a simple parallel array model of equal area 15OOi diameter patches with
uniform charge density, but obeying a Gaussian distribution of charge for the
noninteracting patches. When the measured distribution of flatband voltages
in Figure 5-3 is used to calculate the low-frequency capacitance from the
8 ideal capacitance ,
(v - VFB) f tv-& dVFB the results totally account for the quasistatic curve in Figure 5-2. Thus
surface state densities obtained from capacitance measurements on the
LTCVD Si02-InSb MOS devices will be higher than the true density due to the
spread out of the C-V curves from the nonuniform parallel patch array. This
result has been further verified using the frequency test of Chang 8 by high-
frequency C-V measurements from 200 Hz to 1 MHz, which show no disper-
sion in depletion, indicating the lack of surface states.
Laser Mie scattering studies of Si02 particulates in CVD reactors9
have shown that the basic particle nucleation size is between lOOOK and 2OOOi.
This is further corroborated by the SEM photomicrograph (Figure 5-4) of the
horizontal-reactor CVD oxide, which shows a mean particle size of 1500A.
Thus, there is little doubt that the pyrolytic CVD process in the horizontal
reactor produces a granularity of the same dimension as the surface potential
fluctuation length, laterally across the interface.
5-4
1. (
0. !
0. E
8 u ‘u
0. 7
0. 6
0. 5
I.
)-
I-
I-
..,
‘-----*n -. : :-
.: . .:
MEASURED : * QUASISTATIC- . ‘: AT 100 mv/sec : a:
. - . . . . : -. 4.
MEASURED 1 MHz . .
I
: :
. . . . . . . . ..e.........e.... -.- . . . . .
TD = 71 K 1 I
-1.5 -1.0 -0.5 0.0 0.5 1.0
. . . . . . . . . . . .._......._....-. . . ..-..-.-.I . .._......._....-. . . ..-..-.-.I
VG Ivolts)
Figure 5- 2. - Measured C-V Characteristics of InSb MOS Sample with Gate Oxide Deposited in Horizontal-Flow CVD Reactor,
3.5
3.0
wj- 2.5
z E 2.0 -2 =’
1.5
1.0
0.5
-2. 0
I I I I I I I , ,
-1. 0 VFB tb’dts)
Figure 5-3. - Measured Flatband Voltage Distribution for Sample in Figure 5-2.
5-5
Figure 5-4. - SEM Photo of LTCVD SiO2 Granularity Resulting from a Horizontal CVD Reactor, Showing Mean Size of 15OOA.
Besides the effect on interface diagnostics, CTE of a CCD also may be
influenced by localized variations in surface potential. Charge can be trapped
in the small local potential wells and variably emptied depending on lateral
electric field amplitudes. Figure 5-5 demonstrates how this variable trapping
can cause charge transfer inefficiency. Figure 5-5(a) is a schematic of a 4@
CCD and the surface potentials under the gates while transferring a full
bucket of charge from 42 to @3. As charge flows across the traps, they are
filled to a level consistent with a small lateral field and a full bucket. Charge
is left behind in the traps, resulting in an incomplete charge transfer. Fig-
ure 5-5(b) shows how the charge is recovered in a trailing empty bucket due
to the high lateral field tipping or slanting the edge of the trapping wells.
The quantity of charge which is trapped can be calculated to first order
by modeling the trap as a well of mean diameter 3 and tipping the trap due to
a constant lateral electric field across the trap, as shown in Figure 5-6. The
trapped charge difference between having a full well pass under the gate fol-
lowed by an empty well; i. e. , the charge spilled from a single trap, is
5-6
K -
TRAPS EMPTY
FULL
ULL BUCKET PASSES ULL BUCKET PASSES
TRAPS ARE FILLED - TRAPS ARE FILLED
-i-l- EMPTY
EMPTY BUCKET PASSES UNDER GATES:
TRAPS ARE EMPTIED
lb1
Figure 5- 5. -Charge Transfer Inefficiency Mechanism due to Trapping by Localized Surface Potential Variations.
1 T Ey WHEN GATE IS Ey WHEN GATE IS
“9 . I
#S SURFACE ‘ACE POTENTIAL VARIATION POTENTIAL VARIATION DUE TO CHARGE PATCH TO CHARGE PATCH
Figure 5-6. - Release of Trapped Charge from Trap in Region of Large Lateral Field.
5-7
where Cox is the capacitance per unit area of the gate, At the area of the
trap and Ey the magnitude of the lateral electric field. The total charge dif-
ferential trapped under the gate may be found by summing the individual
traps:
overCgtt?trap s cox w;l A$,/2 (5-5)
where w is the gate width and a$, the difference in surface potential between
an empty and full bucket. The charge transfer efficiency is then:
where L is the gate length. This result is plotted in Figure 5-7, also in-
cluding the inefficiency due to fast surface states as a linear sum
E a
total = ‘ss +x (5-7)
The results of this model predict that a trap diameter (or particle size) of
less than 2501 as well as a low surface state density of * 10 11 cm- 2ev- 1 are
both needed for a CTE of 0. 999. It should be noted that the CTE calculated
in Figure 5-7 agrees well with the measured data, i. e. , CTE = 0. 995 for
a = ISOOK. A more sophisticated model for charge trapping which takes into
account the effects of surface states upon the trap well depth is being devel-
oped. The variations from this effect are not expected to be large, but are
being investigated for accuracy. Preliminary calculations show that the
results are relatively insensitive to patch depths down to the thermal limit
kT - = 6.6 mv (5-8) q 77 K
and thus the simple model for transfer inefficiency can be relied on with
small error. The critical parameter is 2, the lateral variation of the sur-
face potential, Since the experimental data from a variety of techniques
indicate that the Si02 films deposited at -2OO’C in the horizontal-flow
5-8
1012cm-2 - eve1 -2
0.95 5
0.9 I I I I 10-l 0 500 1Mx) 1500 zoo0
MEAN PATCH LIlAMElER 8 (il
Figure 5- 7. - Calculated CTE versus Mean Patch Diameter.
I I I 10-5
-2
AMS-2600 CVD reactor are characterized by a patchiness with2 2 15OOi, we
have confidence that the CTE of the ZO-element arrays fabricated to date is
limited by this effect.
Fortunately, this inefficiency mechanism does not arise from a funda-
mental limitation to monolithic InSb device performance, but rather from the
particular combination of gate oxide deposition technique, reactor geometry,
and deposition parameters used so far in the fabrication of the CCIRIDs.
Various alternatives are being investigated including other means of depositing
SiO2 and Si3N4 at low substrate temperatures, which have been shown in SEM
investigations to produce films which are relatively patch-free when compared
to the horizontal-flow LTCVD SiO2. If the low N,, which has been demon-
strated can be maintained with simultaneous improvement in the gate oxide
morphology, the CTE of the InSb CCDs will approach 0. 9999.
5-9
LTCVD REACTOR DIFFERENCES
The InSb-LTCVD SiO2 interface has been the subject of considerable
study under an Independent Research and Development project, and the find-
ings have been recently published 4,lO . In this work, conductance measure-
ments did not detect any loss peaks due to interface states on properly pre-
pared devices such as that in Figure 5-2. The sensitivity of the measurements
was such that detectable loss in terms of equivalent parallel conductance would
have been sufficient to measure surface state densities in excess of 1 X 101’
eV - I.,-2 . The absence of detectable conductance loss peaks was also found
to correlate with the amount of hysteresis in the C-V curves, with devices
such as in Figure 5-2 displaying no hysteresis.
It has been determined in this work that the preservation of the thin,
native oxide on the InSb surface through a suitable LTCVD process is respon-
sible for the interface properties of devices such as shown in Figure 5-2.
The native oxide has been detected both before and after deposition of the
LTCVD SiO2 by Auger Electron Spectroscopy (AES) and X-ray Photoelectron
Spectroscopy (XPS). These investigations as well as ellipsometric measure-
ments show the native oxide to be only IOA to 151 thick before deposition of
the LTCVD SiO2. The composition of the oxide was determined as In203,
Sb205 and elemental Sb. After the SiO2 deposition, no Sb205 remains, having
presumably volatilized. Some elemental Sb remains, however.
Comparing the XPS spectra for the In 3d spin-orbit splitting obtained
for samples prepared with the two CVD reactor geometries -- horizontal and
vertical -- revealed important differences. The spectra were measured after
sputtering through the LTCVD Si02 layers, stopping at the point of detection
of In for each sample. The two spectra obtained showed a two-component
structure with a lower-energy component corresponding to the bulk In (prob-
ably from the uneven effect of ion sputtering and the thinness of the native
oxide) and a higher energy peak due to In203, at least in the case of the hori-
zontal reactor sample. The vertical reactor sample, however, clearly dis -
played a higher oxidation state rather than the In203 peak. Devices processed
5-10
in the vertical reactor show degraded surface state densities, similar in
their C-V and G-V characteristics to the data reported by other authors 11,12 .
Our hypothesis is that this is caused in the case of the vertical reactor by a
reduction of the thin native oxide by silicon resulting from heterogeneous
nucleation of the silane directly on the oxide, thereby disrupting the inter-
face. In the case of the horizontal reactor, as for the sample of Figure 5-2,
the silane dissociation reaction is predominantly homogeneous (with SiO2
particle nucleation size of 15OOi as discussed previously). Thus, the InSb
native oxide is protected from reduction by particle nucleation away from the
surface in this reactor.
DEVICE OPERATING TEMPERATURE
It was stated in Section 4 that the CCIRIDs from the lots evaluated to
date (4, 8B, and 1lB) showed best performance in the 60 K to 72 K tempera-
ture range, lower than the nominal operating temperature of 77 K. This
result is correlated with the storage times measured for these wafer lots,
which are shorter than what has been shown previously to be achievable in
InSb MOS samples at 77 Kl. The storage times in the present CCDs have
been shown to be limited by dark current from the bulk substrate, rather
than generation out of surface states. The higher bulk thermal generation
rate may correlate with defects which were discovered in much of the InSb
material supplied to us in 1978. These defects are microscopic in nature
and were only revealed by a special etchant. Comparative material evalua-
tions have been made possible by growth of InSb layers at SBRC by liquid
phase epitaxy (LPE). The LPE technique has been found to be capable of
producing very high quality InSb which is both free of these defects and which
displays long 77 K MOS storage times. The operating temperature require-
ments of the 20-element CCIRIDs processed and tested during this program,
therefore, are clearly associated with the characteristics of the starting
material. Since higher quality InSb has been shown to be possible, InSb CCD
arrays with significantly improved temperature characteristics should be
achieved in future efforts.
5-11
In this section, the relationship of clock frequency and integration time
to storage time will be discussed, along with some discussion of the InSb
material.
Relationship of CCD Clock Frequency and Storage Time
The storage time (TS) is related to the dark current density (JD) by the
useful approximation
Q (max) TS1 ’
JD (5-9)
where Q,(max) is the storage capacity of the well in coulombs/cm2. Since,
in general, the dark current is a function of surface potential JD (es), its
magnitude changes (usually decreasing) as the well fills with minority car-
riers. JD in equation (5-9) is therefore an average over the empty-well to
full-well time period.
The dark current at a given temperature establishes a minimum clock
frequency for the CCD which increases as the length of the CCD (i. e. , number
of transfers) increases. Consider a 40 CCD (Figure 5-8) which is transfer-
ring a signal charge Q, in the presence of a small FZ charge QFZ. The
charge Qs + QFZ is stored under each gate in the CCD for TC/4 seconds.
During this time dark current from an area ADK will add a dark charge Q,
coulombs to the well:
QD = JDTcADK/~ (5-10)
I a b C
Figure 5-8. - Dark Current in a 4@ CCD,
5-12
Because all the gates in each bit are not at the same surface potential, it is
not straightforward to calculate Q, exactly. Each gate in the bit contributes
its own dark current 1~ = J($,,Qp)A~ which depends on its surface potential
(i. e. , whether depleted or inverted), or equivalently the charge stored
beneath the gate. We account for this uncertainty by defining an area ADK, ,
which may range from a gate area AG to as large as the full bit area AB. If,
for example, surface generation dominates the dark current, then ADK 1 AB.
This is shown schematically in Figure 5-8; surface-generated dark current
QD under the “off” gates surrounding the “on” gate will collect in the storage
well. The charge from area a to b will accumulate in one well, from area b
to c in the next, etc. Similar to surface generation, if diffusion current from
the substrate is the dominant dark current source, the full bit area AB is the
effective dark current area ADK. In the lower limit, if generation out of bulk
states in the deep-depleted regions is the principal dark current source, then
ADK = AG since only one gate of a bit is in deep depletion at a given time.
In moving from CCD input to output, a signal charge will encounter NG
gates giving a total accumulated dark charge
QDT = NGJDTcADK/~ (5-11)
or
QDT = NBJDTCADK (5- 12)
since NG = 4NB. But the storage capacity of the CCD is Qp(max) AG; there-
fore the accumulated dark charge cannot exceed:
NBJDTCADK d Qp(max) AG (5- 13)
Substituting equation (5-9) in (5-13) and solving for TS gives
TS L (‘-‘JgTc) (ADK/AG) (5- 14)
Note that NB TC is the total transfer time of a signal charge from input to
output. Equation (5- 14) shows that the storage time must be greater than the
5-13
transfer time within the numerical factor ADK/AG which can range from 1
to 4. Writing (5-14) in terms of clock frequency
NB ADK f,L- -
TS AG (5- 15)
The limit established by equation (5- 15), for NB = 20 and ADK/AG = 4,
is plotted versus storage time as curve A in Figure 5-9 (left-hand and bottom
scales). Two other curves, B and C, for 32- and loo-bit CCDs are also
shown for reference. Reading from curve A, for example, if the storage
time is 1 msec, the accumulated dark charge will saturate the CCD at
f, = 80 kHz. The clock frequency must therefore be higher than the curve A
limit by some factor, say 10, to keep the dark charge a small fraction of the
CCD capacity.
The measured storage time for the 8585 Lot 8B witness devices was
approximately 20 msec at 77 K, Minimum f,, from curve A, is therefore
about 4 kHz at this temperature. Because the storage time varies exponen-
tially with inverse temperature, decreasing the temperature by a few degrees
will substantially increase Ts, and consequently lower the minimum. clock
frequency. The measured temperature dependence of TS is shown by the
top scale in Figure 5-9. At 70 K, TS has increased to about 100 msec, and
at 60 K to 0. 7 sec. At 60 K, the clock frequency for saturation has dropped
to 100 Hz.
The 20-element CCDs from Lot 8B were found to follow the predicted
behavior of Figure 5-9. The points (+) plotted in Figure 5-9 indicate temper-
ature-clock frequency combinations where 20-element devices from Lot 8B
were operated with electrical input (photogates off), and where dark charge
was maintained as a small fraction of capacity. These points lie on either
side of curve D, which is the clock frequency necessary to keep QDT at 5%
of charge capacity. In one test, points E in Figure 5-9, the device tempera-
ture was increased from 72 K, where dark charge was s lo%, to 80 K, with
5- 14
TEMPERATURE. 8585 LOT 8B. K
1-4 ?
.,sh \,c \ .+ /
r
/ /
+A,‘+ ’ ,A yA
;
\ +,,/ /-xc---
A INTEGRATION TIME
\
\
I / a 1
STORAGE TIME TS, seconds
Figure 5-9. - Clock Frequency and Integration Time versus Storage Time,
f, = 10 kHz. Saturation with dark charge was observed at 79 K, in good
agreement with the calculations of Figure 5-9.
Integration Time
The relationship of integration time to storage time is straightforward,
i. e. :
TINT s TS (5-16)
which is plotted as curve F in Figure 5-9 (right-hand and bottom scales).
Two other curves, G and H, are also plotted corresponding to 5% and 1%
dark charge levels. Triangular data points in the figure correspond to actual
temperature-integration time combinations where the 20-element CCIRIDs
5-15
were operated in the optical mode with low detector dark charge levels. They
are seen to lie between curves G and H as expected.
Comparison of Czochralski-Grown and LPE InSb
Zerbst analysis of the capacitance-time (C-t) responses of MOS samples
showing the decreased storage times revealed that they were due to excessive
bulk, rather than surface, thermal generation. A change in the quality of the
InSb wafers from the Czochralski (CZ) ingots was therefore suspected, al-
though etch pit density, mobility, and other specified parameters of the wafers
were meeting specifications. Concurrently, on another program epitaxial
InSb layers were being grown by LPE on the CZ wafers which, when impurity
concentration and layer morphology were acceptable, provided relevant com-
parative data. Significant differences in both MOS storage time and leakage
currents of implanted Be p-n junctions were observed when fabricated on the
LPE InSb layers versus the CZ InSb wafers in hand at that time, both charac-
teristics being superior for the LPE layers.
These% electrical differences may correlate with defects observed in the
CZ InSb wafers but that were totally absent in the LPE InSb layers. A prefer-
ential etchant that reveals defects on the cl1 l>B face of the CZ wafers or epi
layers has been developed. A comparison of the results of defect etching a
CZ InSb wafer of suspected quality and an epitaxial layer is shown in Fig-
ures 5- 10 through 5- 12. Figures 5- 10 and 5- 11 show the <I 1 l>B face of the
CZ InSb wafer after the defect etch, at 2X and 40X magnification, respec-
tively. A large density of etch pits, up to several hundred per square centi-
meter, is observed. Before performing the defect etch, 20 pm of material
was removed from the surface of the CZ InSb wafer with a polish etch to
ensure that the pits were not a surface phenomenon, i. e. , due to residual
polishing damage, the encapsulating material used in shipment, and so forth.
The pits revealed by the defect etch do not seem to correlate with dislocations,
as when a first set of etch figures is removed with a polish etch and a new set
produced with another cycle of defect etching, and second set does not reli-
cate the first. Instead, the predominant sources of the etch figures in the
5-16
Figure 5- 10. - Etch Pits on <11 l>B Face of CZ InSb Wafer after Etching to Reveal Defects (2X).
Figure 5- 11. - Etch Pits on CZ InSb Wafer at Higher Magnification (40X).
5-17
, ._ ----_- ..- .-..- ..--.... _- ._.-. .._ .- ..- --
Figure 5-12.- cl1 l>B Face of LPE InSb Layer after Defect Etching (Phase Contrast Photomicrograph) (40X) l
CZ material are thought to be chemical complexes, probably oxides, ran-
domly included throughout the crystal. The low storage time of the MOS
capacitors on the CZ InSb suggests that these complexes may be electrically
active. The density of these defects varies from ingot to ingot, and Fig-
ures 5-10 and 5-11 probably represent a worst case. Pits revealed by the
defect etch also can be due to other sources such as mechanical damage.
For example, the lines of pits near the edge of the wafer visible in Fig-
ure 5- 10 are from handling work damage which occurred when it underwent
the etch process.
Performing the same defect etch on wafers received recently indicates
that CZ ingots can be grown considerably more defect-free than that illus-
trated in Figure 5-10. A CZ wafer from a second InSb source, subjected to
the same defect etch, had fewer pits compared to Figures 5-10 and 5-11 but
was not free of the defects. A new Czochralski puller set up by the first
5-18
InSb supplier has recently produced material with significantly lower defect
count than that illustrated in Figures 5- 10 and 5- 11.
After etching the LPE InSb layer in the B-face defect etch, no pits or
etch figures were developed over the majority of the wafer area, indicating
the total absence of the defects or complexes that were found in the CZ InSb.
Figure 5- 12 shows the Cl 1 l>B face of the LPE InSb layer after defect etching.
The magnification in the photomicrograph of Figure 5- 12 is the same as that
of Figure 5- 11, and phase contrast was used to enhance the surface mor-
phology.
MOS samples fabricated on low impurity concentration LPE InSb layers
showed long storage times characteristic of good substrate material. Fig-
ure 5-13 shows a C-t characteristic for a capacitor processed on the higher
quality material, following application of a voltage step. The 77 K storage
time is seen to be about 1. 5 seconds. With improved material leading to
storage times of this order, a broader range in clock frequency and integra-
tion time will result. This is shown in Figure 5-9 by a second temperature
scale for the improved material at the top right-hand of the figure. At 77 K,
the 20-element CCIRID will not be dark current saturated until the clock
frequency is reduced to 50 Hz, a clock rate orders of magnitude lower than
most anticipated systems require.
Figure 5-13. - MOS Storage Time at 77 K for LPE InSb Layer.
5- 19
IMPROVEMENTS IN PHOTOGATE YIELD
One fabrication process change required for increased yields is to
reduce the number of photogate-to-substrate shorts which were observed in
the 8585 linear imagers processed in this program. Since all the photogate
elements of an imager are in parallel, one short in the array renders it in-
operable. Examination of completed arrays utilizing scanning electron
microscopy showed that these shorts occurred in the contact windows to the
photogates, not in the optically-active areas themselves. In the process
sequence that was used::, the photogates were very thin (0. 0075 pm) evapor-
ated titanium, on the same level as (but not electrically connected to) the
buried metal gates (see Figure 2-5). Both the photogates and buried metal
were subsequently insulated with a 2000A thick SiO2 buried metal insulator.
Contact windows were then etched through the buried metal insulator to the
photogates to allow the next metal layer (surface metal) to contact them.
During this contact window etching process, pinholes were exposed allowing
etching of the underlying SiO2 layers to the InSb substrate surface, causing
the shorts.
The photomicrographs in Figure 5- 14 show these pinholes which were
exposed and the photogate-to-substrate shorts created. The mechanism by
which this pinholing occurred is not clearly understood, since the surface of
the oxide under the photogates is identical to the oxide under the contact.
Pinholes in the gate oxide, if they exist, should be visible throughout the
channel region, and they were not detected there. Having identified the origin
of the shorts, a change in process sequence will alleviate the photogate con-
tact window pinholes in future 8585 wafer lots. Also, the process and mask
design for the next-generation InSb CCIRID chip will be such as to preclude
this problem entirely by having the photogates and their bias bus bar on the
same metal level, thus eliminating the contact cut step.
WBRC is working on development of an antireflective, conductive gate struc- ture on IR&D for future use as optimized photogates with improved trans- mittance characteristics.
5-20
-
TRANSPARENT GATE AND CONTACT WiNDOW
PINHOLES IN CONTACT WINDOW
Figure 5- 14. - 8585 InSb CCIRID Transparent Gate Structure.
5-21
I
Section 6
APPLICATIONS FOR MONOLITHIC InSb CCD ARRAYS
This section describes part of a continuing survey of future instruments
and sensor systems in which potential applications exist for the monolithic
InSb CCIRID technology that is being developed. Space applications for mono-
lithic InSb arrays fall into several areas where the construction of the device
offers operational and reliability advantages over more conventional discrete
or hybrid array technologies. Described in more detail in the following are
three of these areas: earth resources applications; meteorological satellite
applications; and geological applications.
EARTH RESOURCES APPLICATIONS
The Earth Observatory Satellite (EOS) Mission involves remote sensing
from space and transmitting, processing, and delivering earth observational
data by the most cost-effective methods to the user community concerned with
earth resources management. The user community is represented by: NASA -
sponsored principal investigators and their associates; other U. S. federal,
state, and local government agencies; foreign government agencies (some of
whom have their own earth stations); universities; and private industry around
the world. Satisfying this diverse user community is a task that NASA has
undertaken and accomplished since the first LANDSAT spacecraft with a four-
band multispectral scanner (MSS) and a three-band return beam vidicon was
launched in 1972. The launch in January 1975 of the I.ANDSAT-2 spacecraft
with its multispectral scanners provided a system that currently generates
updated earth resources data in a geographical area every nine days.
The experience with the two in-orbit multispectral scanners has been
the basis for evolving the requirements for the Thematic Mapper (TM), the
primary instrument for the EOS or advanced LANDSAT System which is
currently being built by the Hughes Aircraft Company. The TM will be
6-1
installed in the multi-mission modular spacecraft and launched by the Delta
B9 10 or space shuttle in late 1981.
The specified ground resolution of the TM is 30 meters for the reflective
infrared and visible bands, as opposed to 80 meters for the currently in-orbit
multispectral scanners; however, improved ground resolution to 15 meters is
currently being studied in connection with an upgraded TM to be flown on
LANDSAT D’ in 1983.
The current TM employs among others two arrays each containing 16
staggered InSb elements, one covering the 1. 55- to 1. 75-pm band and the
other in the 2. 08- to 2. 35-pm band. These bands are used for agriculture
and geological resource monitoring, respectively. A scan mirror is used to
scan these arrays across the ground track such that a swath 185 km wide is
generated. The scan rate used to ensure contiguity of consecutive swaths
produces a dwell time of less than 10 psec, a value much too short to use
photoconductive PbS which would otherwise be suitable for these spectral
ranges. The 32 InSb elements together with their preamplifier input stages
used in the TM are cooled to a temperature of about 80 K by a passive radia-
tive cooler.
Improvements to the present TM design may include replacement of the
two conventional or discrete element InSb arrays with two monolithic InSb
time-delay-and-integration (TDI) CCIRID arrays (32 cross scan, 16 TDI)
which will give double the present resolution (15 meters) and approximately
the same signal-to-noise ratio. To maintain contiguity of the fields of view
in the TDI direction, the detector/TDI CCD rows would be staggered. This
can be accommodated by the use of a fiber optic relay between the focal plane
and CCD array chip, allowing full utilization of the TM focal plane as pres-
ently configured.
6-2
METEOROLOGICAL SATELLITE APPLICATIONS
Meteorological observations from space include infrared and visible
imaging primarily to observe cloud motion, night or day. Thermal measure-
ments of cloud tops to obtain temperatures allow the determination of wind
velocity as a function of altitude if the lapse rate is assumed.
Temperature sounding is a method by means of which the temperature
profile in the atmosphere can be determined remotely. To do this, we must
observe the radiation emitted by an atmospheric constituent whose vertical
distribution (concentration) and radiating properties are known so that the
transmittance (7) and the slope of transmittance with pressure (dT/dP) are
calculable. This requires that the radiation emanate from a gas which has a
known, stable concentration and that this radiation be separable from all
other sources, gaseous or aerosol. The gases usable for temperature pro-
filing are CO2 in the 2325 cm-l (4. 3-pm) or the 668 cm-l (15-pm) band and
O2 in the 60-GHz microwave band. CO2 is assumed to be essentially uni-
formly distributed throughout the atmosphere. The technique is to observe
radiation emitted within several spectral regions in the CO2 absorption bands -
each of which has a different transmittance. The effect of this is to cause the
observed radiances to originate from a different altitude. Extraction of atmo-
spheric temperatures from radiances is not an exact process since the radi-
ances are not independent. The procedure is to use a first “guess” for the
temperature profile based on the latest forecast or from climatology. Then
by using regression analysis of the differences between the first guess and the
observed radiances a better answer can be obtained.
Temperature Sounding from Synchronous orbit is currently being planned
by NASA using a modified version of the Visible Infrared Spin-Scan Radiometer
(VISSR) built by SBRC. The sensor, known as the VISSR Atmospheric Sounder
(VAS) uses several channels in each of the 4. 3-urn and 15-pm CO2 bands.
Sounding performance is limited, however, by the scan efficiency which is low
owing to the fact that the earth is viewed for about 5% of the spin period at
6-3
synchronous orbit. This necessitates dwell spinning for many revolutions to
build up the signal-to-noise level.
Future improvements to this design include upgrading of the focal plane
through the use of monolithic InSb and HgCdTe TDI CCD arrays for the 4. 3-p.m
and 15-urn bands, respectively. Arrays of up to 40 elements in each band can
be accommodated which will give a signal-to-noise improvement of about six
over the present VAS.
Future sounder developments also include consideration of line-of-
sight stabilized sensors from synchronous orbit. The increased scan effi-
ciency of this type of sensor as compared with the spin-stabilized VAS will
give improved performance. Use of CCD area arrays in this application will
simplify the scan, and improve performance further. Spatial registration of
fields of view in the various spectral regions is important to sounding (regis-
tration to within 1% of footprint area is a commonly used requirement). This
becomes possible with a monolithic array in which the position of elements is
controlled with photoetch masks.
GEOLOGICAL APPLICATIONS
A current development at the Jet Propulsion Laboratory (JPL) is the
Shuttle Multispectral Infrared Reflectance Radiometer (SMIRR). The first
experiment will measure from an aircraft the solar reflectance spectra of
surface minerals between 0, 6 pm and 2. 25 pm. The second experiment,
known as “Son of SMIRR, ” will be flown from the Space Shuttle. It will use
a two-dimensional array of upwards of 1000 elements. The monolithic InSb
CCD array technology would work well in this application. Cooling will be
provided by either a liquid cryogen or a cryogenic refrigerator.
6-4
Section 7
SUMMARY
Monolithic infrared CCD linear imaging arrays were successfully fab-
ricated in InSb, and IR detection and readout with the arrays demonstrated,
in this contract. Twenty MOS detector elements were integrated on the same
chip with a 4@, surface-channel InSb CCD to produce a charge-coupled
infrared imaging device (CCIRID). The development of this technology
allows several signal processing functions to be accomplished on the detector
array chip instead of off-focal-plane as in current systems. The InSb CCDs
can be used for on-chip multiplexing of the detector outputs, or to provide
time-delay-and-integration (TDI) for signal/noise enhancement in scanning
sys terns.
The CCD process developed for InSb includes a capability for p-n
junctions , which are used in the present device for fat zero (FZ) input and
charge output; InSb MOSFETs have also been fabricated. The availability of
these components will allow critical output circuit elements to be incorporated
on-chip in the next InSb CCIRID design along with the possibility of detector ac
coupling, background subtraction, and antiblooming circuits in future arrays.
The fabrication process is suitable for large area arrays, and design and
fabrication of an area array should be undertaken as one of the next tasks in
this development.
The CTE of the InSb CCDs fabricated during this program was measured
to be 0. 995. The 20-element CCIRIDs evaluated were produced in two 8585
wafer fabrication lots (Nos. 8B and 11 B), in which the LTCVD Si02 gate
oxide was deposited by means of a horizontal-flow configuration CVD reactor.
True surface state density of InSb MOS devices produced in this reactor has
been shown to be very low (-10” cmm2-eV-l), and CTE should be correspond-
ingly high, 0. 9995 or better. The CTE of this device group was found, in fact,
to be not limited by surface states but rather by lateral nonuniformity in
7-l
surface potential arising from the microscopic granularity of the LTCVD
S102 oxide layer. This limitation is not fundamental to InSb CCDs or CCDs
in general, and alternate Si02 deposition techniques are being pursued in an
SBRC Independent Research and Development program to greatly reduce or
entirely eliminate the oxide granularity, while preserving the low N,, values
that we have successfully demonstrated on InSb.
In addition to low surface state density, other characteristics of the
LTCVD SiO2-InSb MOS system are very favorable for CCD arrays, such as
the near-zero flatband voltage. Fixed charge density in the gate oxide is
approximately lo1 ’ (positive) charges/cm 2 or less, comparable to typical
silicon CCD devices. This results in low drive voltage requirements, as
well as compatibility with p-n junctions on chip; i. e. , the lightly-doped side
of the junctions are neither strongly accumulated nor inverted by a large
oxide fixed charge.
Charge integration in the photogates, transfer into the register, and
serial readout of the 20 detector signals was demonstrated for the InSb linear
CCIRIDs. Because of its inherent flexibility, application of the InSb CCIRID
concept in future IR sensors will offer many advantages. The CCD clock
frequency, and thus the array readout rate, is variable over a wide range to
suit system needs. In the first device tests reported here, the 20-element
CCIRID clock frequency ranged from 1 to 200 kHz. With storage time im-
provements gained through improved InSb material quality (which has been
demonstrated), the 20-element CCIRID will have a 77 K operational clock
frequency range from a few hundred Hertz to over 1 MHz. Since the CCD
registers are 4@, they can also be clocked in reverse allowing the design of
bidirectional scanning arrays. The separation of detection and multiplexing
functions in the InSb CCIRID allows the integration time to be varied inde-
pendently of readout rate from TINT = f,- ‘, the TDI mode, to TINT >> Nf, -1 ,
where the N detectors in the array are read out during a small fraction of the
integration time. Both operational modes were demonstrated during this
program. Integration times of several hundred milliseconds at 77 K are
7-2
feasible for low background photon flux levels. If applications require it,
even longer integration times can be obtained with lower operating tempera-
tures. Storage times have been measured as a function of temperature and
increase to P102 set at 50 K and >103 set for lower temperatures.
The output voltage magnitude (and therefore responsivity) of the present
devices is reduced by the interim use of discrete silicon MOSFETs in the out-
put circuit rather than on-chip transistors. The sum of output diode, MOSFET
input, bonding pad, and stray capacitances on the output node is about 6 pf,
which results in a full-well output voltage of 60 mv. Nearly an order of mag-
nitude improvement will be obtained with critical elements in the output circuit
integrated monolithically on the InSb chip. The potential for on-chip transistors
has been established by separately fabricating InSb MOSFETs, utilizing the Be-
implant procedure to produce planar source and drain and LTCVD Si02 for the
gate oxide. The InSb FETs are p-channel enhancement-mode devices and show
promise for several on-chip applications.
The D+ was measured for one 20-element InSb CCIRID operating in the
multiplexing mode and was greater than 10 I1 cm-Hz;-watt- 1 at low background
and for the particular clock and integration time conditions of the test. With
improvements in both the transparent photogate process (increasing the present
transmittance from - 30% to > 70%) and the output circuit, array D::: > 10 12
cm-Hz;-watt-l is predicted for backgrounds less than lOI ph/sec-cm2. This
is the single-element D+ and a further fi improvement should be obtained with
TDI.
Two ZO-element InSb CCIRIDs fabricated in the program were delivered
to NASA Langley Research Center for further evaluation, device Nos.
498- 17-A3 and 498- 17-F4.
7-3
REFERENCES
1. R. D. Thorn, R. E. Eck, J. D. Phillips, and J. B. Scorso, “InSb CCDs and Other MIS Devices for Infrared Applications, ‘I Proc. of the 1975 Intl. Conf. on the Applications of CCDs, San Diego, CA, 29-31 Oct. 1975.
2. J. D. Phillips, J. B. Scorso, and R. D. Thorn, “InSb Arrays with CCD Readout for 1. 0- to 5. 5-pm IR Applications, I’ Proc. of the 1976 NASA- JPL Symposium on CCD Technology and Applications, October 1976.
3. W. W. Anderson, Infrared Physics 17, 147 (1977).
4. J. D. Langan, C. R. Viswanathan, C. A. Merilainen, and J. F. Santarosa, “Characterization of Improved InSb Interfaces, ” IEEE Intl. Electron Devices Meeting Technical Digest, Washington D. C. , December 1978.
5. R. D. Thorn, W. H. Konkel, and R. M. Hoendervoogt, “Planar P-N Junctions in InSb by Be Ion Implantation,” IEEE Device Research Con- ference, Ithaca, New York, 27 June 1977.
6. G. F. Vanstone, J. B. G. Roberts, and A. E. Long, Solid State Electronics 17, 889 (1974).
7. R. Castagne and V. Vapaille, “Description of the SiO2-Si Interface Properties by Means of Very Low Frequency MOS Capacitance Measure- merits, ” Surf. Sci. 3, 157 (1971).
8. C. C. Chang, PhD Dissertation, Princeton University, February 1976.
9. A. Shintani, K. Suda, M, Suzuki, and K. Takami, “SiO2 Particulates Dispersed in CVD Reactor,” J. Electrochem. Sot. 124, 1771 (1977).
10. J. D. Langan, C. R. Viswanathan, R. D. Thorn, C. A. Merilainen, and R. E. Kvaas, “Characterization of Improved InSb Interfaces, ” Sixth Annual Conference on the Physics of Compound Semiconductor Inter- faces, 30 January - 1 February 1979, Asilomar Conf. Grounds, Pacific Grove, CA.
11. J. C. Kim, “InSb MIS Structures for Infrared Imaging Devices,” Inter- national Electron Devices Meeting, Washington D. C. , December 1973.
12. Gordon Wood Anderson, William A. Schmidt, and James Comas, “Com- position, Chemical Bonding, and Contamination of Low Temperature SiOxNy Insulating Films, ” J. Electrochem. Sot. , Vol. 125, p. 424; March 1978.
R-l
.‘---. J ---
1. Report No. 2. Government Accession No.
NASA CR-3235 4. Title and Subtitle
InSb Charge Coupled Infrared Imaging Device-20-Element Linear Imager
7. Author(s) 8. Performing Organization Report No.
R. D. Thorn, T. L. Koch, W. J. Parrish, J. D. Langan, and S. C. Chase
10. Work Unit No. J I
9. Performing Organization Name and Address
Santa Barbara Research Center 75 Coromar Drive Goleta, CA 93017
12. Sponsoring Agency Name and Address
National Aeronautics and Space Administration Washington, DC 20546
3. Recipient’s Catalog No.
5. Report Date
February 1980 6. Performing Organization Code
11. Contract or Grant No.
NASl-14922 - 13. Type of Report and Period Covered
Contractor Report 14. Army Project No.
15. Supplementary Notes
Langley Technical Monitor: William E. Miller Final Report
16. Abstract This report describes the design and fabrication of the 8585 InSb Charge
Coupled Infrared Imaaing Device (CCIRID) chip, on which a 20-element linear imager is the principal devjce, and the electrical and optical characteristics of the experimental devices that were determined under this contract. The report is organ- ized as follows: device design and fabrication, including discussion of the InSb material characteristics; the design and description of the 8585 chip; the fabrication process; and mask and process modifications that were implemented in the program. Test results for the two-element InSb CCIRID on the 8585 chip are discussed, which was the first device produced. Included are: evaluation of the gate oxide character- istics; development of the surface potential diagram; discussion of the CCIRID channel stopping approach; and operation of the two-element device. A similar discussion of the test results for the 20-element CCIRID, including gate oxide characteristics, test equipment configuration , measurement of charge transfer efficiency, and optical mode operation is presented. A discussion of test results examines some of the factors that have been identified which influence the current performance of these arrays is presented, along with means of improvement.
7. Key Words (Suggested by Author(s) J 1 18. Distribution Statement
Infrared Imagers; Imaging Arrays; Monolithic Imagers; Charge Coupled Devices; Unclassified - Unlimited InSb; Linear Imagers; Charge Transfer; Optical Sensitivity; Array Design; Subject Category 35 Array Fabrication
19. Security Classif. (of this report1 20. Security Classif. (of this pagel 21. No. of Pages 22. Price’
Unclassified Unclassified 143 $7.25
‘For sale by the National Technical Information Service, Springfield, Virginia 22161 NASA-Langley, 1981