instruction-level parallelism for low-power embedded processors january 23, 2001 presented by anup...

Instruction-Level Parallelism for Low-Power Embedded

Processors

January 23, 2001Presented By

Anup Gangwar

Embedded Systems Group IIT Delhi

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Introduction

Need for high performance low power processors

Synergistic hardware -compiler design for EPIC or VLIW like architectures

A new variable instruction length scheme

Full predication support in hardware


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Outline

Instruction-Level Parallelism Power Consumption in VLSI Circuits A Look at Available Mobile and DSP Processors High-Level Evaluation of A Low-Power VLIW

Processor The DEVIL Low-Power Processor A Step Towards Predicated Execution Conclusion


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ILP : Concepts and Limitations

Data DependencesFlow Dependence or RAWAnti Dependence or WAROutput Dependence or WAW

Reduction of critical pathControl DependencesResource Conflicts


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Achieving ILP : Pipelining

Control dependencies affect pipelined execution

Data dependencies affect pipelined execution

Resource conflicts affect pipelined execution


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Achieving ILP: Superscalar Architectures

In-order issue with in-order completion

In-order issue with out-of-order completion

Out-of-order issue with out-of-order completion


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Achieving ILP: VLIW Processors

Low circuit overhead than Superscalar Processors

Limited number of resourcesExplicit insertion of NOPs increases

code size


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Extracting ILP : BasicBlock Scheduling


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Extracting ILP: Superblock Scheduling


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Extracting ILP: Predicated Execution


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Power Consumption in CMOS Circuits : Parallelism for Energy Efficiency


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Available Mobile and VLIW Processors

The ARM FamilyThe ARM7 GenerationThe StrongARMThe ARM Thumb OptionThe ARM Piccolo OptionThe ARM9 and ARM10


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Available Mobile and VLIW Processors

The Motorola M-CoreThe LSI TinyRiscThe Hitachi SuperH FamilyVLIW Processors

The Motorola-Lucent Star*CoreThe Philips TriMediaThe HP/Intel IA-64


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High Level Evaluation of A Low-Power VLIW Processor

Energy consumption distribution


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High Level Evaluation of A Low-Power VLIW ProcessorNOP Elimination in VLIW Processor


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High Level Evaluation of A Low-Power VLIW ProcessorSpeed-up Comparison


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High Level Evaluation of A Low-Power VLIW Processor

Energy Comparison


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High Level Evaluation of A Low-Power VLIW ProcessorEnergy-Delay Product Comparison


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The DEVIL Low-Power Processor

Complexity in VLIW ArchitecturesHardware Duplication

FUs and number of registers as well as ports

Number of FUs versus type of FU

Number of FUs versus available ILP


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The DEVIL Low-Power ProcessorCode Memory


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The DEVIL Low-Power Processor


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The DEVIL Low-Power ProcessorInstruction Fetch Mechanism


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The DEVIL Low-Power ProcessorBranch Prediction Mechanism


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The DEVIL Low-Power Processor Performance with and without superscalar optimizations


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The DEVIL Low-Power Processor Effect of SuperScalar optimization on code size


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The DEVIL Low-Power ProcessorEffect of NOP elimination on code size


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The DEVIL Low-Power Processor Effect of NOP elimination on the number of

accesses to code memory


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The DEVIL Low-Power Processor Effect of instruction fetch mechanism on code size


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The DEVIL Low-Power Processor Code size comparison with existing mobile processors


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A Step Towards Predicated Execution

Compiler techniques for reducing predicate code sizeReduction of number of Control InstructionsPredicate promotion and Instruction merging Instruction reduction for advanced code

generation


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A Step Towards Predicated Execution:Reduction of number of Control Instructions


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A Step Towards Predicated Execution: Predicate promotion and Instruction merging


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Introducing predication support into processorEffect on code size of full predicationPredication code size and Execution

CharactersticsPrefix based predication


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A Step Towards Predicated ExecutionRelative number of predicated instructions


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Code expansion considering predication


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A Step Towards Predicated Execution Code reductions due to predicated execution


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Conclusions

A synergistic hardware-compiler approach for low-power processors

A new VLIW architecture to reduce increase in code size

A prefix based predicated execution architecture framework

instruction-level parallelism for low-power embedded processors january 23, 2001 presented by anup...

Documents

lowpower vliw processorspeed

high level evaluation

extracting ilp

order completioninorder

order completionout

available ilpemb

rawanti dependence

waroutput dependence