CMPT 250 Computer Architecture

Instructor: Yuzhuang Huyhu1@cs.sfu.ca

Final Exam!

The final exam is scheduled on

7th, August, Friday

7:00 pm – 10:00 pm

The Reduced Instruction Set Computer (RISC)The goal of a RISC architecture is high

throughput and fast execution. To achieve these goals, accesses to memory are to be avoided.

A RISC architecture has the following properties: Memory accesses are restricted to load and store

instructions, and data-manipulation instructions are register-to-register.

Addressing modes are limited in number. Instruction formats are all of the same length. Instructions perform elementary operations.

Datapath OrganizationThe new datapath has 32 32-bit registers. The address inputs

are therefore five bits.

The replacement of the single-bit position shifter with a barrel shifter to permit multiple-position (SH) shifting.

In the function unit, the ALU is expanded to 32 bits.

The constant unit performs zero fill for CS=0 and sign extension for CS=1.

MUX A is added to provide a path from the updated PC, PC-1, for implementation of the JML instruction.

Datapath Organization contd.Adding an additional input to MUX D to implement the

Set if Less Than (SLT) instruction. It is 1 when N is 1 and V is 0, or N is 0 and V is 1.

A final difference is that the register file is no longer edge triggered and is no longer a part of a pipeline platform at the end of the write-back (WB) stage.

In the second half of the cycle, it is possible to read data written into the register file during the first half of the same clock cycle. It is called a read-after-write register file.

Control OrganizationSH is added to IR, CS is added to the instruction

decoder, MD is expanded to two bits.

MUX C selects from three different sources for the next value of PC.

BrA is formed from the sum of the updated PC value for the branch instruction and the target offset.

BAA is used for the register jump.

BS, PS and Z are used to select the next PC value.

Definition of Control Fields BS and FS

Register Transfer BS Code

PS Code

Comments

PC<-PC+1 00 X Increment PC

Z:PC<-BrA, Z:PC<-PC+1

01 0 Branch on Zero

Z:PC<-BrA, Z:PC<-PC+1

01 1 Branch on Nonzero

PC<-R[AA] 10 X Jump to Contents of R[AA]

PC<-BrA 11 X Unconditional Branch

Data HazardsUnfortunately, there are other problems with

pipeline operation that reduce throughput.

Data Hazards

Control Hazards

Data hazardsConsider the following instructions

1. MOV R1, R5

2. ADD R2, R1, R6

3. ADD R3, R1, R2

IF DOF EX WB

IF DOF EX WB

IF DOF EX WB

1 2 3 4 5

Mov R1, R5Add R2, R1, R6Add R3, R1, R2

A Program Based SolutionAdd NOPs to the program.

IF DOF EX WB

IF DOF EX WB

IF DOF EX WB

IF DOF EX WB

IF DOF EX WB

Mov R1, R5

Add R2, R1, R6

Add R3, R1, R2

NOP

NOP

1 2 3 4 5 6 7 8

Data Hazard StallInsert bubbles to the pipeline.

IF DOF EX WB

IF DOF

IF DOF EX WB

IF DOF

IF DOF EX WB

Mov R1, R5

Add R2, R1, R6

Add R3, R1, R2

(Add R2, R1, R6)

1 2 3 4 5 6 7 8

(Add R3, R1, R2)

Data hazards detected,pipeline stalled,bubble launched

Data Forwarding

No extra delay.

IF DOF EX WB

IF DOF EX WB

IF DOF EX WB

Mov R1, R5Add R2, R1, R6Add R3, R1, R2

Control Hazards 1 BZ R1, 18

2 MOV R2, R33 MOV R1, R24 MOV R4, R220 MOV R5, R6

IF DOF EX WB

IF DOF EX WB

IF DOF EX WB

BZ R1, 18

MOV R2, R3

MOV R1, R2IF DOF EX WBMOV R5, R6

Change in R2 Change in

R1

PC set to 20

A Program Based Solution

1 BZ R1, 182 MOV R2, R33 MOV R1, R24 MOV R4, R220 MOV R5, R6

IF DOF EX WB

IF DOF EX WB

IF DOF EX WB

BZ R1, 18

NOP

NOPIF DOF EX WBMOV R5, R6

No change

No change

PC set to 20

Branch Prediction

1 BZ R1, 182 MOV R2, R33 MOV R1, R24 MOV R4, R220 MOV R5, R6

IF DOF EX WB

IF DOF

IF

BZ R1, 18

NOP

NOPIF DOF EX WBMOV R5, R6

No change

No change

PC set to 20

Branch detected and bubbles launched

CISC ArchitectureThe goal of the CISC architecture is to match more

closely the operations used in programming language and to provide instructions that facilitate compact programs and conserve memory.

A purely CISC architecture has the following properties: Memory access is directly available to most types of

instructions. Addressing modes are substantial in number. Instruction formats are of different lengths. Instructions perform both elementary and complex

operations.

THANKS!