integrated dual rf receivers data sheet adrv9008-1 · integrated dual rf receivers data sheet...

Integrated Dual RF Receivers Data Sheet ADRV9008-1

Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com

FEATURES Dual receivers Maximum receiver bandwidth: 200 MHz Fully integrated, fractional-N, RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz

APPLICATIONS 3G/4G/5G FDD, macrocell base stations Wideband active antenna systems Massive multiple input, multiple output (MIMO) Phased array radar Electronic warfare Military communications Portable test equipment

GENERAL DESCRIPTION The ADRV9008-1 is a highly integrated, dual radio frequency (RF), agile receiver offering integrated synthesizers and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 3G/4G/5G macrocell, frequency division duplex (FDD), base station applications.

The receive path consists of two independent, wide bandwidth, direct conversion receivers with state-of-the-art dynamic range. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. RF front-end control and several auxiliary functions, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) for the power amplifier (PA), are also integrated.

In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing dynamic gain control.

The received signals are digitized with a set of four, high dynamic range, continuous time, sigma-delta (Σ-Δ) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture (which does not suffer from out of band image mixing) and the lack of aliasing reduces the requirements of the RF filters compared to the requirements of traditional intermediate frequency (IF) receivers.

The fully integrated phase-locked loop (PLL) provides high performance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and serial interface. A multichip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. The ADRV9008-1 features the isolation that high performance base station applications require. All voltage controlled oscillators (VCOs) and loop filter components are integrated.

The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.

The core of the ADRV9008-1 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption during normal use. The ADRV9008-1 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).

https://form.analog.com/Form_Pages/feedback/documentfeedback.aspx?doc=ADRV9008-1.pdf&product=ADRV9008-1&rev=0

http://www.analog.com/en/content/technical_support_page/fca.html

http://www.analog.com/


http://www.analog.com/ADRV9008-1?doc=ADRV9008-1.pdf

ADRV9008-1 Data Sheet

Rev. 0 | of 68

TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications ..................................................................................... 4

Current and Power Consumption Specifications ..................... 8 Timing Diagrams .......................................................................... 9

Absolute Maximum Ratings .......................................................... 10 Reflow Profile .............................................................................. 10 Thermal Management ............................................................... 10 Thermal Resistance .................................................................... 10 ESD Caution ................................................................................ 10

Pin Configuration and Function Descriptions ........................... 11 Typical Performance Characteristics ........................................... 17

75 MHz to 525 MHz Band ........................................................ 17 650 MHz to 3000 MHz Band .................................................... 25 3400 MHz to 4800 MHz Band .................................................. 33 5100 MHz to 5900 MHz Band .................................................. 40 Receiver Input Impedance......................................................... 45

Terminology .................................................................................... 46

Theory of Operation ...................................................................... 47 Receivers ...................................................................................... 47 Clock Input .................................................................................. 47 Synthesizers ................................................................................. 47 SPI ................................................................................................. 47 JTAG Boundary Scan ................................................................. 47 Power Supply Sequence ............................................................. 47 GPIO_x Pins ............................................................................... 48 Auxiliary Converters .................................................................. 48 JESD204B Data Interface .......................................................... 48

Applications Information .............................................................. 49 PCB Layout and Power Supply Recommendations ............... 49 PCB Material and Stackup Selection ....................................... 49 Fanout and Trace Space Guidelines ......................................... 51 Component Placement and Routing Guidelines ................... 52 RF and JESD204B Transmission Line Layout ........................ 58 Isolation Techniques Used on the ADRV9008-1W/PCBZ ... 60 RF Port Interface Information .................................................. 61

Outline Dimensions ....................................................................... 68 Ordering Guide .......................................................................... 68

REVISION HISTORY 9/2018—Revision 0: Initial Version


Data Sheet ADRV9008-1

Rev. 0 | of 68

FUNCTIONAL BLOCK DIAGRAM

RF_EXT_LO_I/O+

RX2_IN+

RX2_IN–

RX1_IN+

RX1_IN–Rx1

Rx2

LPF

LPF

CLOCKGENERATION

SERDOUT0±SERDOUT1±SERDOUT2±SERDOUT3±SYSREF_IN±GP_INTERRUPTRX1_ENABLERX2_ENABLE

TESTSCLK

SDOSDIO

REF_CLK_IN +REF_CLK_IN –

DIGITALPROCESSING

DECIMATIONpFIRAGC

DC OFFSETQEC

JESD204BCIF/RIF

RF_EXT_LO_I/O–

GPIOs, AUXILIARY ADCs,AND AUXILIARY DACs

GPIO_3p3_x GPIO_x AUXADC_x

ADRV9008-1

CS

RESET

SYNCIN0±SYNCIN1±

ADC

ADC

1683

0-00

1

ArmCortex-M3

RF LOSYNTHESIZER

Figure 1.



Rev. 0 | of 68

SPECIFICATIONS Electrical characteristics at VDDA1P31 = 1.3 V, VDDD1P3_DIG = 1.3 V, TJ = full operating temperature range, and LO frequency (fLO) = 1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer to the Typical Performance Characteristics section for input/output circuit path loss. The device configuration profile for the 75 MHz to 525 MHz frequency range is as follows: receiver = 50 MHz bandwidth (inphase quadrature (I/Q) rate = 61.44 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz. Unless otherwise specified, the device configuration for all other frequency ranges is as follows: receiver = 200 MHz bandwidth (I/Q rate = 245.76 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.

Table 1. Parameter Symbol Min Typ Max Unit Test Conditions/Comments RECEIVERS

Center Frequency 75 6000 MHz Gain Range 30 dB Analog Gain Step 0.5 dB Attenuator steps from 0 dB to 6 dB 1 dB Attenuator steps from 6 dB to 30 dB Bandwidth Ripple ±0.5 dB 200 MHz bandwidth, compensated by

programmable finite impulse response (FIR) filter

±0.2 dB Any 20 MHz bandwidth span, compensated by programmable FIR filter

Receiver (Rx) Bandwidth 200 MHz Receiver Alias Band

Rejection 80 dB Due to digital filters

Maximum Useable Input Level

PHIGH 0 dB attenuation, increases decibel for decibel with attenuation, continuous wave (CW) = 1800 MHz, corresponds to −1 dBFS at ADC

−11 dBm 75 MHz < f ≤ 3000 MHz −10.2 dBm 3000 MHz < f ≤ 4800 MHz −9.5 dBm 4800 MHz < f ≤ 6000 MHz Noise Figure NF 0 dB attenuation, at receiver port 11.5 dB 75 MHz < f ≤ 600 MHz 12 dB 600 MHz < f ≤ 3000 MHz 13 dB 3000 MHz < f ≤ 4800 MHz 15.2 dB 4800 MHz < f ≤ 6000 MHz Ripple 1.8 dB At band edge maximum bandwidth mode Input Third-Order Intercept

Point IIP3

Difference Product 12 dBm 75 MHz < f ≤ 600 MHz, (PHIGH − 12) dB per tone; 600 MHz < f ≤ 6000 MHz, (PHIGH − 10) dB per tone; two tones near band edge

Sum Product 12 dBm 75 MHz < f ≤ 600 MHz, (PHIGH − 12) dB per tone; 600 MHz < f ≤ 6000 MHz, (PHIGH − 10) dB per tone; two tones at bandwidth/6 offset from the LO

Third-Order Harmonic Distortion

HD3 75 MHz < f ≤ 600 MHz, (PHIGH − 6) dB; 600 MHz < f ≤ 6000 MHz, (PHIGH − 4) dB; CW tone at bandwidth/6 offset from the LO

−65 dBc 75 MHz < f ≤ 600 MHz −66 dBc 600 MHz < f ≤ 4800 MHz −62 dBc 4800 MHz < f ≤ 6000 MHz



Rev. 0 | of 68

Parameter Symbol Min Typ Max Unit Test Conditions/Comments Second-Order Input

Intermodulation Intercept Point

IIP2 62 dBm 75 MHz < f ≤ 600 MHz, (PHIGH − 12) dB per tone; 600 MHz < f ≤ 6000 MHz, (PHIGH − 10) dB per tone; 0 dB attenuation, complex

Image Rejection 75 dB QEC active, within 200 MHz receiver bandwidth

Input Impedance 100 Ω Differential (see Figure 168) Receiver to Receiver

Isolation 77 dB 75 MHz < f ≤ 600 MHz

65 dB 600 MHz < f ≤ 4800 MHz 61 dB 4800 MHz < f ≤ 6000 MHz Receiver Band Spurs

Referenced to RF Input at Maximum Gain

−95 dBm No more than one spur at this level per 10 MHz of receiver bandwidth

Receiver LO Leakage at Receiver Input at Maximum Gain

Leakage decreases decibel for decibel with attenuation for first 12 dB

−70 dBm 75 MHz < f ≤ 600 MHz −70 dBm 600 MHz < f ≤ 3000 MHz −65 dBm 3000 MHz < f ≤ 6000 MHz

LO SYNTHESIZER LO Frequency Step 2.3 Hz 1.5 GHz to 2.8 GHz, 76.8 MHz phase

frequency detector (PFD) frequency LO Spur −85 dBc Excludes integer boundary spurs Integrated Phase Noise 2 kHz to 18 MHz

75 MHz LO 0.014 °rms Narrow PLL loop bandwidth (50 kHz) 1900 MHz LO 0.2 °rms Narrow PLL loop bandwidth (50 kHz) 3800 MHz LO 0.36 °rms Wide PLL loop bandwidth (300 kHz) 5900 MHz LO 0.54 °rms Wide PLL loop bandwidth (300 kHz)

Spot Phase Noise 75 MHz LO Narrow PLL loop bandwidth

10 kHz Offset −126.5 dBc/Hz 100 kHz Offset −132.8 dBc/Hz 1 MHz Offset −150.1 dBc/Hz 10 MHz Offset −150.7 dBc/Hz

1900 MHz LO Narrow PLL loop bandwidth 100 kHz Offset −100 dBc/Hz 200 kHz Offset −115 dBc/Hz 400 kHz Offset −120 dBc/Hz 600 kHz Offset −129 dBc/Hz 800 kHz Offset −132 dBc/Hz 1.2 MHz Offset −135 dBc/Hz 1.8 MHz Offset −140 dBc/Hz 6 MHz Offset −150 dBc/Hz 10 MHz Offset −153 dBc/Hz

3800 MHz LO Wide PLL loop bandwidth 100 kHz Offset −104 dBc/Hz 1.2 MHz Offset −125 dBc/Hz 10 MHz Offset −145 dBc/Hz

5900 MHz LO Wide PLL loop bandwidth 100 kHz Offset −99 dBc/Hz 1.2 MHz Offset −119.7 dBc/Hz 10 MHz Offset −135.4 dBc/Hz

LO PHASE SYNCHRONIZATION Change in LO delay per temperature change

Phase Deviation 1.6 ps/°C



Rev. 0 | of 68

Parameter Symbol Min Typ Max Unit Test Conditions/Comments EXTERNAL LO INPUT

Input Frequency fEXTLO 300 8000 MHz Input frequency must be 2× the desired LO frequency

Input Signal Power 0 12 dBm 50 Ω matching at the source 3 dBm fEXTLO ≤ 2 GHz, add 0.5 dBm/GHz above

2 GHz 6 dBm fEXTLO = 8 GHz External LO Input Signal

Differential To ensure adequate QEC

Phase Error 3.6 ps Amplitude Error 1 dB Duty Cycle Error 2 %

Even Order Harmonics −50 dBc CLOCK SYNTHESIZER

Integrated Phase Noise 1 kHz to 100 MHz 1966.08 MHz LO 0.4 °rms PLL optimized for close in phase noise

Spot Phase Noise 1966.08 MHz

100 kHz Offset −109 dBc/Hz 1 MHz Offset −129 dBc/Hz 10 MHz Offset −149 dBc/Hz

REFERENCE CLOCK (REF_CLK_IN±)

Frequency Range 10 1000 MHz Signal Level 0.3 2.0 V p-p AC-coupled, common-mode voltage (VCM) =

618 mV, use <1 V p-p input clock for best spurious performance

AUXILIARY CONVERTERS ADC

Resolution 12 Bits Input Voltage

Minimum 0.05 V Maximum VDDA_

3P3 − 0.05

V

DAC Resolution 10 Bits Includes four offset levels Output Voltage

Minimum 0.7 V 1 V VREF Maximum VDDA_

3P3 − 0.3

V 2.5 V VREF

Output Drive Capability 10 mA DIGITAL SPECIFICATIONS

(CMOS): SERIAL PERIPHERAL INTERFACE (SPI), GPIO_x

Logic Inputs Input Voltage

High Level VDD_ INTERFACE × 0.8

VDD_ INTERFACE

V

Low Level 0 VDD_ INTERFACE × 0.2

V

Input Current High Level −10 +10 μA



Rev. 0 | of 68

Parameter Symbol Min Typ Max Unit Test Conditions/Comments Low Level −10 +10 μA

Logic Outputs Output Voltage

High Level VDD_ INTERFACE × 0.8

V

Low Level VDD_ INTERFACE × 0.2

V

Drive Capability 3 mA

DIGITAL SPECIFICATIONS (CMOS): GPIO_3p3_x

Logic Inputs Input Voltage

High Level VDDA_ 3P3 × 0.8

VDDA_3P3 V

Low Level 0 VDDA_ 3P3 × 0.2

V

Input Current High Level −10 +10 μA Low Level −10 +10 μA

Logic Outputs Output Voltage

High Level VDDA_ 3P3 × 0.8

V

Low Level VDDA_ 3P3 × 0.2

V

Drive Capability 4 mA DIGITAL SPECIFICATIONS, LOW

VOLTAGE DIFFERENTIAL SIGNALING (LVDS)

Logic Inputs (SYSREF_IN±, SYNCINx±)

Input Voltage Range 825 1675 mV Each differential input in the pair Input Differential Voltage

Threshold −100 +100 mV

Receiver Differential Input Impedance

100 Ω Internal termination enabled

SPI TIMING See the UG-1295 for more information SCLK Period tCP 20 ns SCLK Pulse Width tMP 10 ns CS Setup to First SCLK

Rising Edge tSC 3 ns

Last SCLK Falling Edge to CS Hold

tHC 0 ns

SDIO Data Input Setup to SCLK

tS 2 ns

SDIO Data Input Hold to SCLK

tH 0 ns

SCLK Rising Edge to Output Data Delay (3-Wire Mode or 4-Wire Mode)

tCO 3 8 ns

Bus Turnaround Time, Read After Baseband Processor (BBP) Drives Last Address Bit

tHZM tH tCO ns




Rev. 0 | of 68

Parameter Symbol Min Typ Max Unit Test Conditions/Comments Bus Turnaround Time, Read

After ADRV9008-1 Drives Last Data Bit

tHZS 0 tCO ns

JESD204B DATA OUTPUT TIMING

AC-coupled

Unit Interval UI 81.38 320 ps Data Rate Per Channel (NRZ) 3125 12288 Mbps Rise Time tR 24 39.5 ps 20% to 80% in 100 Ω load Fall Time tF 24 39.4 ps 20% to 80% in 100 Ω load Output Common-Mode

Voltage VCM 0 1.8 V AC-coupled

Differential Output Voltage VDIFF 360 600 770 mV Short-Circuit Current IDSHORT −100 +100 mA Differential Termination

Impedance 80 94.2 120 Ω

Total Jitter 15.13 ps Bit error rate (BER) = 10−15 Uncorrelated Bounded

High Probability Jitter UBHPJ 0.56 ps

Duty Cycle Distortion DCD 0.369 ps SYSREF_IN± Setup Time to

REF_CLK_IN± 2.5 ns See Figure 2

SYSREF_IN± Hold Time to REF_CLK_IN±

−1.5 ns See Figure 2

Latency tLAT_FRM REF_CLK_IN± = 245.76 MHz 89.4 Clock

cycles Receiver bandwidth = 200 MHz, IQ rate = 245.76 MHz, lane rate = 9830.4 MHz, M = 2, L = 2, N = 16, S = 1

364.18 ns 1 VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RF_VCO_LDO, VDDA1P3_RF_LO,

VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.

CURRENT AND POWER CONSUMPTION SPECIFICATIONS

Table 2. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY CHARACTERISTICS

VDDA1P31 Analog Supply 1.267 1.3 1.33 V VDDD1P3_DIG Supply 1.267 1.3 1.33 V VDDA1P8_AN Supply 1.71 1.8 1.89 V VDDA1P8_BB Supply 1.71 1.8 1.89 V VDD_INTERFACE Supply 1.71 1.8 2.625 V CMOS and LVDS supply, 1.8 V to 2.5 V nominal range VDDA_3P3 Supply 3.135 3.3 3.465 V

POSITIVE SUPPLY CURRENT LO at 2600 MHz 200 MHz Receiver Bandwidth Two receivers enabled

VDDA1P31 Analog Supply 1645 mA VDDD1P3_DIG Supply 984 mA Receiver QEC active VDDA1P8_AN Supply 0.4 mA VDDA1P8_BB Supply 68 mA VDD_INTERFACE Supply 8 mA VDDA_3P3 Supply 3 mA No Auxiliary DAC x or AUXADC_x enabled (if enabled,

AUXADC_x adds 2.7 mA, and each Auxiliary DAC x adds 1.5 mA)

Total Power Dissipation 3.57 W Typical supply voltages, receiver QEC active 1 VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX, VDDA1P3_RF_VCO_LDO,

VDDA1P3_RF_LO, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.



Rev. 0 | of 68

TIMING DIAGRAMS

REF_CLK_IN±

AT DEVICE PINS AT DEVICE COREREF_CLK_IN± DELAYIN REFERENCE TO SYSREF_IN±

CLK DELAY = 2nstH = –1.5nstS = +2.5ns

t’H = +0.5nst’S = +0.5ns

tS

tH

tS

tH t’H

t’S t’S

t’H

1683

0-00

5

NOTES1. tH AND tS ARE THE HOLD AND SETUP TIMES FOR THE REF_CLK_IN± PINS. t’H AND t’S REFER TO THE DELAYED HOLD AND SETUP TIMES AT THE DEVICE CORE IN REFERENCE TO THE SYSREF_N± SIGNALS DUE TO AN INTERNAL BUFFER THAT THE SIGNAL PASSES THROUGH.

Figure 2. SYSREF_IN± Setup and Hold Timing

REF_CLK_IN±

SYSREF_IN±

VALID SYSREF INVALID SYSREFtH = –1.5nstS = +2.5ns

tS

tH

tS

tH

tS

tH

tS

tH

1683

0-00

6

Figure 3. SYSREF_IN± Setup and Hold Timing Examples, Relative to Device Clock



Rev. 0 | of 68

ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating VDDA1P31 to VSSA −0.3 V to +1.4 V VDDD1P3_DIG to VSSD −0.3 V to +1.4 V VDD_INTERFACE to VSSA −0.3 V to +3.0 V VDDA_3P3 to VSSA −0.3 V to +3.9 V VDD_INTERFACE Logic Inputs and

Outputs to VSSD −0.3 V to VDD_ INTERFACE + 0.3 V

JESD204B Logic Outputs to VSSA −0.3 V to VDDA1P3_SER Input Current to Any Pin Except

Supplies ±10 mA

Maximum Input Power into RF Port 23 dBm (peak) Maximum Junction Temperature 110°C Storage Temperature Range −65°C to +150°C 1 VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH,

VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX, VDDA1P3_RF_VCO_LDO, VDDA1P3_RF_LO, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_SYNTH, and VDDA1P3_CLOCK_VCO_LDO.

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

REFLOW PROFILE The ADRV9008-1 reflow profile is in accordance with the JEDEC JESD204B criteria for Pb-free devices. The maximum reflow temperature is 260°C.

THERMAL MANAGEMENT The ADRV9008-1 is a high power device that can dissipate over 3 W depending on the user application and configuration. Because of the power dissipation, the ADRV9008-1 uses an

exposed die package to provide the customer with the most effective method of controlling the die temperature. The exposed die allows cooling of the die directly. Figure 4 shows the profile view of the device mounted to a user printed circuit board (PCB) and a heat sink (typically the aluminum case) to keep the junction (exposed die) below the maximum junction temperature shown in Table 3. The device is designed for a lifetime of 10 years when operating at the maximum junction temperature.

THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Thermal resistance data for the ADRV9008-1 mounted on both a JEDEC 2S2P test board and a 10-layer Analog Devices, Inc., evaluation board is listed in Table 4. Do not exceed the absolute maximum junction temperature rating in Table 3. Ten-layer PCB entries refer to the 10-layer Analog Devices evaluation board, which more accurately reflects the PCB used in customer applications.

Table 4. Thermal Resistance1, 2 Package Type θJA θJC_TOP θJB ΨJT ΨJB Unit BC-196-13 21.1 0.04 4.9 0.3 4.9 °C/W 1 For the θJC test, 100 µm thermal interface material (TIM) is used. TIM is

assumed to have 3.6 thermal conductivity watts/(meter × Kelvin). 2 Using enhanced heat removal techniques such as PCB, heat sink, and airflow

improves the thermal resistance values.

ESD CAUTION

CUSTOMER CASE (HEAT SINK)

CUSTOMER THERMAL FILLER

SILICON (DIE)

IC PROFILEPACKAGE SUBSTRATE

CUSTOMER PCB 1683

0-00

8

Figure 4. Typical Thermal Management Solution



Rev. 0 | of 68

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VSSA VSSA VSSA RX2_IN+ RX2_IN– VSSA VSSA RX1_IN+ RX1_IN– VSSA VSSA VSSA VSSA

VSSA VSSA VSSA VSSA VSSARF_EXT_LO_I/O–

RF_EXT_LO_I/O+ VSSA VSSA VSSA VSSA VSSA VSSA

GPIO_3p3_3 VDDA1P3_RX VSSAVDDA1P3_

RF_VCO_LDOVDDA1P3_RF_

VCO_LDOVDDA1P1_

RF_VCOVDDA1P3_

RF_LO VSSA

VDDA1P3_AUX_VCO_

LDO VSSA VDDA_3P3 GPIO_3p3_9 RBIAS

GPIO_3p3_4 VSSA VSSA VSSA VSSA VSSA VSSA VSSAVDDA1P1_AUX_VCO VSSA VSSA GPIO_3p3_8 GPIO_3p3_10

GPIO_3p3_5 GPIO_3p3_6 VDDA1P8_BB VDDA1P3_BB VSSA REF_CLK_IN+ REF_CLK_IN– VSSAAUX_SYNTH_

OUT AUXADC_3 VDDA1P8_AN GPIO_3p3_7 GPIO_3p3_11

VSSA AUXADC_0 AUXADC_1 VSSA VSSA VSSA VSSA VSSA VSSA AUXADC_2 VSSA VSSA VSSA

VSSA VSSA VSSAVDDA1P3_ CLOCK_SYNTH VSSA

VDDA1P3_RF_SYNTH VDDA1P3_

AUX_SYNTHRF_SYNTH_

VTUNE VSSA VSSA VSSA VSSA VSSA

VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA DNC

VSSA GPIO_18 RESETGP_

INTERRUPT TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA DNC

VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CS GPIO_14 GPIO_9 VSSA VSSA

VSSA SYNCIN1– SYNCIN1+ GPIO_6 GPIO_7 VSSDVDDD1P3_

DIGVDDD1P3_

DIG VSSD GPIO_15 GPIO_8VDDA1P3_

SERVDDA1P3_

SER

VSSA SYNCIN0– SYNCIN0+ RX1_ENABLE VSSD RX2_ENABLE VSSD VSSA GPIO_17 GPIO_16VDD_

INTERFACEVDDA1P3_

SERVDDA1P3_

SER

VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSAVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SER VSSA

VSSA

VDDA1P3_RX_RF

GPIO_3p3_0

GPIO_3p3_1

GPIO_3p3_2

VSSA

VSSA

DNC

DNC

VSSA

VSSA

VDDA1P1_CLOCK_VCO

VDDA1P3_CLOCK_

VCO_LDO

AUX_SYNTH_VTUNE VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+

VDDA1P3_SER

VDDA1P3_SER VSSA

VDDA1P3_SER

VDDA1P3_SER

VDDA1P3_SER

VDDA1P3_SER

1 2 3 4 5 6 7 8 9 10 11 12 13 14

A

B

C

D

E

F

G

H

J

K

L

M

N

P

ADRV9008-1 1683

0-99

9

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions Pin No. Type Mnemonic Description A1 to A4, A7, A8, A11 to A14, B2

to B6, B9 to B14, C4, C9, C11, D3 to D9, D11, D12, E6, E9, F1, F2, F5 to F10, F12 to F14, G1 to G4, G6, G10 to G14, H2 to H10, H13, J2, J13, K1, K2, K13, K14, L1, L2, M2, M9, N2, N7, N14, P2, P3, P10

Input VSSA Analog Supply Voltage (VSS).



Rev. 0 | of 68

Pin No. Type Mnemonic Description A5, A6 Input RX2_IN+, RX2_IN− Differential Input for Receiver 1. When unused, connect these

pins to ground. A9, A10 Input RX1_IN+, RX1_IN− Differential Input for Receiver 2. When unused, connect these

pins to ground. B1 Input VDDA1P3_RX_RF Receiver Mixer Supply. B7, B8 Input RF_EXT_LO_I/O−,

RF_EXT_LO_I/O+ Differential External LO Input/Output. If these pins are used for external LO, the input frequency must be 2× the desired carrier frequency. When unused, do not connect these pins.

C1 Input/ output

GPIO_3p3_0 GPIO Pin Referenced to 3.3 V Supply. The alternate function is Auxiliary DAC 4. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or this pin can be left floating, programmed as an output, and driven low.

C2 Input/ output

GPIO_3p3_3 GPIO Pin Referenced to 3.3 V Supply. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or this pin can be left floating, programmed as an output, and driven low.

C3 Input VDDA1P3_RX 1.3 V Supply for Receiver Baseband Circuits, Transimpedance Amplifier (TIA), Baseband Filters, and Auxiliary DACs.

C5, C6 Input VDDA1P3_RF_VCO_LDO RF VCO Low Dropout (LDO) Supply Inputs. Connect Pin C5 to Pin C6. Use a separate trace to a common supply point.

C7 Input VDDA1P1_RF_VCO 1.1 V VCO Supply. Decouple this pin with 1 µF. C8 Input VDDA1P3_RF_LO 1.3 V LO Generator for RF Synthesizer. This pin is sensitive to

aggressors. C10 Input VDDA1P3_AUX_VCO_LDO 1.3 V Supply. C12 Input VDDA_3P3 General-Purpose Output Pull-Up Voltage and Auxiliary DAC

Supply Voltage. C13 Input/

output GPIO_3p3_9 GPIO Pin Referenced to 3.3 V Supply. The alternative function

is Auxiliary DAC 9. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or this pin can be left floating, programmed as an output, and driven low.

C14 Input/ output

RBIAS Bias Resistor. Tie this pin to ground using a 14.3 kΩ resistor. This pin generates an internal current based on an external 1% resistor.

D1 Input/ output

GPIO_3p3_1 GPIO Pin Referenced to 3.3 V Supply. The alternative function is Auxiliary DAC 5. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or this pin can be left floating, programmed as an output, and driven low.

D2 Input/ output


D10 Input VDDA1P1_AUX_VCO 1.1 V VCO Supply. Decouple with 1 µF. D13 Input/





Rev. 0 | of 68

Pin No. Type Mnemonic Description D14 Input/



E1 Input/ output

GPIO_3p3_2 GPIO Pin Referenced to 3.3 V Supply. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or this pin can be left floating, programmed as an output, and driven low.

E2 Input/ output


E3 Input/ output


E4 Input VDDA1P8_BB 1.8 V Supply for the ADC and DAC. E5 Input VDDA1P3_BB 1.3 V Supply for the ADC, DAC, and Auxiliary ADCs. E7, E8 Input REF_CLK_IN+, REF_CLK_IN− Device Clock Differential Input. E10 Output AUX_SYNTH_OUT Auxiliary PLL Output. When unused, do not connect this pin. E11, F3, F4, F11 Input AUXADC_0 to AUXADC_3 Auxiliary ADC Input. When unused, connect these pins to ground

with a pull-down resistor, or connect directly to ground. E12 Input VDDA1P8_AN 1.8 V Bias Supply for Analog Circuitry. E13 Input/



E14 Input/ output

GPIO_3p3_11 GPIO Pin Referenced to 3.3 V Supply. The alternative function is Auxiliary DAC 3. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or this pin can be left floating, programmed as outputs, and driven low.

G5 Input VDDA1P3_CLOCK_SYNTH 1.3 V Supply Input for Clock Synthesizer. Use a separate trace on the PCB back to a common supply point.

G7 Input VDDA1P3_RF_SYNTH 1.3 V RF Synthesizer Supply Input. This pin is sensitive to aggressors.

G8 Input VDDA1P3_AUX_SYNTH 1.3 V Auxiliary Synthesizer Supply Input. G9 Output RF_SYNTH_VTUNE RF Synthesizer VTUNE Output. H1, J1, H14, J14 DNC1 DNC Do Not Connect. Do not connect these pins. H11 Input/

output GPIO_12 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or it can be left floating, programmed as an output, and driven low.

H12 Input/ output

GPIO_11 Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or it can be left floating, programmed as an output, and driven low.



Rev. 0 | of 68

Pin No. Type Mnemonic Description J3 Input/

output GPIO_18 Digital GPIO, 1.8 V to 2.5 V. The joint test action group (JTAG)

function is test clock (TCLK). Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or it can be left floating, programmed as an output, and driven low.

J4 Input RESET Active Low Chip Reset.

J5 Output GP_INTERRUPT General-Purpose Digital Interrupt Output Signal. When unused, do not connect this pin.

J6 Input TEST Pin Used for JTAG Boundary Scan. When unused, connect this pin to ground.

J7 Input/ output

GPIO_2 Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0. Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or it can be left floating, programmed as an output, and driven low.

J8 Input/ output


J9 Input/ output

SDIO Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire Mode.

J10 Output SDO Serial Data Output. In SPI 3-Wire mode, do not connect this pin. J11 Input/



J12 Input/ output


K3, K4 Input SYSREF_IN+, SYSREF_IN− LVDS Input. K5 Input/

output GPIO_5 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test data

output (TDO). Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or it can be left floating, programmed as an output, and driven low.

K6 Input/ output

GPIO_4 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test rest (TRST). Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or it can be left floating, programmed as an output, and driven low.

K7 Input/ output


K8 Input/ output


K9 Input SCLK Serial Data Bus Clock. K10 Input CS Serial Data Bus Chip Select, Active Low.



Rev. 0 | of 68

Pin No. Type Mnemonic Description K11 Input/



K12 Input/ output


L3, L4 Input SYNCIN1−, SYNCIN1+ LVDS Input. When unused, connect these pins to ground with a pull-down resistor, or connect directly to ground.

L5 Input/ output

GPIO_6 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test data input (TDI). Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or it can be left floating, programmed as an output, and driven low.

L6 Input/ output

GPIO_7 Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test mode select input (TMS). Because this pin contains an input stage, the voltage on the pin must be controlled. When unused, this pin can be tied to ground through a resistor to safeguard against misconfiguration, or it can be left floating, programmed as an output, and driven low.

L7, L10, M6, M8 Input VSSD Digital VSS. L8, L9 Input VDDD1P3_DIG 1.3 V Digital Core. Connect Pin L8 to Pin L9. Use a separate

trace to a common supply point. L11 Input/



L12 Input/ output


L13, L14, M13, M14, N8 to N13, P8, P9, P11 to P14

Input VDDA1P3_SER 1.3 V Supply for JESD204B Serializer.

M1 Input VDDA1P1_CLOCK_VCO 1.1 V VCO Supply. Decouple this pin with 1 µF. M3, M4 Input SYNCIN0−, SYNCIN0+ JESD204B Receiver Channel 0. These pins form the synchro-

nization signal associated with receiver channel data on the JESD204B interface. When unused, connect these pins to ground with a pull-down resistor, or connect directly to ground.

M5 Input RX1_ENABLE Receiver 1 Enable Pin. When unused, connect this pin to ground with a pull-down resistor, or connect directly to ground.

M7 Input RX2_ENABLE Receiver 2 Enable Pin. When unused, connect this pin to ground with a pull-down resistor, or connect directly to ground.

M10 Input/ output


M11 Input/ output


M12 Input VDD_INTERFACE Input/Output Interface Supply, 1.8 V to 2.5 V. N1 Input VDDA1P3_CLOCK_VCO_LDO 1.3 V Supply. Use a separate trace to a common supply point.



Rev. 0 | of 68

Pin No. Type Mnemonic Description N3, N4 Output SERDOUT3−, SERDOUT3+ RF Current Mode Logic (CML) Differential Output 3. When

unused, do not connect these pins. N5, N6 Output SERDOUT2−, SERDOUT2+ RF CML Differential Output 2. When unused, do not connect

these pins. P1 Output AUX_SYNTH_VTUNE Auxiliary Synthesizer VTUNE Output. P4, P5 Output SERDOUT1−, SERDOUT1+ RF CML Differential Output 1. When unused, do not connect

these pins. P6, P7 Output SERDOUT0−, SERDOUT0+ RF CML Differential Output 0. When unused, do not connect

these pins. 1 DNC means do not connect.



Rev. 0 | of 68

TYPICAL PERFORMANCE CHARACTERISTICS The temperature settings refer to the die temperature.

75 MHz TO 525 MHz BAND 0

–100

–40

–20

–80

–90

–60

–30

–10

–70

–50

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)

75 525475275125 375 425225 325175RECEIVER LO FREQUENCY (MHz)

+110°C+25°C–40°C

1683

0-58

1

Figure 6. Receiver LO Leakage vs. Receiver LO Frequency, 75 MHz, 300 MHz,

525 MHz; Receiver Attenuation = 0 dB, RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS

45

0

25

35

5

15

30

40

10

20

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

0 20181682 12 146 104RECEIVER ATTENUATION (dB)

+110°C+25°C–40°C

1683

0-58

2

Figure 7. Receiver Noise Figure vs. Receiver Attenuation, LO = 75 MHz,

RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, Integration Bandwidth = 1 MHz to 25 MHz

45

0

25

35

5

15

30

40

10

20

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


+110°C+25°C–40°C

1683

0-58

3



45

0

25

35

5

15

30

40

10

20

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


+110°C+25°C–40°C

1683

0-58

4



20

0

12

16

2

4

8

14

18

6

10

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

75 475175 375275RECEIVER LO FREQUENCY (MHz)

+110°C+25°C–40°C

1683

0-58

5

Figure 10. Receiver Noise Figure vs. Receiver LO Frequency, Receiver

Attenuation = 0 dB, RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, Integration Bandwidth = ±25 MHz

20

18

8

10

14

12

16

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

–25 2515–15 5–5RECEIVER OFFSET FREQUENCY FROM LO (75MHz)

+110°C+25°C–40°C

1683

0-58

9

Figure 11. Receiver Noise Figure vs. Receiver Offset Frequency from LO,

Integration Bandwidth = 200 kHz, LO = 75 MHz



Rev. 0 | of 68

20

18

8

10

14

12

16

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


+110°C+25°C–40°C

1683

0-59

0

Figure 12. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Integration Bandwidth = 200 kHz, LO = 300 MHz

20

18

8

10

14

12

16

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


+110°C+25°C–40°C

1683

0-59

1


100

50

55

60

65

70

75

80

85

90

95

0 2 4 8 1612 20 24 286 1410 18 22 26 30

RECE

IVER

IIP2

(dBm

)

RECEIVER ATTENUATION (dB)

+110°C (SUM)+25°C (SUM)–40°C (SUM)+110°C (DIFF)+25°C (DIFF) –40°C (DIFF)

1683

0-59

2

Figure 14. Receiver IIP2 vs. Receiver Attenuation, LO = 75 MHz, Tones Placed at 82.5 MHz and 83.5 MHz, −23.5 dBm Plus Attenuation

110

50

60

70

80

90

100

0 2 4 8 1612 20 24 286 1410 18 22 26 30

RECE

IVER

IIP2

(dBm

)



1683

0-59

3

Figure 15. Receiver IIP2 vs. Receiver Attenuation, LO = 300 MHz, Tones Placed

at 310 MHz and 311 MHz, −23.5 dBm Plus Attenuation

80

40

45

55

50

60

65

70

75

80.081.0

82.583.5

87.588.5

92.593.575

97.598.5

90.091.0

100.0101.0

95.096.0

102.5103.5

REC

EIVE

R II

P2 S

UM

AN

D D

IFFE

REN

CE

AC

RO

SS B

AN

DW

IDTH

(dB

m)

SWEPT PASS BAND FREQUENCY (MHz)


1683

0-59

4

Figure 16. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass

Band Frequency, Receiver Attenuation = 0 dB, LO = 75 MHz, 10 Tone Pairs, −23.5 dBm Each

80

40

45

55

50

60

65

70

75

305.0306.0

307.5308.5

310.0311.0

315.0316.0

320.0321.0

312.5313.5

322.5323.5

317.5318.5

300

327.5328.5

325.0326.0

REC

EIVE

R II

P2 S

UM

AN

D D

IFFE

REN

CE

AC

RO

SS B

AN

DW

IDTH

(dB

m)



1683

0-59

5

Figure 17. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass

Band Frequency, Receiver Attenuation = 0 dB, LO = 300 MHz, 10 Tone pairs, −23.5 dBm Each



Rev. 0 | of 68

110

50

60

70

80

90

100

0 5 10 15 2520 30

REC

EIVE

R II

P2 (d

Bm

)


Rx1 (SUM) = +110°CRx1 (DIFF) = +110°CRx1 (SUM) = +25°CRx1 (DIFF) = +25°CRx1 (SUM) = –40°CRx1 (DIFF) = –40°C


1683

0-59

6

Figure 18. Receiver IIP2 vs. Receiver Attenuation, LO = 75 MHz, Tones Placed at 77 MHz and 97 MHz, −23.5 dBm Plus Attenuation

80

40

45

50

55

65

75

60

70

79.577.0

82.077.0

84.577.0

87.077.0

97.077.0

92.077.0

94.577.0

89.577.0

99.577.0

REC

EIVE

R II

P2 S

UM

AN

D D

IFFE

REN

CE

AC

RO

SS B

AN

DW

IDTH

(dB

m)




1683

0-59

7

Figure 19. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 75 MHz, Tone 1 =

77 MHz, Tone 2 Swept, −23.5 dBm Each

50

0

5

10

15

20

25

30

35

40

45

0 5 10 15 2520 30

REC

EIVE

R IN

PUT

IP3

(dBm

)

ATTENUATION (dB)

Rx1 = +110°CRx1 = +25°CRx1 = –40°CRx2 = +110°CRx2 = +25°CRx2 = –40°C

1683

0-59

8

Figure 20. Receiver IIP3 vs. Attenuation, LO = 300 MHz, Tone 1 = 325 MHz, Tone 2 = 326 MHz, −21 dBm Plus Attenuation

25

0

5

10

15

20

305.0306.0

307.5308.5

310.0311.0

312.5313.5

315.0316.0

317.5318.5

320.0321.0

322.5323.5

325.0326.0

327.5328.5

REC

EIVE

R II

P3 (d

Bm

)



1683

0-59

9

Figure 21. Receiver IIP3, Receiver Attenuation = 0 dB, LO = 300 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each, Swept Across Pass Band

50

0

5

10

15

20

25

30

35

40

45

0 5 10 20 3025 35

REC

EIVE

R II

P3 (d

Bm)

ATTENUATION (dB)


1683

0-60

0


25

0

5

10

15

20

302.0304.5

302.0307.0

302.0309.5

302.0314.5

302.0312.0

302.0317.0

302.0319.5

302.0322.0

302.0324.5

302.0327.0

REC

EIVE

R II

P3 (d

Bm

)



1683

0-60

1

Figure 23. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 300 MHz, Tone 1 = 302 MHz, Tone 2 Swept Across Pass Band, −19 dBm

Each



Rev. 0 | of 68

–10

–110

–90

–70

–50

–100

–80

–60

–40

–30

–20

–25 –20 –5 10–15 0 15–10 5 20 25

REC

EIVE

R IM

AG

E (d

Bc)

BASEBAND FREQUENCY OFFSET

+110°C+25°C–40°C

1683

0-60

2

Figure 24. Receiver Image vs. Baseband Frequency Offset, Attenuation = 0 dB, RF Bandwidth = 50 MHz, Tracking Calibration Active,

Sample Rate = 61.44 MSPS, LO = 75 MHz

–10

–110

–90

–70

–50

–100

–80

–60

–40

–30

–20

–25 –20 –5 10–15 0 15–10 5 20 25

REC

EIVE

R IM

AGE

(dB

c)


+110°C+25°C–40°C

1683

0-60

3



–10

–110

–90

–70

–50

–100

–80

–60

–40

–30

–20

–25 –20 –5 10–15 0 15–10 5 20 25

REC

EIVE

R IM

AGE

(dB

c)


+110°C+25°C–40°C

1683

0-60

4



0

–120

–80

–100

–60

–40

–20

0 155 2010 25 30

REC

EIVE

R IM

AG

E (d

Bc)

ATTENUATOR SETTING (dB)

+110°C+25°C–40°C

1683

0-60

5

Figure 27. Receiver Image vs. Attenuator Setting, RF Bandwidth = 25 MHz, Tracking Calibration Active, Sample Rate = 61.44 MSPS, LO = 75 MHz,

Baseband Frequency = 25 MHz

0

–120

–80

–100

–60

–40

–20

0 155 2010 25 30

REC

EIVE

R IM

AG

E (d

Bc)


+110°C+25°C–40°C

1683

0-60

6

Figure 28. Receiver Image vs. Attenuator Setting, RF Bandwidth = 25 MHz, Tracking Calibration Active, Sample Rate = 61.44 MSPS, LO = 325 MHz,


25

–15

–5

–10

0

5

15

10

20

0 155 2010 25 30

RECE

IVER

GAI

N (d

B)

RECEIVER ATTENUATOR SETTING (dB)

+110°C+25°C–40°C

1683

0-60

7

Figure 29. Receiver Gain vs. Receiver Attenuator Setting, RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, LO = 75 MHz



Rev. 0 | of 68

25

–15

–5

–10

0

5

15

10

20

0 155 2010 25 30

REC

EIVE

R G

AIN

(dB

)


+110°C+25°C–40°C

1683

0-60

8

Figure 30. Receiver Gain vs. Receiver Attenuator Setting,

RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, LO = 325 MHz

25

–15

–5

–10

0

5

15

10

20

0 155 2010 25 30

REC

EIVE

R G

AIN

(dB

)


+110°C+25°C–40°C

1683

0-60

9

Figure 31. Receiver Gain vs. Receiver Attenuator Setting, RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, LO = 525 MHz

10

14

12

16

18

22

20

24

75 275125 375175 475225 320 425 525

REC

EIVE

R G

AIN

(dB

)

LO FREQUENCY (MHz)

+110°C+25°C–40°C

1683

0-61

0

Figure 32. Receiver Gain vs. LO Frequency, RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS

–0.5

–0.3

–0.4

–0.2

0

0.4

0.2

–0.1

0.3

0.1

0.5

0 123 186 24 279 15 21 30

RECE

IVER

GAI

N ST

EP E

RRO

R (d

B)


+110°C+25°C–40°C

1683

0-61

1

Figure 33. Receiver Gain Step Error vs. Receiver Attenuator Setting,

LO = 75 MHz

–0.5

–0.3

–0.4

–0.2

0

0.4

0.2

–0.1

0.3

0.1

0.5

0 123 186 24 279 15 21 30

RECE

IVER

GAI

N ST

EP E

RRO

R (d

B)


+110°C+25°C–40°C

1683

0-61

2


LO = 325 MHz

–0.5

–0.3

–0.4

–0.2

0

0.4

0.2

–0.1

0.3

0.1

0.5

0 123 186 24 279 15 21 30

RECE

IVER

GAI

N ST

EP E

RRO

R (d

B)


+110°C+25°C–40°C

1683

0-61

3


LO = 525 MHz



Rev. 0 | of 68

0.5

–1.0–0.9–0.8–0.7–0.6–0.5–0.4–0.3–0.2–0.1

00.10.20.30.4

0.99

8

3.99

8

6.99

8

9.99

8

18.9

94

12.9

82

25.0

06

27.9

98

15.9

86

22.0

06

NO

RM

ALI

ZED

REC

EIVE

RB

ASE

BA

ND

FLA

TNES

S (d

B)

BASEBAND OFFSET FREQUENCY (MHz)

I RIPPLE = +110°CI RIPPLE = +25°CI RIPPLE = –40°CQ RIPPLE = +110°CQ RIPPLE = +25°CQ RIPPLE = –40°C

1683

0-61

4

Figure 36. Normalized Receiver Baseband Flatness vs. Baseband Offset

Frequency (Receiver Flatness), LO = 75 MHz

–50

–110

–90

–100

–80

–70

–60

75 275125 375175 475225 325 425 525

REC

EIVE

R D

C O

FFSE

T (d

BFS

)

RECEIVER LO FREQUENCY (MHz)

+110°C+25°C–40°C

1683

0-61

5

Figure 37. Receiver DC Offset vs. Receiver LO Frequency

–70

–110

–100

–105

–95

–85

–75

–90

–80

RECE

IVER

DC

OFF

SET

(dBF

S)

+110°C+25°C–40°C

0 155 2010 25 30RECEIVER ATTENUATOR SETTING (dB) 16

830-

616

Figure 38. Receiver DC Offset vs. Receiver Attenuator Setting,

LO = 75 MHz

–70

–110

–100

–105

–95

–85

–75

–90

–80

RECE

IVER

DC

OFF

SET

(dBF

S)

+110°C+25°C–40°C

0 155 2010 25 30RECEIVER ATTENUATOR SETTING (dB) 16

830-

617

Figure 39. Receiver DC Offset vs. Receiver Attenuator Setting, LO = 525 MHz

–30

–150

–60

–40

–100

–80

–120

–70

–50

–110

–90

–130

–140

REC

EIVE

R H

D2

LEFT

(dB

c)

–30 30200–20 10–10BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

ATTN = 15 +110°CATTN = 15 +25°CATTN = 15 –40°CATTN = 0 +110°CATTN = 0 +25°CATTN = 0 –40°C

1683

0-61

8

Figure 40. Receiver Second-Order Harmonic Distortion (HD2) Left vs. Baseband Frequency Offset and Attenuation, Tone Level = −21 dBm at

Attenuation = 0 dB, X-Axis Is Baseband Frequency Offset of Fundamental Tone, Not Frequency of HD2 Product (HD2 Product is 2× Baseband

Frequency), HD2 Canceller Disabled, LO = 75MHz

–30

–150

–60

–40

–100

–80

–120

–70

–50

–110

–90

–130

–140

REC

EIVE

R H

D2

LEFT

(dB

c)



1683

0-61

9

Figure 41. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation, Tone Level −21 dBm at Attenuation = 0 dB, X-Axis Is Baseband Frequency

Offset of Fundamental Tone, Not Frequency of HD2 Product (HD2 Product Is 2× Baseband Frequency), HD2 Canceller Disabled, LO = 300 MHz



Rev. 0 | of 68

–30

–150

–60

–40

–100

–80

–120

–70

–50

–110

–90

–130

–140

REC

EIVE

R H

D2

LEFT

(dB

c)



1683

0-62

0

Figure 42. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation, Tone Level −21 dBm at Attenuation = 0 dB, X-Axis Is Baseband Frequency

Offset of Fundamental Tone, Not Frequency of HD2 Product (HD2 Product Is 2× Baseband Frequency), HD2 Canceller Disabled, LO = 525 MHz

–10

–150

–130

–110

–90

–70

–50

–30

–25 –20 –15 –10 –5 575

10 15 2520

REC

EIVE

R H

D3,

LEF

T A

ND

RIG

HT

(dB

c)

FREQUENCY OFFSET FROM LO AND ATTENUATION (MHz)

+110°C Rx2 (RIGHT)+110°C Rx1 (RIGHT)+25°C Rx2 (RIGHT)+25°C Rx1 (RIGHT)–40°C Rx2 (RIGHT)–40°C Rx1 (RIGHT)

+110°C Rx2 (LEFT)+110°C Rx1 (LEFT)+25°C Rx2 (LEFT)+25°C Rx1 (LEFT)–40°C Rx2 (LEFT)–40°C Rx1 (LEFT)

1683

0-62

1

Figure 43. Receiver HD3, Left and Right vs. Frequency Offset from LO and Attenuation, Tone Level = −16 dBm at Attenuation = 0 dB, LO = 75 MHz

–10

–150

–130

–110

–90

–70

–50

–30

–25 –20 –15 –10 –5 5300

10 15 2520

REC

EIVE

R H

D3,

LEF

T A

ND

RIG

HT

(dB

c)

FREQUENCY OFFSET FROM LO (MHz)



1683

0-62

2

Figure 44. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone

Level −17 dBm at Attenuation = 0 dB, LO = 300 MHz

–10

–150

–130

–110

–90

–70

–50

–30

–25 –20 –15 –10 –5 5525

10 15 2520

REC

EIVE

R H

D3,

LEF

T A

ND

RIG

HT

(dB

c)




1683

0-62

3


Level −17 dBm at Attenuation = 0 dB, LO = 525 MHz

0

–50

–30

–40

–20

–10

–35

–45

–25

–15

–5

–65 –35–55 –25–45 –15 5–5

RECE

IVER

EVM

(dB)

LTE 20MHz RF INPUT POWER (dBm)

+110°C+25°C–40°C

1683

0-62

4

Figure 46. Receiver Error Vector Magnitude (EVM) vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF Signal, LO = 75 MHz, Default AGC Settings

0

–50

–30

–40

–20

–10

–35

–45

–25

–15

–5

–65 –35–55 –25–45 –15 5–5

RECE

IVER

EVM

(dB)


+110°C+25°C–40°C

1683

0-62

5

Figure 47. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF Signal, LO = 300 MHz, Default AGC Settings



Rev. 0 | of 68

0

–50

–30

–40

–20

–10

–35

–45

–25

–15

–5

–65 –35–55 –25–45 –15 5–5

RECE

IVER

EVM

(dB)


+110°C+25°C–40°C

1683

0-62

6


0

100

60

80

40

20

70

90

50

30

10

0 300100 400200 500 600

REC

EIVE

R T

O R

ECEI

VER

ISO

LATI

ON

(dB

)

LO FREQUENCY (MHz)

Rx1 TO Rx2Rx2 TO Rx1

1683

0-62

7

Figure 49. Receiver to Receiver Isolation vs. LO Frequency,


–80–85–90–95

–100–105–110–115–120–125–130–135–140–145–150–155–160–165–170

100 1k 10k 100k 1M 10M 100M

PHA

SE N

OIS

E (d

Bc/

Hz)

FREQUENCY (Hz) 1683

0-05

0

100Hz = –110.00dBc/Hz1kHz = –120.75dBc/Hz10kHz = –126.54dBc/Hz100kHz = –132.76dBc/Hz1MHz = –150.09dBc/Hz10MHz = –151.09dBc/Hz100MHz = –150.74dBc/Hz

Figure 50. LO Phase Noise vs. Frequency Offset, LO = 75 MHz, PLL Loop

Bandwidth = 50 kHz

–80–85–90–95

–100–105–110–115–120–125–130–135–140–145–150–155–160–165–170

100 1k 10k 100k 1M 10M 100M

PHA

SE N

OIS

E (d

Bc/

Hz)

FREQUENCY (Hz) 1683

0-05

1



Bandwidth = 50 kHz

–80–85–90–95

–100–105–110–115–120–125–130–135–140–145–150–155–160–165–170

100 1k 10k 100k 1M 10M 100M

PHA

SE N

OIS

E (d

Bc/

Hz)

FREQUENCY (Hz) 1683

0-05

2



Bandwidth = 50 kHz



Rev. 0 | of 68


–3.00

–1.00

–0.50

–0.75

–0.25

–1.50

–2.25

–1.75

–2.00

–1.25

–2.50

–2.75

RECE

IVER

OFF

CHI

P M

ATCH

ING

CIRC

UIT

PATH

LO

SS (d

B)

LO FREQUENCY (MHz)

500

1500

2500

3000

1000

2000

1250

2250

275075

0

1750

1683

0-69

5

Figure 53. Receiver Off Chip Matching Circuit Path Loss vs. LO Frequency,

Can Be Used for De-Embedding Performance Data

0

–100

–40

–20

–30

–10

–60

–90

–70

–80

–50

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)


650

1450

2250

2850

1050

1850

1250

2050

2450

265085

0

1650

+110°C+25°C–40°C

1683

0-69

6

Figure 54. Receiver LO Leakage vs. Receiver LO Frequency, Receiver

Attenuation = 0 dB, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS

45

0

30

40

10

20

25

35

15

5

RECE

IVER

NO

ISE

FIG

URE

(dBc

)

0 201262 168 14 18104

ATTENUATION (dB)

+110°C+25°C–40°C

1683

0-69

7

Figure 55. Receiver Noise Figure vs. Attenuation, LO = 650 MHz, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS, Integration Bandwidth =

500 kHz to 100 MHz

45

0

30

40

10

20

25

35

15

5

RECE

IVER

NO

ISE

FIG

URE

(dBc

)

0 201262 168 14 18104

ATTENUATION (dB)

+110°C+25°C–40°C

1683

0-69

8

Figure 56. Receiver Noise Figure vs. Attenuation, LO = 1850 MHz, 200 MHz Bandwidth, Sample Rate = 245.76 MSPS,

Integration Bandwidth = 500 kHz to 100 MHz

45

0

30

40

10

20

25

35

15

5

RECE

IVER

NO

ISE

FIG

URE

(dBc

)

0 201262 168 14 18104


+110°C+25°C–40°C

1683

0-69

9

Figure 57. Receiver Noise Figure vs. Receiver Attenuation, 2850 MHz LO, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS,


20

0

12

16

14

18

8

2

6

4

10

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


650

1450

2250

2850

1050

1850

1250

2050

2450

265085

0

1650

+110°C+25°C–40°C

1683

0-70

0

Figure 58. Receiver Noise Figure vs. Receiver LO Frequency,

Receiver Attenuation = 0 dB, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS, Integration Bandwidth = ±100 MHz



Rev. 0 | of 68

8

10

12

14

16

18

20

–100 –80 –60 –40 –20 0 20 40 60 80 100

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

RECEIVER OFFSET FREQUENCY FROM LO (650MHz)

–40°C+25°C+110°C

1683

0-32

3

Figure 59. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Integration

Bandwidth = 200 kHz, LO = 650 MHz

8

10

12

14

16

18

20

–100 –80 –60 –40 –20 0 20 40 60 80 100

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


–40°C+25°C+110°C

1683

0-32

4

Figure 60. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Integration

Bandwidth = 200 kHz, LO = 1850 MHz

8

10

12

14

16

18

20

–100 –80 –60 –40 –20 0 20 40 60 80 100

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)


–40°C+25°C+110°C

1683

0-32

5


0

5

10

15

20

25

30

35

40

–20 –15 –10 –5 0 5 10

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

CW OUT OF BAND BLOCKER LEVEL (dBm)

–40°C+25°C+110°C

1683

0-32

6

Figure 62. Receiver Noise Figure vs. CW Out of Band Blocker Level, LO = 1685 MHz, Blocker = 2085 MHz

50

60

70

80

90

100

110

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

REC

EIVE

R II

P2 (d

Bm

)


–40°C (SUM)–40°C (DIFF)+25°C (SUM)+25°C (DIFF)+110°C (SUM)+110°C (DIFF)

1683

0-32

7

Figure 63. Receiver IIP2 vs. Receiver Attenuation, LO = 1800 MHz, Tones

Placed at 1845 MHz and 1846 MHz, −21 dBm Each at Attenuation = 0 dB

40

45

50

55

60

65

70

75

80

806 826 846 866 886 906805 825 845 865 885 905

800

REC

EIVE

R II

P2SU

M A

ND

DIF

FER

ENC

EA

CR

OSS

BA

ND

WID

TH (d

Bm

)



1683

0-32

8

Figure 64. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 800 MHz, Six Tone Pairs,

−21 dBm Each



Rev. 0 | of 68

40

45

50

55

60

65

70

75

80

1806 1826 1846 1866 1886 19061805 1825 1845 1865 1885 1905

1800

REC

EIVE

R II

P2SU

M A

ND

DIF

FER

ENC

EA

CR

OSS

BA

ND

WID

TH (d

Bm

)



1683

0-32

9


−21 dBm Each

40

45

50

55

60

65

70

75

80

2906 2926 2946 2966 2986 30062905 2925 2945 2965 2985 3005

REC

EIVE

R II

P2SU

MA

ND

DIF

FER

ENC

EA

CR

OSS

BA

ND

WID

TH (d

Bm

)


–40°C (DIFF)–40°C (SUM)

+25°C (SUM)+25°C (DIFF)+110°C (SUM)+110°C (DIFF)

1683

0-33

0


−21 dBm Each

100

95

90

85

80

75

70

65

60

55

500 20.05.02.5 7.5 10.0 12.5 15.0 17.5 22.5 25.0 27.5 30.0

REC

EIVE

R II

P2 (d

Bm

)

TONE1 = 1802MHz, TONE2 = 1892MHzATTENUATOR = SWEPT

RX1 +110°C MAX OF IIP2_SUM_CFRX1 +110°C MAX OF IIP2_DIF_CFRX2 +110°C MAX OF IIP2_SUM_CFRX2 +110°C MAX OF IIP2_DIF_CF

RX1 +25°C MAX OF IIP2_SUM_CFRX1 +25°C MAX OF IIP2_DIF_CFRX2 +25°C MAX OF IIP2_SUM_CFRX2 +25°C MAX OF IIP2_DIF_CFRX1 –40°C MAX OF IIP2_SUM_CFRX1 –40°C MAX OF IIP2_DIF_CFRX2 –40°C MAX OF IIP2_SUM_CFRX2 –40°C MAX OF IIP2_DIF_CF

1683

0-08

8

Figure 67. Receiver IIP2, LO = 1800 MHz, Tones Placed at 1802 MHz and 1892 MHz, −21 dBm Each at Attenuation = 0 dB, IIP2_SUM_CF and IIP2_DIF_CF

Indicate Sum and Difference Products

100

95

90

85

80

75

70

65

60

55

50

807

812

822

827

832

837

842

847

852

857

862

867

872

877

882

887

892

897

902

907

REC

EIVE

R II

P2 (d

Bm

)

TONE1 = 802MHz, TONE2 = SWEPT ACROSS PASSBANDATTENUATOR = 0

RX1 +110°C MAX OF IIP2_SUM_CFRX1 +110°C MAX OF IIP2_DIF_CFRX2 +110°C MAX OF IIP2_SUM_CFRX2 +110°C MAX OF IIP2_DIF_CFRX1 +25°C MAX OF IIP2_SUM_CFRX1 +25°C MAX OF IIP2_DIF_CFRX2 +25°C MAX OF IIP2_SUM_CFRX2 +25°C MAX OF IIP2_DIF_CFRX1 –40°C MAX OF IIP2_SUM_CFRX1 –40°C MAX OF IIP2_DIF_CFRX2 –40°C MAX OF IIP2_SUM_CFRX2 –40°C MAX OF IIP2_DIF_CF

1683

0-08

9

Figure 68. Receiver IIP2 Sum and Difference Across Bandwidth, Receiver

Attenuation = 0 dB, LO = 800 MHz, Tone 1 = 802 MHz, Tone 2 Swept, −21 dBm Each, IIP2_SUM_CF and IIP2_DIF_CF Indicate Sum and Difference

Products

50

55

60

65

70

75

80

85

90

95

100

REC

EIVE

R II

P2SU

MA

ND

DIF

FER

ENC

EA

CR

OSS

BA

ND

WID

TH (d

Bm

)


1807 1817 1827 1837 1847 1857 1867 1877 1887 1897 1907

Rx1 –40°C MAX OF IIP2_SUM_CFRx1 –40°C MAX OF IIP2_DIF_CFRx1 +25°C MAX OF IIP2_SUM_CFRx1 +25°C MAX OF IIP2_DIF_CFRx1 +110°C MAX OF IIP2_SUM_CFRx1 +110°C MAX OF IIP2_DIF_CFRx2 –40°C MAX OF IIP2_SUM_CFRx2 –40°C MAX OF IIP2_DIF_CFRx2 +25°C MAX OF IIP2_SUM_CFRx2 +25°C MAX OF IIP2_DIF_CFRx2 +110°C MAX OF IIP2_SUM_CFRx2 +110°C MAX OF IIP2_DIF_CF

1683

0-33

2

Figure 69. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 1800 MHz, Tone 1 = 1802 MHz, Tone 2 Swept, −21 dBm Each, IIP2_SUM_CF and IIP2_DIF_CF

Indicate Sum and Difference Products

50

55

60

65

70

75

80

85

90

95

100

2907 2917 2927 2937 2947 2957 2967 2977 2987 2997 3007

REC

EIVE

R II

P2SU

M A

ND

DIF

FER

ENC

EA

CR

OSS

BA

ND

WID

TH (d

Bm

)


Rx1 –40°C (SUM)Rx1 –40°C (DIF)Rx1 +25°C (SUM)Rx1 +25°C (DIF)Rx1 +110°C (SUM)Rx1 +110°C (DIF)Rx2 –40°C (SUM)Rx2 –40°C (DIF)Rx2 +110°C (SUM)Rx2 +110°C (DIF)

1683

0-33

3

Figure 70. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 2900 MHz, Tone 1 =

2902 MHz, Tone 2 Swept, −21 dBm Each



Rev. 0 | of 68

0

5

10

15

20

25

30

35

40

45

0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 30.0

REC

EIVE

R II

P3 (d

Bm

)

ATTENUATION (dB)

Rx1 –40°CRx1 +25°CRx1 +110°CRx2 –40°CRx2 +25°CRx2 +110°C

27.5

1683

0-33

4

Figure 71. Receiver IIP3 vs. Attenuation, LO = 1800 MHz, Tone 1 = 1890 MHz, Tone 2 = 1891 MHz, −21 dBm Each at Attenuation = 0 dB

0

5

10

15

20

25

30

805 815 825 835 845 855 865 875 885 895 905 915 925806 816 826 836 846 856 866 876 886 896 906 916 926


REC

EIVE

R II

P3 (d

Bm

)


1683

0-33

5

Figure 72. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =

0 dB, LO = 800 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each, Swept Across Pass Band

0

5

10

15

20

25

30

1805 1815 1825 1835 1845 1855 1865 1875 1885 1895 1905 1915 19251806 1816 1826 1836 1846 1856 1866 1876 1886 1896 1906 1916 1926

REC

EIVE

R II

P3 (d

Bm

)


Rx1 –40°CRx1 +25°CRx1 +110°CRx2 –40°CRx2 +25°C

Rx2 +110°C

1683

0-33

6

Figure 73. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 1800 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each,

Swept Across Pass Band

0

5

10

15

20

25

2905 2915 2925 2935 2945 2955 2965 2975 2985 2995 3005 3015 30252906 2916 2926 2936 2946 2956 2966 2976 2986 2996 3006 3016 3026

REC

EIVE

R II

P3 (d

Bm

)



1683

0-33

7

Figure 74. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =

0 dB, LO = 2900 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each, Swept Across Pass Band

0

10

20

30

40

50

60

0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0

REC

EIVE

R II

P3 (d

Bm

)

ATTENUATION (dB)


1683

0-33

8

Figure 75. Receiver IIP3 vs. Attenuation, LO = 1800 MHz, Tone 1 = 1802 MHz, Tone 2 = 1892 MHz, −21 dBm Each at Attenuation = 0 dB

0

5

10

15

20

25

30

807 817 827 837 847 857 867 877 887 897 907

REC

EIVE

R II

P3 (d

Bm

)



1683

0-33

9

Figure 76. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 800 MHz, Tone 1 = 802 MHz, Tone 2 Swept Across Pass Band,

−21 dBm Each



Rev. 0 | of 68

0

5

10

15

20

25

30

1807 1817 1827 1837 1847 1857 1867 1877 1887 1897 1907

REC

EIVE

R II

P3 (d

Bm

)



1683

0-34

0


−21 dBm Each

0

5

10

15

20

25

30

2907 2917 2927 2937 2947 2957 2967 2977 2987 2997 3007

RECE

IVER

IIP3

(dBm

)


Rx1 –40°CRx1 +25°CRx1 +110°CRx2 –40°CRx2 +110°C

1683

0-34

1


−21 dBm Each

–120

–100

–80

–60

–40

–20

0

–100 –75 –50 –25 0 25 50 75 100

RECE

IVER

IMAG

E (d

Bc)

BASEBAND FREQUENCY OFFSET (Hz)

–40°C+25°C+110°C

1683

0-34

2

Figure 79. Receiver Image vs. Baseband Frequency Offset,

Attenuation = 0 dB, 200 MHz RF Bandwidth, Tracking Calibration Active, Sample Rate = 245.76 MSPS, LO = 650 MHz

–120

–100

–80

–60

–40

–20

0

–100 –75 –50 –25 0 25 50 75 100

REC

EIVE

R IM

AG

E (d

Bc)


–40°C+25°C+110°C

1683

0-34

3

Figure 80. Receiver Image vs. Baseband Frequency Offset,

Attenuation = 0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active, Sample Rate = 245.76 MSPS, LO = 1850 MHz

–120

–100

–80

–60

–40

–20

0

–100 –75 –50 –25 0 25 50 75 100

REC

EIVE

R IM

AG

E (d

Bc)


–40°C+25°C+110°C

1683

0-34

4



–120

–100

–80

–60

–40

–20

0

0 2.5 5.0 7.5 10.0 12.5 15.0

REC

EIVE

R IM

AG

E (d

Bc)


–40°C+25°C+110°C

1683

0-34

5

Figure 82. Receiver Image vs. Attenuator Setting,

RF Bandwidth = 200 MHz, Tracking Calibration Active, Sample Rate = 245.76 MSPS, LO = 1850 MHz



Rev. 0 | of 68

–15

–10

–5

0

5

10

15

20

25

0 5 10 15 20 25 30

REC

EIVE

R G

AIN

(dB

)


–40°C+25°C+110°C

1683

0-34

6

Figure 83. Receiver Gain vs. Receiver Attenuation, RF Bandwidth = 20 MHz, Sample Rate = 245.76 MSPS, LO = 1850 MHz

10

12

14

16

18

20

22

24

650

750

850

950

1050

1150

1250

1350

1450

1550

1650

1750

1850

1950

2050

2150

2250

2350

2450

2550

2650

2750

2850

REC

EIVE

R G

AIN

(dB

)

LO FREQUENCY (MHz)

–40°C+25°C+110°C

1683

0-34

7

Figure 84. Receiver Gain vs. LO Frequency, RF Bandwidth = 20 MHz, Sample

Rate = 245.76 MSPS

–0.5

–0.4

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

0.4

0.5

0 5 10 15 20 25 30

REC

EIVE

R G

AIN

STE

P ER

RO

R (d

B)


–40°C+25°C+110°C

1683

0-34

9

Figure 85. Receiver Gain Step Error vs. Receiver Attenuator Setting over

Temperature

0.10

NORM

ALIZ

ED R

ECEI

VER

BASE

BAND

FLA

TNES

S (d

B)

BASEBAND OFFSET FREQUENCY (MHz)

0.050

–0.05–0.10–0.15–0.20–0.25–0.30–0.35–0.40–0.45–0.50–0.55–0.60–0.65–0.70–0.75–0.80–0.85–0.90–0.95–1.00

1.00

44.

492

7.99

611

.516

15.0

4418

.484

22.0

0425

.492

29.0

1232

.492

36.0

0439

.484

43.0

1246

.484

50.0

1253

.524

57.0

0460

.484

64.0

0467

.516

70.9

9674

.468

78.0

0481

.476

84.9

8888

.492

92.0

1295

.492

98.9

9610

2.48

410

6.00

410

9.46

811

2.91

6

NORMALIZED I RIPPLENORMALIZED I RIPPLENORMALIZED I RIPPLENORMALIZED Q RIPPLENORMALIZED Q RIPPLENORMALIZED Q RIPPLE

1683

0-35

0

Figure 86. Normalized Receiver Baseband Flatness vs. Baseband Offset

Frequency, LO = 2600 MHz

–100

–95

–90

–85

–80

–75

–70

650 850 1050 1250 1450 1650 1850 2050 2250 2450 2650 2850

RECE

IVER

DC

OFF

SET

(dBF

S)


–40°C+25°C+110°C

1683

0-35

1


–100

–95

–90

–85

–80

–75

–70

0 5 10 15 20 25 30

REC

EIVE

R D

C O

FFSE

T (d

BFS

)


–40°C+25°C+110°C

1683

0-35

2




Rev. 0 | of 68

–150

–130

–110

–90

–70

–50

–30

–60 –40 –20 0 20 40 60BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

RECE

IVER

HD2

LEF

T (d

Bc)

ATTN = 15 –40°CATTN = 0 –40°CATTN = 15 +25°CATTN = 0 +25°CATTN = 15 +110°CATTN = 0 +110°C

1683

0-35

3

Figure 89. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB, HD2 Correction Configured for

Low-Side Optimization, X-Axis = Baseband Frequency Offset of Fundamental Tone and Not the Frequency of the HD2 Product (HD2 Product = 2× Baseband

Frequency), LO = 650 MHz

–150

–130

–110

–90

–70

–50

–30

–60 –40 –20 0 20 40 60

REC

EIVE

R H

D2

LEFT

(dB

c)

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

ATTN = 15 –40°CATTN = 0 –40°CATTN = 15 +25°CATTN = 0 +25°CATTN = 15 +110°CATTN = 0 +110°C

1683

0-35

4

Figure 90. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB, HD2 Correction Configured for Low-Side Optimization, X-Axis = Baseband Frequency Offset of the Fundamental Tone and Not the Frequency of the HD2 Product (HD2 Product = 2× the Baseband

Frequency), LO = 1850 MHz –30

–50

–110

–90

–70

–130

–150–60 –40 –20 0 –20 –40 60

RECE

IVER

HD2

LEF

T (d

Bc)

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

ATTN = 15dB, +110°CATTN = 0dB, +110°CATTN = 15dB, +25°CATTN = 0dB, +25°CATTN = 15dB, –40°CATTN = 0dB, –40°C

1683

0-11

2

Figure 91. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB, HD2 Correction Configured for Low-Side Optimization, X-Axis = Baseband Frequency Offset of the Fundamental Tone and Not the Frequency of the HD2 Product (HD2 Product = 2× the Baseband

Frequency), LO = 2850 MHz

–150

–130

–110

–90

–70

–50

–30

–10

10

–50 –40 –30 –20 –10 10 20 30 40 50650

REC

EIVE

R H

D3,

LEF

TA

ND

RIG

HT

(dB

c)


Rx1 –40°C HD3 (LEFT)Rx1 –40°C HD3 (RIGHT)Rx1 +25°C HD3 (LEFT)Rx1 +25°C HD3 (RIGHT)Rx1 +110°C HD3 (LEFT)Rx1 +110°C HD3 (RIGHT)Rx2 –40°C HD3 (LEFT)Rx2 –40°C HD3 (RIGHT)

Rx2 +25°C HD3 (LEFT)Rx2 +25°C HD3 (RIGHT)Rx2 +110°C HD3 (LEFT)Rx2 +110°C HD3 (RIGHT)

1683

0-35

6


Level = −15 dBm at Attenuation = 0 dB, LO = 650 MHz

–150

–130

–110

–90

–70

–50

–30

–10

10

–50 –40 –30 –20 –10 10 20 30 40 501850

REC

EIVE

R H

D3,

LEF

TA

ND

RIG

HT

(dB

c)




1683

0-35

7



–150

–130

–110

–90

–70

–50

–30

–10

10

–50 –40 –30 –20 –10 10 20 30 40 502850

REC

EIVE

R H

D3,

LEF

TA

ND

RIG

HT

(dB

c)




1683

0-35

8





Rev. 0 | of 68

–150

–130

–110

–90

–70

–50

–30

–10

10

0 15 30 10 25 5 20 0 15 30 10 25 5 20 0 15 30 10 25 5 20 0 15 30–50 –40 –30 –20 –10 10 20 30 40 50

1850

RECE

IVER

HD3

, LEF

TAN

D RI

GHT

(dBc

)

UPPER: RECEIVER ATTENUATION (dB)LOWER: FREQUENCY OFFSET FROM LO (MHz)



1683

0-35

9

Figure 95. Receiver HD3, Left and Right vs. Receiver Attenuation and Frequency Offset from LO, Baseband Tone Held Constant, Tone Level Increased 1 for 1 as

Attenuator is Swept from 0 dB to 30 dB, HD3 Right (High Side): Tone on Same Side as HD3 Product; HD3 Left (Low Side): Tone on Opposite Side as HD3 Product,

CW Signal, LO = 1850 MHz, Tone Level = −15 dBm at Attenuation = 0 dB

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

REC

EIVE

R E

VM (d

B)

0

–65 –55 –45 –35 –25 –15 –5 5LTE 20MHz RF INPUT POWER (dBm)

–40°C+25°C+110°C

1683

0-36

0

Figure 96. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF Signal, LO = 600 MHz

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

0

–65 –55 –45 –35 –25 –15 –5 5

REC

EIVE

R E

VM (d

B)


–40°C+25°C+110°C

1683

0-36

1

Figure 97. Receiver EVM vs. LTE 20 MHz RF Input Power,

LTE 20 MHz RF Signal, LO = 1800 MHz

–45

–40

–35

–30

–25

–20

–15

–10

–5

0

–65 –55 –45 –35 –25 –15 –5 5

REC

EIVE

R E

VM (d

B)


–40°C+25°C+110°C

1683

0-36

2

Figure 98. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF Signal, LO = 2700 MHz

0

10

20

30

40

50

60

70

80

90

REC

EIVE

RTO

REC

EIVE

R IS

OLA

TIO

N (d

B)

LO FREQUENCY (MHz)

–40°C+25°C+110°C

650

750

850

950

1050

1150

1250

1350

1450

1550

1650

1750

1850

1950

2050

2150

2250

2350

2450

2550

2650

2750

2850

1683

0-36

3

Figure 99. Receiver to Receiver Isolation (dB) vs. LO Frequency (MHz)

–70

–80

–90

–100

–110

LO P

HA

SE N

OIS

E (d

B)

–120

–130

–140

–150

–160

–170

FREQUENCY OFFSET (Hz)100M100 1k 10k 100k 1M 10M

1683

0-36

4

Figure 100. LO Phase Noise vs. Frequency Offset, LO = 1900 MHz, Spectrum

Analyzer Limits Far Out Noise



Rev. 0 | of 68


–2.0

–0.8

–0.4

–0.6

–0.2

–1.2

–1.8

–1.4

–1.6

–1.0

REC

EIVE

R O

FF C

HIP

MA

TCH

ING

CIR

CU

IT P

ATH

LO

SS (d

B)

LO FREQUENCY (MHz)3400 4200 50003800 46004000 48003600 4400

1683

0-80

3

Figure 101. Receiver Off Chip Matching Circuit Path Loss vs. LO Frequency

(Simulation), Can Be Used for De-Embedding Performance Data

0

–10

–100

–50

–70

–30

–20

–60

–90

–80

–40

RECE

IVER

LO

LEA

KAG

E (d

Bm)

RECEIVER LO FREQUENCY (MHz)3600 4600

+110°C+25°C–40°C

1683

0-80

4

Figure 102. Receiver LO Leakage from 3600 MHz to 4600 MHz, 0 dB Receiver

Attenuation, 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate

45

40

0

20

30

35

10

5

15

25

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

RECEIVER ATTENUATION (dB)0 2018161412108642

+110°C+25°C–40°C

1683

0-80

5

Figure 103. Receiver Noise Figure vs. Receiver Attenuation,

LO = 3600 MHz, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS, Integration Bandwidth = 500 kHz to 100 MHz

45

40

0

20

30

35

10

5

15

25

REC

EIVE

R N

OIS

E FI

GU

RE

(dB

)

RECEIVER ATTENUATION (dB)0 2018161412108642

+110°C+25°C–40°C

1683

0-80

6

Figure 104. Receiver Noise Figure vs. Receiver Attenuation, LO = 4600 MHz, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS,


REC

EIVE

R II

P2 (d

Bm

)


IIP2 SUM +110°CIIP2 SUM +25°CIIP2 SUM –40°CIIP2 DIFF +110°CIIP2 DIFF +25°CIIP2 DIFF –40°C

120

50

80

100

60

110

70

90

0 282624222018161412108642 30

1683

0-80

7


Placed at 3645 MHz and 3646 MHz, −21 dBm Plus Attenuation

REC

EIVE

R II

P2 (d

Bm

)



110

50

80

100

60

70

90

0 282624222018161412108642 30

1683

0-80

8





Rev. 0 | of 68

REC

EIVE

R II

P2 S

UM

AN

D D

IFFE

REN

CE

AC

RO

SSB

AN

DW

IDTH

(dB

m)


80

40

55

75

45

50

65

70

60

36063605

36863685

36663665

36463645

36263625

37063705

SWEPT PASS BAND FREQUENCY (MHz) 1683

0-80

9

Figure 107. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept

Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 3600 MHz, Six Tone Pairs, −21 dBm Plus Attenuation Each

REC

EIVE

R II

P2 S

UM

AN

D D

IFFE

REN

CE

AC

RO

SSB

AN

DW

IDTH

(dB

m)


80

40

55

75

45

50

65

70

60

46064605

46864685

46664665

46464645

46264625

47064705


0-81

0


Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 4600 MHz, Six Tone Pairs, −21 dBm Each

REC

EIVE

R II

P2 (d

Bm

)

100

80

50

55

75

90

85

95

65

70

60

0 2015105 3025RECEIVER ATTENUATION

+110°C = Rx1 (DIFF)+110°C = Rx1 (SUM)+25°C = Rx1 (DIFF)+25°C = Rx1 (SUM)–40°C = Rx1 (DIFF)–40°C = Rx1 (SUM)


1683

0-81

1

Figure 109. Receiver IIP2 vs. Receiver Attenuation, LO = 3600 MHz, Tone 1 = 4602 MHz and Tone 2 = 4692 MHz, −21 dBm Plus Attenuation

REC

EIVE

R II

P2 (d

Bm

)

100

80

50

55

75

90

85

95

65

70

60

0 2015105 3025RECEIVER ATTENUATION



1683

0-81

2

Figure 110. Receiver IIP2 vs. Receiver Attenuation, LO = 4600 MHz, Tones Placed at 4602 MHz and 4692 MHz, −21 dBm Plus Attenuation

REC

EIVE

R II

P2 S

UM

AN

D D

IFFE

REN

CE

AC

RO

SSB

AN

DW

IDTH

(dB

m)

100

80

50

55

75

90

85

95

65

70

60

3612 3692367236523632 3682366236423622 37123702SWEPT PASS BAND FREQUENCY (MHz)



1683

0-81

3

Figure 111. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 3600 MHz,

Tone 1 = 3602 MHz, Tone 2 Swept, −21 dBm Each

100

70

75

80

85

90

95

65

60

55

50

404612 4622 4632 4642 4652 4662 4672 4682 4692 4702 4712

REC

EIVE

R II

P2 S

UM

AN

D D

IFFE

REN

CE

AC

RO

SSB

AN

DW

IDTH

(dB

m)


Rx2 +25°C IIP2_SUM_CFRx2 +25°C IIP2_DIF_CFRx1 –40°C IIP2_SUM_CFRx1 –40°C IIP2_DIF_CFRx2 –40°C IIP2_SUM_CFRx2 –40°C IIP2_DIF_CF

Rx1 +110°C IIP2_SUM_CFRx1 +110°C IIP2_DIF_CFRx2 +110°C IIP2_SUM_CFRx2 +110°C IIP2_DIF_CFRx1 +25°C IIP2_SUM_CFRx1 +25°C IIP2_DIF_CF

1683

0-19

3


Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 4600 MHz, Tone 1 = 4602 MHz, Tone 2 Swept, −21 dBm Each, IIP2_SUM_CF and

IIP2_DIF_CF Indicate Sum and Difference Products

Tone2



Rev. 0 | of 68

REC

EIVE

R II

P3 (d

Bm

)

45

30

0

5

25

40

35

15

20

10

0 2015105 3025ATTENUATION (dB)


1683

0-81

4


REC

EIVE

R II

P3 (d

Bm

)

45

30

0

5

25

40

35

15

20

10

0 2015105 3025TONE 1 = 4695MHz TONE 2 = 4696MHzRECEIVER ATTENUATION SWEPT (dB)


1683

0-81

5

Figure 114. Receiver IIP3 vs. Receiver Attenuation Swept, LO = 4600 MHz,

Tone 1 = 4695 MHz, Tone 2 = 4696 MHz, −21 dBm Plus Attenuation

REC

EIVE

R II

P3 A

CR

OSS

BA

ND

WIT

H (d

Bm

)

30

0

5

25

15

20

10 Rx1 = +110°CRx1 = +25°CRx1 = –40°CRx2 = +110°CRx2 = +25°CRx2 = –40°C

36053606

36853686

36653666


36453646

36253626

37053706

1683

0-81

6

Figure 115. Receiver IIP3 Across Bandwidth, Receiver Attenuation = 0 dB, LO =

3600 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each, Swept Across Pass Band

REC

EIVE

R II

P3 (d

Bm

)

30

0

5

25

15

20

10 Rx1 = +110°CRx1 = +25°CRx1 = –40°CRx2 = +110°CRx2 = +25°CRx2 = –40°C

46054606

46854686

46654666

46454646

46254626

47054706

RECEIVER ATTENUATION (dB) 1683

0-81

7

Figure 116. Receiver IIP3 vs. Receiver Attenuation, Receiver Attenuation = 0 dB,

LO = 4600 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each, Swept Across Pass Band

50

45

40

0

20

30

35

10

5

15

25

RECE

IVER

IIP3

(dBm

)

0 30252015


105


1683

0-81

8

Figure 117. Receiver IIP3 vs. Receiver Attenuation, LO = 3600 MHz, Tone 1 = 3602 MHz, Tone 2 = 3692 MHz, −21 dBm Plus Attenuation

50

50

40

0

20

30

10

RECE

IVER

IIP3

(dBm

)

0 30252015


105


1683

0-81

9




Rev. 0 | of 68

REC

EIVE

R II

P3 A

CR

OSS

BA

ND

WID

TH (d

Bm

)

35

30

0

5

25

15

20

10Rx1 = +110°CRx1 = +25°CRx1 = –40°CRx2 = +110°CRx2 = +25°CRx2 = –40°C

3612 3692367236523632 3712


0-82

0

Figure 119. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 3600 MHz, Tone 1 = 3602 MHz, Tone 2 Swept

Across Pass Band, −21 dBm Each

REC

EIVE

R II

P3 A

CR

OSS

BA

ND

WID

TH (d

Bm

)

35

30

0

5

25

15

20

10Rx1 = +110°CRx1 = +25°CRx1 = –40°CRx2 = +110°CRx2 = +25°CRx2 = –40°C

4612 4692467246524632 4712SWEPT PASS BAND FREQUENCY (MHz) 16

830-

821

Figure 120. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 4600 MHz,

Tone 1 = 4602 MHz, Tone 2 Swept Across Pass Band, −21 dBm Each

0

–120

–100

–80

–60

–40

–20

REC

EIVE

R IM

AG

E (d

Bc)

+110°C+25°C–40°C

BASEBAND FREQUENCY OFFSET (MHz)–100 –75 0–25–50 25 75 10050

1683

0-82

2



0

–100

–80

–60

–40

–20

REC

EIVE

R IM

AG

E (d

Bc)

BASEBAND FREQUENCY OFFSET (MHz)

+110°C+25°C–40°C

–100 –75 0–25–50 25 75 10050–120

1683

0-82

3

Figure 122. Receiver Image vs. Baseband Frequency Offset, Attenuation =

0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active, Sample Rate = 245.76 MSPS, LO = 4600 MHz

0

–120

–100

–80

–60

–40

–20

0 105 15 25 3020

REC

EIVE

R IM

AG

E (d

Bc)


+110°C+25°C–40°C

1683

0-82

4

Figure 123. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz,

Tracking Calibration Active, Sample Rate = 245.76 MSPS, LO = 3600 MHz, Baseband Frequency= 10 MHz

0

–120

–100

–80

–60

–40

–20

0 105 15 25 3020

REC

EIVE

R IM

AG

E (d

Bc)


+110°C+25°C–40°C

1683

0-82

5


Tracking Calibration Active, Sample Rate = 245.76 MSPS, LO = 4600 MHz, Baseband Frequency = 10 MHz



Rev. 0 | of 68

25

–15

–10

–5

0

5

15

10

20

0 105 15 25 3020

REC

EIVE

R G

AIN

(dB

c)


+110°C+25°C–40°C

1683

0-82

6

Figure 125. Receiver Gain vs. Receiver Attenuation, RF Bandwidth = 20 MHz,


25

–15

–10

–5

0

5

15

10

20

0 105 15 25 3020

REC

EIVE

R G

AIN

(dB

c)


+110°C+25°C–40°C

1683

0-82

7

Figure 126. Receiver Gain vs. Receiver Attenuation, RF Bandwidth = 20 MHz,


24

10

12

14

16

18

22

20

3400

3800

3600

4000

4600

4800

4200

3700

3500

3900

4400

4500

4700

4300

4100

RECE

IVER

GAI

N (d

Bc)

LO FREQUENCY (MHz)

+110°C+25°C–40°C

1683

0-82

8

Figure 127. Receiver Gain vs. LO Frequency, RF Bandwidth = 200 MHz,

Sample Rate = 245.76 MSPS

0 105 15 25 3020

REC

EIVE

R G

AIN

STE

P ER

RO

R (d

B)


+110°C+25°C–40°C

0.5

0.4

–0.5

0

–0.4

–0.2

0.2

0.3

–0.1

–0.3

0.1

1683

0-82

9


LO = 3600 MHz

0 105 15 25 3020

REC

EIVE

R G

AIN

STE

P ER

RO

R (d

B)


+110°C+25°C–40°C

0.5

0.4

–0.5

0

–0.4

–0.2

0.2

0.3

–0.1

–0.3

0.1

1683

0-83

0


LO = 4600 MHz

–50

–110

–100

–80

–60

–90

–70

REC

EIVE

R D

C O

FFSE

T (d

BFS

)

RECEIVER LO FREQUENCY (MHz)3400 4200 48003800 460040003600 4400

+110°C+25°C–40°C

1683

0-83

1




Rev. 0 | of 68

–70

–110

–105

–95

–75

–100

–85

–80

–90

REC

EIVE

R D

C O

FFSE

T (d

BFS

)

RECEIVER ATTENUATOR SETTING (dB)0 20 3010 155 25

+110°C+25°C–40°C

1683

0-83

2


–70

–110

–105

–95

–75

–100

–85

–80

–90

REC

EIVE

R D

C O

FFSE

T (d

BFS

)

RECEIVER ATTENUATOR SETTING (dB)0 20 3010 155 25

+110°C+25°C–40°C

1683

0-83

3


–30

–150

–130

–90

–40

–110

–60

–50

–70

–140

–100

–120

–80

REC

EIVE

R H

D2,

LEF

T (d

Bc)

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)–60 20 60–20 0–40 40


1683

0-83

4

Figure 133. Receiver HD2, Left vs. Baseband Frequency Offset and Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB, X-Axis =

Baseband Frequency Offset of the Fundamental Tone Not the Frequency of the HD2 Product (HD2 Product = 2× the Baseband Frequency), HD2

Canceller Disabled, LO = 3600 MHz

–30

–150

–130

–90

–40

–110

–60

–50

–70

–140

–100

–120

–80

REC

EIVE

R H

D2,

LEF

T (d

Bc)

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)–60 20 60–20 0–40 40


1683

0-83

5

Figure 134. Receiver HD2, Left vs. Baseband Frequency Offset and Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB, X-Axis =

Baseband Frequency Offset of the Fundamental Tone, Not the Frequency of the HD2 Product (HD2 Product = 2× the Baseband Frequency), HD2

Canceller Disabled, LO = 4600 MHz

10

–150

–130

–90

–10

–110

–50

–30

–70

REC

EIVE

R H

D3,

LEF

T A

ND

RIG

HT

(dB

c)


–50 103600

50–30 –20–40 3020–10 40

Rx2 = +110°C (RIGHT)Rx2 = +110°C (LEFT)Rx2 = +25°C (RIGHT)Rx2 = +25°C (LEFT)Rx2 = –40°C (RIGHT)Rx2 = –40°C (LEFT)


1683

0-83

6



10

–150

–130

–90

–10

–110

–50

–30

–70

REC

EIVE

R H

D3,

LEF

T A

ND

RIG

HT

(dB

c)

FREQUENCY OFFSET FROM LO AND ATTENUATION (MHz)

–50 104600

50–30 –20–40 3020–10 40



1683

0-83

7

Figure 136. Receiver HD3, Left and Right vs. Frequency Offset from LO and

Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB, LO = 4600 MHz



Rev. 0 | of 68

0

–50

–45

–25

–5

–35

–15

–30

–10

–40

–20

RECE

IVER

EVM

(dB)

LTE 20MHz RF INPUT POWER (dBm)–65 –25 5–45 –5–35–55 –15

+110°C+25°C–40°C

1683

0-83

8

Figure 137. Receiver EVM vs. LTE 20 MHz RF Input Power, RF Signal = LTE 20 MHz, LO = 3600 MHz, Default AGC Settings

0

–45

–25

–5

–35

–15

–30

–10

–40

–20

RECE

IVER

EVM

(dB)

LTE 20MHz RF INPUT POWER (dBm)–65 –25 5–45 –5–35–55 –15

+110°C+25°C–40°C

1683

0-83

9

Figure 138. Receiver EVM vs. LTE 20 MHz RF Input Power,

RF Signal = LTE 20 MHz, LO = 4600 MHz, Default AGC Settings

0

90

50

10

70

30

60

20

80

40

REC

EIVE

R T

O R

ECEI

VER

ISO

LATI

ON

(dB

)

LO FREQUENCY (MHz)

3400

4200

4800

3800

4600

4000

3600

4400

4100

4700

3700

4500

3900

3500

4300

Rx1 TO Rx2 ISOLATIONRx2 TO Rx1 ISOLATION

1683

0-84

0

Figure 139. Receiver to Receiver Isolation vs. LO Frequency

–70

–170

–130

–80

–160

–150

–110

–100

–140

–90

–120

LO P

HASE

NO

ISE

(dB)

FREQUENCY OFFSET (Hz)100 1M 100M10k 100k1k 10M

1683

0-84

1


Bandwidth = 300 kHz, Spectrum Analyzer Limits Far Out Noise



Rev. 0 | of 68


–2.00

–0.80

–0.40

–0.60

–0.20

–1.20

–1.80

–1.40

–1.60

–1.00

REC

EIVE

R O

FF C

HIP

MA

TCH

ING

CIR

CU

IT P

ATH

LO

SS (d

B)

LO FREQUENCY (MHz)5000 5800 60005400 56005200

1683

0-89

9

Figure 141. Receiver Off Chip Matching Circuit Path Loss vs. LO Frequency

(Simulation), Can Be Used for De-Embedding Performance Data

0

–100

–40

–20

–30

–10

–60

–90

–70

–80

–50

REC

EIVE

R L

O L

EAK

AG

E (d

Bm

)

RECEIVER LO FREQUENCY (MHz)5200 5700 58005400 560055005300

+110°C+25°C–40°C

1683

0-90

0

Figure 142. Receiver LO Leakage vs. Receiver LO Frequency, 5200 MHz,

5500 MHz, and 5800 MHz, Receiver Attenuation = 0 dB, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS

110

50

70

90

80

100

60

REC

EIVE

R II

P2 (d

Bm

)

ATTENUATION (dB)0 28 3010 22164 268 20142 246 1812


1683

0-90

1

Figure 143. Receiver IIP2 vs. Attenuation, LO = 5800 MHz, Tones Placed at

5845 MHz and 5846 MHz, −21 dBm Plus Attenuation

80

40

50

65

55

75

60

70

45

REC

EIVE

R II

P2 S

UM

AN

D D

IFFE

REN

CE

AC

RO

SSB

AN

DW

IDTH

(dB

m)

58055806

58855886

59055906

58255826

58655866

58455846



1683

0-90

2


Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 5800 MHz, Six Tone Pairs, −21 dBm Plus Attenuation Each

110

50

70

90

80

100

60

REC

EIVE

R II

P2 (d

Bm

)

RECEIVER ATTENUATION0 25 3010 205 15

Rx1 IIP2 DIFF +110°CRx1 IIP2 SUM +110°CRx1 IIP2 DIFF +25°CRx1 IIP2 SUM +25°CRx1 IIP2 DIFF –40°CRx1 IIP2 SUM –40°C


1683

0-90

3



80

40

60

70

65

75

50

55

45

REC

EIVE

R II

P2 S

UM

AN

D D

IFFE

REN

CE

AC

RO

SSB

AN

DW

IDTH

(dB

m)


58025802

58325802

58425802

58125802

58225802

58525802

58825802

58925802

59025802

58625802

58725802



1683

0-90

4

Figure 146. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 5800 MHz,

Tone 1 = 5802 MHz, Tone 2 Swept, −21 dBm Each



Rev. 0 | of 68

45

0

25

35

30

40

15

20

5

10

RECE

IVER

IIP3

(dBm

)

RECEIVER ATTENUATION (dB)0 15 205 10 25 30


1683

0-90

5


30

0

10

20

15

25

5

REC

EIVE

R II

P3 (d

Bm

)


58055806

58355836

58455846

58155816

58255826

58555856

58885886

58955896

59155916

59055906

58655866

58755876


1683

0-90

6

Figure 148. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver

Attenuation = 0 dB, LO = 5800 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each, Swept Across Pass Band

60

0

20

40

30

50

10

RECE

IVER

IIP3

(dBm

)

RECEIVER ATTENUATION (dB)0 15 205 10 25 30


1683

0-90

7


30

0

10

20

15

25

5

REC

EIVE

R II

P3 A

CR

OSS

BA

ND

WID

TH (d

Bm

)


58025812

58025842

58025852

58025822

58025832

58025862

58025892

58025902

58025922

58025912

58025872

58025882


1683

0-90

8

Figure 150. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency,

Receiver Attenuation = 0 dB, LO = 5800 MHz, Tone 1 = 5802 MHz, Tone 2 Swept Across Pass Band, −21 dBm Each

–10

–110

–100

–80

–60

–40

–20

–90

–70

–50

–30

REC

EIVE

R IM

AG

E (d

Bc)

+110°C+25°C–40°C


1683

0-90

9



–10

–110

–100

–80

–60

–40

–20

–90

–70

–50

–30

REC

EIVE

R IM

AG

E (d

Bc)

+110°C+25°C–40°C


1683

0-91

0





Rev. 0 | of 68

0

–120

–100

–60

–20

–80

–40

REC

EIVE

R IM

AG

E (d

Bc)

+110°C+25°C–40°C

ATTENUATOR SETTING (dB)0 10 152 25 3020

1683

0-91

1


Tracking Calibration Active, Sample Rate = 245.76 MSPS, LO = 5200 MHz, Baseband Frequency = 10 MHz

0

–120

–100

–60

–20

–80

–40

REC

EIVE

R IM

AG

E (d

Bc)

+110°C+25°C–40°C

ATTENUATOR SETTING (dB)0 10 152 25 3020

1683

0-91

2


Tracking Calibration Active, Sample Rate = 245.76 MSPS, LO = 5900MHz, Baseband Frequency = 10 MHz

0.5

–0.5

–0.4

0

0.4

–0.2

0.2

–0.1

0.3

–0.3

0.1

REC

EIVE

R G

AIN

STE

P ER

RO

R (d

Bc)

+110°C+25°C–40°C

RECEIVER ATTENUATOR SETTING AND TEMPERATURE (dB)0 10 152 25 3020

1683

0-91

3

Figure 155. Receiver Gain Step Error vs. Receiver Attenuator Setting and Temperature, LO = 5200 MHz

0.5

–0.5

–0.4

0

0.4

–0.2

0.2

–0.1

0.3

–0.3

0.1

REC

EIVE

R G

AIN

STE

P ER

RO

R (d

Bc)

+110°C+25°C–40°C


1683

0-91

4

Figure 156. Receiver Gain Step Error vs. Receiver Attenuator Setting and

Temperature, LO = 5600 MHz

0.5

–0.5

–0.4

0

0.4

–0.2

0.2

–0.1

0.3

–0.3

0.1

REC

EIVE

R G

AIN

STE

P ER

RO

R (d

Bc)

+110°C+25°C–40°C


1683

0-91

5

Figure 157. Receiver Gain Step Error vs. Receiver Attenuator Setting and

Temperature, LO = 6000 MHz

0.50.40.30.20.1

0–0.1–0.2–0.3–0.4

–1.0

–0.5–0.6–0.7–0.8–0.9

0.99

4.50

28.

002

11.4

9814

.998

18.5

1422

.006

25.5

1429

.006

32.4

9835

.978

39.5

0242

.998

46.5

0249

.978

53.5

1856

.998

60.5

0664

.006

67.5

0271

.014

74.5

0677

.986

81.5

0284

.998

88.4

9891

.978

95.4

8698

.998

102.

514

105.

998

109.

502

113.

002

NO

RM

ALI

ZED

REC

EIVE

RB

ASE

BA

ND

FLA

TNES

S (d

B)

BASEBAND FREQUENCY (MHz)

MAX OF NORMALIZED I RIPPLE –40°CMAX OF NORMALIZED I RIPPLE +25°CMAX OF NORMALIZED I RIPPLE +110°CMAX OF NORMALIZED Q RIPPLE –40°CMAX OF NORMALIZED Q RIPPLE +25°CMAX OF NORMALIZED Q RIPPLE +110°C

1683

0-29

9

Figure 158. Normalized Receiver Baseband Flatness vs. Baseband Frequency

(Receiver Flatness)



Rev. 0 | of 68

–30

–150

–140

–100

–80

–120

–130

–110

–50

–40

–70

–90

–60

REC

EIVE

R H

D2

LEFT

(dB

c)

BASEBAND FREQUENCY OFFSET (MHz)–60 –20 0–40 40 6020


1683

0-91

6

Figure 159. Receiver HD2 Left vs. Baseband Frequency Offset, Tone Level = −15 dBm at Attenuation = 0 dB, X-Axis = Baseband Frequency Offset of the

Fundamental Tone Not the Frequency of the HD2 Product (HD2 Product = 2× the Baseband Frequency), HD2 Canceller Disabled,

LO = 5200 MHz

–30

–150

–140

–100

–80

–120

–130

–110

–50

–40

–70

–90

–60

REC

EIVE

R H

D2

LEFT

(dB

c)

BASEBAND FREQUENCY OFFSET (MHz)–60 –20 0–40 40 6020


1683

0-91

7

Figure 160. Receiver HD2 Left vs. Baseband Frequency Offset, Tone Level =

−15 dBm at Attenuation = 0 dB, X-Axis = Baseband Frequency Offset of the Fundamental Tone Not the Frequency of the HD2 Product (HD2 Product = 2×

the Baseband Frequency), HD2 Canceller Disabled, LO = 5900 MHz

–10

–150

–110

–50

–30

–90

–130

–70

REC

EIVE

R H

D3,

LEF

T A

ND

RIG

HT

(dB

c)


–50 –30 –10–20 10–40 30 40 505200

20

Rx2 = +110°C (RIGHT)Rx1 = +110°C (RIGHT)Rx2 = +25°C (RIGHT)Rx1 = +25°C (RIGHT)Rx2 = –40°C (RIGHT)Rx1 = –40°C (RIGHT)

Rx2 = +110°C (LEFT)Rx1 = +110°C (LEFT)Rx2 = +25°C (LEFT)Rx1 = +25°C (LEFT)Rx2 = –40°C (LEFT)Rx1 = –40°C (LEFT)

1683

0-91

8



–10

–150

–110

–50

–30

–90

–130

–70

REC

EIVE

R H

D3,

LEF

T A

ND

RIG

HT

(dB

c)


–50 –30 –10–20 10–40 30 40 505900

20

Rx2 = +110°C (RIGHT)Rx1 = +110°C (RIGHT)Rx2 = +25°C (RIGHT)Rx1 = +25°C (RIGHT)Rx2 = –40°C (RIGHT)Rx1 = –40°C (RIGHT)

Rx2 = +110°C (LEFT)Rx1 = +110°C (LEFT)Rx2 = +25°C (LEFT)Rx1 = +25°C (LEFT)Rx2 = –40°C (LEFT)Rx1 = –40°C (LEFT)

1683

0-91

9



0

–45

–40

–30

–25

–35

–20

–10

–5

–15

REC

EIVE

R E

VM (d

B)

+110°C+25°C–40°C

LTE 20MHz RF INPUT POWER (dBm)–65 –45 –35–55 –15 –5 5–25

1683

0-92

0

Figure 163. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF

Signal, LO = 5200 MHz, Default AGC Settings

0

–45

–40

–30

–25

–35

–20

–10

–5

–15

REC

EIVE

R E

VM (d

B)

+110°C+25°C–40°C


1683

0-92

1




Rev. 0 | of 68

0

–45

–40

–30

–25

–35

–20

–10

–5

–15

REC

EIVE

R E

VM (d

B)

+110°C+25°C–40°C


1683

0-92

2

Figure 165. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF

Signal, LO = 5800 MHz, Default AGC Settings

0

100

90

50

10

70

30

60

20

80

40

REC

EIVE

R T

O R

ECEI

VER

ISO

LATI

ON

(dB

)

LO FREQUENCY (MHz)5000 5800 60005400 56005200 57005300 55005100 5900

Rx1 TO Rx2Rx2 TO Rx1

1683

0-92

3

Figure 166. Receiver to Receiver Isolation vs. LO Frequency

–20

–180

–120

–40

–160

–80

–140

–60

–100

LO P

HASE

NO

ISE

(dB)

FREQUENCY OFFSET (Hz)100 1M 100M10k 100k1k 10M

1683

0-92

4


Bandwidth > 300 kHz, Spectrum Analyzer Limits Far Out Noise



Rev. 0 | of 68

RECEIVER INPUT IMPEDANCE

M15FREQUENCY = 100.0MHzS (1,1) = 0.390 / –1.819IMPEDANCE = 113.933 – j3.331

RX PORT SIMULATED IMPEDANCE: SEDZ

FREQUENCY (0Hz TO 6.000GHz)

S (1

,1)



M18FREQUENCY = 1.000GHzS (1,1) = 0.377 / –18.643IMPEDANCE = 100.377 – j28.250





M23FREQUENCY = 6.000GHzS (1,1) = 0.266 / 130.063IMPEDANCE = 32.890 + j14.399

M23

M22

M21M20 M19

M15M16M17M18

1683

0-00

4

Figure 168. Receiver Input Impedance, Series Equivalent Differential Impedance (SEDZ)



Rev. 0 | of 68

TERMINOLOGY Large Signal Bandwidth Large signal bandwidth, otherwise known as instantaneous bandwidth or signal bandwidth, is the bandwidth over which there are large signals. For example, for Band 42 LTE, the large signal bandwidth is 200 MHz.

Occupied Bandwidth Occupied bandwidth is the total bandwidth of the active signals. For example, three 20 MHz carriers have a 60 MHz occupied bandwidth, regardless of the placement of the carriers within the large signal bandwidth.

Backoff Backoff is the difference (in dB) between full-scale signal power and the rms signal power.

PHIGH PHIGH is the largest signal that can be applied without overloading the ADC for the receiver input. This input level results in slightly less than full scale at the digital output because of the nature of the continuous-time, Σ-Δ ADCs, which, for example, exhibit a soft overload in contrast to the hard clipping of pipeline ADCs.



Rev. 0 | of 68

THEORY OF OPERATION The ADRV9008-1 is a highly integrated, RF, agile receiver subsystem capable of configuration for a wide range of applications. The device integrates all RF, mixed-signal, and digital blocks necessary to provide all receiver functions in a single device. Programmability allows the receiver to be adapted for use in many TDD and 3G/4G/5G cellular standards. The ADRV9008-1 contains two high speed links each for the receiver chain. These links are JESD204B, Subclass 1 compliant.

The ADRV9008-1 also provides tracking correction of dc offset QEC errors to maintain high performance under varying temp-eratures and input signal conditions. The device also includes test modes that allow system designers to debug designs during prototyping and optimize radio configurations.

RECEIVERS The ADRV9008-1 receivers contain all the blocks necessary to receive RF signals and convert them to digital data used by a BBP. Each receiver can be configured as a direct conversion system that supports up to a 200 MHz bandwidth. Each receiver contains a programmable attenuator stage and matched I and Q mixers that downconvert received signals to baseband for digitization.

Achieve gain control by using the on-chip AGC or by allowing the BBP to make gain adjustments in a manual gain control mode. Optimize performance by mapping each gain control setting to specific attenuation levels at each adjustable gain block in the receiver signal path. Additionally, each channel contains independent receive signal strength indicator (RSSI) measurement capability, dc offset tracking, and all circuitry necessary for self calibration.

The receivers include ADCs and adjustable sample rates that produce data streams from the received signals. The signals can be conditioned further by a series of decimation filters and a programmable FIR filter with additional decimation settings. The sample rate of each digital filter block is adjustable by changing decimation factors to produce the desired output data rate.

CLOCK INPUT The ADRV9008-1 requires a differential clock connected to the REF_CLK_IN_x pins. The frequency of the clock input must be between 10 MHz and 1000 MHz, and the frequency must have low phase noise because this signal generates the RF LO and internal sampling clocks.

SYNTHESIZERS RF PLL

The ADRV9008-1 contains a fractional-N PLL to generate the RF LO for the signal paths. The PLL incorporates an internal VCO and loop filter, requiring no external components. The LOs on multiple chips can be phase synchronized to support active antenna systems and beam forming applications.

Clock PLL

The ADRV9008-1 contains a PLL synthesizer that generates all the baseband related clock signals and serialization/ deserialization (SERDES) clocks. This PLL is programmed based on the data rate and sample rate requirements of the system.

SPI The ADRV9008-1 uses an SPI interface to communicate with the BBP. This interface can be configured as a 4-wire interface with a dedicated receiver port and transmitter port. The interface can also be configured as a 3-wire interface with a bidirectional data communications port. This bus allows the BBP to set all device control parameters using a simple address data serial bus protocol.

Write commands follow a 24-bit format. The first five bits set the bus direction and the number of bytes to transfer. The next 11 bits set the address where the data is written. The final eight bits are the data transferred to the specific register address.

Read commands follow a similar format with the exception that the first 16 bits are transferred on the SDIO pin and the final eight bits are read from the ADRV9008-1, either on the SDO pin in 4-wire mode or on the SDIO pin in 3-wire mode.

JTAG BOUNDARY SCAN The ADRV9008-1 provides support for the JTAG boundary scan. There are five dual-function pins associated with the JTAG interface. These pins, listed in Figure 5, are used to access the on-chip test access port. To enable the JTAG functionality, set the GPIO_3 pin through the GPIO_0 pin to 1001 and pull the TEST pin high.

POWER SUPPLY SEQUENCE The ADRV9008-1 requires a specific power-up sequence to avoid undesired power-up currents. In the optimal power-up sequence, the VDDD1P3_DIG supply and the VDDA1P3_x supply (VDDA1P3_x includes all 1.3 V domains) power up together first. If these supplies cannot be powered up simultaneously, then the VDDD1P3_DIG supply must power up first. Power up the VDDA_3P3 supply, the VDDA1P8_x supply, and the VDDA1P3_SER supply after powering up the 1.3 V supplies. The VDD_INTERFACE supply can be powered up at any time. No device damage occurs if this sequence is not followed, but failing to follow this sequence may result in higher than expected power-up currents. Toggle the RESET signal after the power stabilizes, prior to configuration. The power-down sequence is not critical. If a power-down sequence is followed, remove the VDDD1P3_DIG supply last to avoid any back biasing of the digital control lines.



Rev. 0 | of 68

GPIO_x PINS The ADRV9008-1 provides nineteen 1.8 V to 2.5 V GPIO signals that can be configured for numerous functions. When configured as outputs, certain pins can provide real-time signal information to the BBP, allowing the BBP to determine receiver performance. A pointer register selects the information that is output to these pins. Signals used for manual gain mode, calibration flags, state machine states, and various receiver parameters are among the outputs that can be monitored on these pins. Additionally, certain pins can be configured as inputs and used for various functions, such as setting the receiver gain in real time.

Twelve 3.3 V GPIO_x pins are also included on the device. These pins provide control signals to external components.

AUXILIARY CONVERTERS AUXADC_x

The ADRV9008-1 contains an auxiliary ADC that is multiplexed to four input pins (AUXADC_x). The auxiliary ADC is 12 bits with an input voltage range of 0.05 V to VDDA_3P3 − 0.05 V. When

enabled, the auxiliary ADC is free running. The SPI reads provide the last value latched at the ADC output. The auxiliary ADC can also be multiplexed to a built in, diode-based temperature sensor.

Auxiliary DAC x

The ADRV9008-1 contains 10 identical auxiliary DACs that can be used for bias or other system functionality. The auxiliary DACs are 10 bits, have an output voltage range of approximately 0.7 V to VDDA_3P3 − 0.3 V, and have a current drive of 10 mA.

JESD204B DATA INTERFACE The digital data interface for the ADRV9008-1 uses JEDEC JESD204B Subclass 1. The serial interface operates at speeds of up to 12.288 Gbps. The benefits of the JESD204B interface include a reduction in required board area for data interface routing, resulting in smaller total system size. Four high speed serial lanes are provided for the receiver. The ADRV9008-1 supports single-lane and dual-lane interfaces and supports fixed and floating point data formats for receiver.

Table 6. Example Receiver Interface Rates (Other Output Rates, Bandwidths, and JESD204B Lanes Also Supported)

Bandwidth (MHz) Output Rate (MSPS)

Single-Channel Operation Dual-Channel Operation JESD204B Lane Rate (Mbps)

JESD204B Number of Lanes

JESD204B Lane Rate (Mbps)

JESD204B Number of Lanes

80 122.88 4915.2 1 9830.4 1 100 153.6 6144 1 12288 1 100 245.76 9830.4 1 9830.4 2 200 245.76 9830.4 1 9830.4 2 200 245.76 4915.2 2 4915.2 4

RECEIVEHALF-BAND

FILTER3

ADCRECEIVE

HALF-BANDFILTER

2

RECEIVEHALF-BAND

FILTER1

FIRFILTER

(DECIMATION1, 2, 4)

DCESTIMATION

DIGITALGAIN JESD204B

1683

0-31

0

Figure 169. Receiver Datapath Filter Implementation



Rev. 0 | of 68

APPLICATIONS INFORMATION PCB LAYOUT AND POWER SUPPLY RECOMMENDATIONS Overview

The ADRV9008-1 is a highly integrated, RF, agile receiver with significant signal conditioning integrated on one chip. Due to the increased complexity of the device and its high pin count, careful PCB layout is important to achieve optimal performance. This data sheet provides a checklist of issues to look for and guidelines on how to optimize the PCB to mitigate performance issues. The goal of this data sheet is to help achieve optimal performance of the ADRV9008-1 while reducing board layout effort. This data sheet assumes that the reader is an experienced analog and RF engineer with an understanding of RF PCB layout and RF transmission lines. This data sheet discusses the following issues and provides guidelines for system designers to achieve optimal performance of the ADRV9008-1:

• PCB material and stackup selection • Fanout and trace space layout guidelines • Component placement and routing guidelines • RF and JESD204B transmission line layout • Isolation techniques used on the ADRV9008-1W/PCBZ • Power management considerations • Unused pin instructions

PCB MATERIAL AND STACKUP SELECTION Figure 170 shows the PCB stackup used for the ADRV9008-1W/PCBZ. Table 7 and Table 8 list the single-ended and differential impedance for the stackup shown in Figure 170. The dielectric material used on the top and the bottom layers is 8 mil Rogers 4350B. The remaining dielectric layers are FR4-370 HR. The board design uses the Rogers laminate for the top and the bottom layers for the low loss tangent at high frequencies. The ground planes under the Rogers laminate (Layer 2 and Layer 13) are the reference planes for the transmission lines routed on the outer surfaces. These layers are solid copper planes without any splits under the RF traces. Layer 2 and Layer

13 are crucial to maintaining the RF signal integrity and, ultimately, the ADRV9008-1 performance. Layer 3 and Layer 12 are used to route power supply domains. To keep the RF section of the ADRV9008-1 isolated from the fast transients of the digital section, the JESD204B interface lines are routed on Layer 5 and Layer 10. These layers have impedance control set to a 100 Ω differential. The remaining digital lines from ADRV9008-1 are routed on Inner Layer 7 and Inner Layer 8. RF traces on the outer layers must be a controlled impedance for optimal performance of the device. The inner layers in this board use 0.5 ounce copper or 1 ounce copper. The outer layers use 1.5 ounce copper so that the RF traces are less prone to pealing. Ground planes on this board are full copper floods with no splits except for vias, through-hole components, and isolation structures. The ground planes must route entirely to the edge of the PCB under the Surface-Mount Type A (SMA) connectors to maintain signal launch integrity. Power planes can be pulled back from the board edge to decrease the risk of shorting from the board edge.

1683

0-43

4

Figure 170. ADRV9008-1W/PCBZ Trace Impedance and Stackup

http://www.analog.com/EVAL-ADRV9008-9009?doc=ADRV9008-1.pdf






Rev. 0 | of 68

Table 7. Evaluation Board Single-Ended Impedance and Stackup1

Layer

Board Copper (%)

Starting Copper (oz.)

Finished Copper (oz.)

Single-Ended Impedance

Designed Trace Single-Ended (Inches)

Finished Trace Single-Ended (Inches)

Calculated Impedance (Ω)

Single-Ended Reference Layers

1 N/A 0.5 1.71 50 Ω ±10% 0.0155 0.0135 49.97 2 2 65 1 1 N/A N/A N/A N/A N/A 3 50 0.5 1 N/A N/A N/A N/A N/A 4 65 1 1 N/A N/A N/A N/A N/A 5 50 0.5 0.5 50 Ω ±10% 0.0045 0.0042 49.79 4, 6 6 65 1 1 N/A N/A N/A N/A N/A 7 50 0.5 0.5 50 Ω ±10% 0.0049 0.0039 50.05 6, 9 8 50 0.5 0.5 50 Ω ±10% 0.0049 0.0039 50.05 6, 9 9 65 1 1 N/A N/A N/A N/A N/A 10 50 0.5 1 50 Ω ±10% 0.0045 0.0039 49.88 9, 11 11 65 0.5 1 N/A N/A N/A N/A N/A 12 50 1 1 N/A N/A N/A N/A N/A 13 65 1 1 N/A N/A N/A N/A N/A 14 0.5 1.64 50 Ω ±10% 0.0155 0.0135 49.97 13 1 N/A means not applicable.

Table 8. Evaluation Board Differential Impedance and Stackup1

Layer Differential Impedance

Designed Trace (Inches)

Gap Differential for Designed Trace (Inches)

Finished Trace (Inches)

Gap Differential for Finished Trace (Inches)

Calculated Impedance (Ω)

Differential Reference Layers

1 100 Ω ± 10% 0.008 0.006 0.007 0.007 99.55 2 50 Ω ± 10% 0.0032 0.004 0.0304 0.0056 50.11 2 2 N/A1 N/A N/A N/A N/A N/A N/A 3 N/A N/A N/A N/A N/A N/A N/A 4 N/A N/A N/A N/A N/A N/A N/A 5 100 Ω ±10% 0.0036 0.0064 0.0034 0.0065 99.95 4, 6 6 N/A N/A N/A N/A N/A N/A N/A 7 100 Ω ±10% 0.0036 0.0064 0.0034 0.0066 100.51 6, 9 8 100 Ω ±10% 0.0038 0.0062 0.0034 0.0066 100.51 6, 9 9 N/A N/A N/A N/A N/A N/A N/A 10 100 Ω ±10% 0.0036 0.0064 0.003 0.007 100.80 9, 11 11 N/A N/A N/A N/A N/A N/A N/A 12 N/A N/A N/A N/A N/A N/A N/A 13 100 Ω ±10% 0.008 0.006 0.007 0.007 99.55 13 14 50 Ω ±10% 0.032 N/A 0.004 N/A 50.11 13 1 N/A means not applicable.



Rev. 0 | of 68

FANOUT AND TRACE SPACE GUIDELINES The ADRV9008-1 uses a 196-ball chip scale ball grid array (CSP_BGA), 12 mm × 12 mm package. The pitch between the pins is 0.8 mm. This small pitch makes it impractical to route all signals on a single layer. RF pins are placed on the outer edges of the ADRV9008-1 package. The location of the pins helps route the critical signals without a fanout via. Each digital signal is routed from the BGA pad using a 4.5 mil trace. The trace is connected to the BGA using a via in the pad structure. The signals are buried in the inner layers of the board for routing to other parts of the system.

The JESD204B interface signals are routed on two signal layers that use impedance control (Layer 5 and Layer 10). The spacing between the BGA pads is 17.5 mil. After the signal is on the inner layers, a 3.6 mil trace (50 Ω) connects the JESD204B signal to the field programmable gate array (FPGA) mezzanine card (FMC) connector. The recommended BGA land pad size is 15 mil.

Figure 171 shows the fanout scheme of the ADRV9008-1W/PCBZ. As mentioned before, the ADRV9008-1W/PCBZ uses a via in the pad technique. This routing approach can be used for the ADRV9008-1 if there are no issues with manufacturing capabilities.

JESD204B INTERFACETRACE WIDTH = 3.6mil

4.5mil TRACE

AIR GAP = 17.5mil

PAD SIZE = 15mil

VIA SIZE = 14mil

1683

0-43

5

Figure 171. Trace Fanout Scheme on the ADRV9008-1W/PCBZ (PCB Layer Top and Layer 5 Enabled)






Rev. 0 | of 68

COMPONENT PLACEMENT AND ROUTING GUIDELINES The ADRV9008-1 receiver requires few external components to function, but those that are used require careful placement and routing to optimize performance. This section provides a checklist for properly placing and routing critical signals and components.

Signals with Highest Routing Priority

RF lines and JESD204B interface signals are the signals that are most critical and must be routed with the highest priority.

Figure 170 shows the general directions in which each of the signals must be routed so that they can be properly isolated from noisy signals.

The receiver baluns and the matching circuits affect the overall RF performance of the ADRV9008-1 receiver. Make every effort to optimize the component selection and placement to avoid performance degradation. The RF Routing Guidelines section describes proper matching circuit placement and routing in more detail. Refer to the RF Port Interface Information section for more information.

To achieve the desired level of isolation between RF signal paths, use the technique described in the Isolation Techniques Used on the ADRV9008-1W/PCBZ section in customer designs.

1683

0-43

7






VCO_LDOVDDA1P1_

RF_VCOVDDA1P3_

RF_LO VSSA

VDDA1P3_AUX_VCO_






VSSA VSSA VSSAVDDA1P3_ CLOCK_

SYNTH VSSAVDDA1P3_RF_SYNTH VDDA1P3_

AUX_SYNTHRF_SYNTH_







DIGVDDD1P3_


SERVDDA1P3_

SER


INTERFACEVDDA1P3_

SERVDDA1P3_

SER


SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SER VSSA

VSSA

VDDA1P3_RX_RF

GPIO_3p3_0

GPIO_3p3_1

GPIO_3p3_2

VSSA

VSSA

DNC

DNC

VSSA

VSSA

VDDA1P1_CLOCK_VCO

VDDA1P3_CLOCK_

VCO_LDO


VDDA1P3_SER

VDDA1P3_SER VSSA

VDDA1P3_SER

VDDA1P3_SER

VDDA1P3_SER

VDDA1P3_SER

Figure 172. RF Input/Output, REF_CLK_IN±, and JESD204B Signal Routing Guidelines



Rev. 0 | of 68

Figure 173 shows placement for ac coupling capacitors and a 100 Ω termination resistor near the ADRV9008-1 REF_CLK_IN± pins. Shield the traces with ground flooding that is surrounded with vias staggered along the edge of the trace pair. The trace pair creates a shielded channel that shields the reference clock from any interference from other signals. Refer to the ADRV9008-1W/PCBZ layout and board support files included with the evaluation board software for exact details.

Route the JESD204B interface at the beginning of the PCB design and with the same priority as the RF signals.

The JESD204B Trace Routing Recommendations section outlines recommendations for JESD204B interface routing. Provide appropriate isolation between interface differential pairs. The Isolation Between JESD204B Lines section provides guidelines for optimizing isolation.

The RF_EXT_LO_I/O− pin (B7) and RF_EXT_LO_I/O+ pin (B8) on the ADRV9008-1 are internally dc biased. If an external LO is used, connect the LO to the device via ac coupling capacitors.

TOBGA BALLS

AC COUPLINGCAPS

100ΩTERMINATIONRESISTOR

1683

0-43

9

Figure 173. REF_CLK_IN± Routing Recommendation




Rev. 0 | of 68

Signals with Second Routing Priority

Power supply quality has a direct impact on overall system performance. To achieve optimal performance, follow recommendations for ADRV9008-1 power supply routing. The following recommendations outline how to route different power domains that can be connected together directly and to the same supply, but are separated by a 0 Ω placeholder resistor or ferrite bead.

When the recommendation is to use a trace to connect power to a particular domain, ensure that this trace is surrounded by ground.

Figure 174 shows an example of such traces routed on the ADRV9008-1W/PCBZ on Layer 12. Each trace is separated from any other signal by the ground plane and vias. Separating the traces from other signals is essential to providing necessary isolation between the ADRV9008-1 power domains.

1683

0-44

0

Figure 174. Layout Example of Power Supply Domains Routed with Ground Shielding (Layer 12 to Power)




Rev. 0 | of 68

Each power supply pin requires a 0.1 µF bypass capacitor near the pin at a minimum. Place the ground side of the bypass capacitor so that ground currents flow away from other power pins and the bypass capacitors.

For domains shown in Figure 175, like the domains powered through a 0 Ω placeholder resistor or ferrite bead (FB), place the 0 Ω placeholder resistors or ferrite beads further away from the device. Space 0 Ω placeholder resistors or ferrite beads apart from each other to ensure the electric fields on the ferrite beads do not influence each other. Figure 176 shows an example of how the ferrite beads, reservoir capacitors, and decoupling capacitors are

placed. The recommendation is to connect a ferrite bead between a power plane and the ADRV9008-1 at a distance away from the device. The ferrite bead and the reservoir capacitor provide stable voltage to the ADRV9008-1 during operation by isolating the pin or pins that the network is connected to from the power plane. Then, shield this trace with ground and provide power to the power pins on the ADRV9008-1. Place a 100 nF capacitor near the power supply pin with the ground side of the bypass capacitor placed so that ground currents flow away from other power pins and the bypass capacitors.

1683

0-44

1






VCO_LDOVDDA1P1_

RF_VCOVDDA1P3_

RF_LO VSSA

VDDA1P3_AUX_VCO_






VSSA VSSA VSSA VSSAVDDA1P3_RF_SYNTH VDDA1P3_

AUX_SYNTHRF_SYNTH_



VSSA GPIO_18 RESET TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA DNC



DIGVDDD1P3_


SERVDDA1P3_

SER


INTERFACEVDDA1P3_

SERVDDA1P3_

SER


SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SER VSSA

VSSA

VDDA1P3_RX_RF

GPIO_3p3_0

GPIO_3p3_1

GPIO_3p3_2

VSSA

VSSA

DNC

DNC

VSSA

VSSA

VDDA1P1_CLOCK_VCO

VDDA1P3_CLOCK_

VCO_LDO


VDDA1P3_SER

VDDA1P3_SER VSSA

VDDA1P3_SER

VDDA1P3_SER

VDDA1P3_SER

VDDA1P3_SER

VDDA1P3_ CLOCK_SYNTH

GP_INTERRUPT

TRACE THROUGH 0Ω RES. TO 1.3V ANALOG PLANE (AP)MAINTAIN LOWEST POSSIBLE IMPEDANCE

TRACE THROUGH 0.1Ω RESISTOR TO AP

TRACE THROUGH 0Ω RESISTOR TO AP

TRACE THROUGH FBTO 3.3V PLANE

TRACE THROUGH 0ΩTO 1.8V PLANE

WIDE TRACE TO1.3V DIGITAL SUPPLYHIGH CURRENT

TRACE THROUGHFB TO 1.3VJESD204B SUPPLY

TRACE THROUGH0Ω TO AP

TRACE THROUGH1Ω RESISTOR TO AP



TRACE THROUGH FBTO INTERFACE SUPPLY



TRACE THROUGH0Ω TO 1.8V PLANE

TRACE THROUGH 0ΩTO PLANE

Figure 175. Power Supply Domains Interconnection Guidelines



Rev. 0 | of 68

DUT

0Ω RESISTOR

1µ + 100nF bypass

CAPS ORIENTED SUCH

THAT CURRENTS FLOW

AWAY FROM OTHER

POWER PINS

PLACEHOLDERSFOR FERRITE BEADS

0Ω RESISTORPLACEHOLDERSFOR FERRITE BEADS

RESERVOIRCAPACITORS

1683

0-44

4

Figure 176. Placement Example of 0 Ω Resistor Placeholders for Ferrite Beads, Reservoir and Bypass Capacitors on the ADRV9008-1W/PCBZ (Layer 12 to Power and

Bottom)




Rev. 0 | of 68

Signals with Lowest Routing Priority

As a last step while designing the PCB layout, route the signals shown in Figure 177. The following list outlines the recommended order of signal routing:

1. Use ceramic 1 µF bypass capacitors at the VDDA1P1_ RF_VCO, VDDA1P1_AUX_VCO, and VDDA1P1_CLOCK_ VCO pins. Place these pins as close as possible to the ADRV9008-1 device with the ground side of the bypass capacitor placed so that ground currents flow away from other power pins and the bypass capacitors, if possible.

2. Connect a 14.3 kΩ resistor to the RBIAS pin (C14). This resistor must have a 1% tolerance.

3. Pull the TEST pin (J6) to ground for normal operation. The device supports JTAG boundary scan, and this pin is used to access that function. Refer to the JTAG Boundary Scan section for JTAG boundary scan information.

4. Pull the RESET pin (J4) high with a 10 kΩ resistor to VDD_INTERFACE for normal operation. To reset the device, drive the RESET pin low.

When routing analog signals such as GPIO_3p3_x or AUXADC_x, it is recommended to route the signals away from the digital section (Row H through Row P). Do not cross the analog section of the ADRV9008-1, highlighted by a red dotted line in Figure 177, by any digital signal routing.

When routing digital signals from Row H and below, it is important to route the signals away from the analog section (Row A through Row G). Do not cross the analog section of the ADRV9008-1, highlighted by a red dotted line in Figure 177, by any digital signal routing.






VCO_LDOVDDA1P1_

RF_VCOVDDA1P3_

RF_LO VSSA

VDDA1P3_AUX_VCO_






VSSA VSSA VSSAVDDA1P3_ CLOCK_SYNTH VSSA

VDDA1P3_RF_SYNTH VDDA1P3_

AUX_SYNTHRF_SYNTH_







DIGVDDD1P3_


SERVDDA1P3_

SER


INTERFACEVDDA1P3_

SERVDDA1P3_

SER


SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SERVDDA1P3_

SER VSSA

VSSA

VDDA1P3_RX_RF

GPIO_3p3_0

GPIO_3p3_1

GPIO_3p3_2

VSSA

VSSA

DNC

DNC

VSSA

VSSA

VDDA1P1_CLOCK_VCO

VDDA1P3_CLOCK_

VCO_LDO


VDDA1P3_SER

VDDA1P3_SER VSSA

VDDA1P3_SER

VDDA1P3_SER

VDDA1P3_SER

VDDA1P3_SER

1683

0-44

5

1µF CAPACITOR1µF CAPACITOR

1µF CAPACITOR

14.3kΩ RESISTOR

ALL DIGITALGPIO SIGNALSROUTED BELOWTHE RED LINE

Figure 177. AUXADC_x, Analog, and Digital GPIO Signals Routing Guidelines



Rev. 0 | of 68

RF AND JESD204B TRANSMISSION LINE LAYOUT RF Routing Guidelines

The ADRV9008-1W/PCBZ uses microstrip type lines for receiver traces. In general, Analog Devices does not recommend using vias to route RF traces unless a direct line route is not possible. Differential lines from the balun to the receiver pins must be as short as possible. Keep the length of the single-ended transmission line short to minimize the effects of parasitic coupling. It is important to note that these traces are the most critical when optimizing performance and are, therefore, routed before any other routing. These traces have the highest priority if trade-offs are needed.

Figure 178 shows pi matching networks on the single-ended side of the baluns. The receiver front end is dc biased internally. Therefore, the differential side of the balun is ac-coupled. The system designer can optimize the RF performance with a proper selection of the balun, matching components, and ac coupling capacitors. The external LO traces and the REF_CLK_IN± traces may also require matching components to ensure optimal performance.

All the RF signals mentioned previously must have a solid ground reference under each trace. Do not run any of the critical traces over a section of the reference plane that is discontinuous. The ground flood on the reference layer must extend all the way to the edge of the board. This flood length ensures signal integrity for the SMA launch when an edge launch connector is used.

Refer to the RF Port Interface Information section for more information on RF matching recommendations for the ADRV9008-1.

1683

0-44

8

Figure 178. Pi Network Matching Components Available on Different RF Nets




Rev. 0 | of 68

JESD204B Trace Routing Recommendations

The ADRV9008-1 receiver uses the JESD204B, high speed serial interface. To ensure optimal performance of this interface, keep the differential traces as short as possible by placing the ADRV9008-1 as close as possible to the FPGA or BBP, and route the traces directly between the devices. Use a PCB material with a low dielectric constant (< 4) to minimize loss. For distances greater than 6 inches, use a premium PCB material, such as RO4350B or RO4003C.

Routing Recommendations

Route the differential pairs on a single plane using a solid ground plane as a reference on the layers above and/or below these traces.

All JESD204B lane traces must be impedance controlled to achieve 50 Ω to ground. It is recommended that the differential pair be coplanar and loosely coupled. An example of a typical configuration is 5 mil trace width and 15 mil edge to edge spacing, with the trace width maximized as shown in Figure 179.

Match trace widths with pin and ball widths as closely as possible while maintaining impedance control. If possible, use 1 oz. copper trace widths of at least 8 mil (200 µm). The coupling capacitor pad size must match JESD204B lane trace widths as closely as possible. If trace width does not match pad size, use a smooth transition between different widths.

The pad area for all connector and passive component choices must be minimized due to a capacitive plate effect that leads to problems with signal integrity.

Reference planes for impedance controlled signals must not be segmented or broken for the entire length of a trace.

The REF_CLK_IN± signal trace and the SYSREF signal trace are impedance controlled for character impedance (ZO) = 50 Ω.

Stripline Transmission Lines vs. Microstrip Transmission Lines

Stripline trasmission lines have less signal loss and emit less electromagnetic interference than microstrip trasmission lines. However, stripline trasmission lines require the use of vias that add line inductance, increasing the difficulty of controlling the impedance.

Microstrip trasmission lines are easier to implement if the component placement and density allow routing on the top layer. Microstrip trasmission lines make controlling the impedance easier.

If the top layer of the PCB is used by other circuits or signals, or if the advantages of stripline are more desirable over the advantages of microstrip, follow these recommendations:

• Minimize the number of vias. • Use blind vias where possible to eliminate via stub effects,

and use micro vias to minimize via inductance. • When using standard vias, use a maximum via length to

minimize the stub size. For example, on an 8-layer board, use Layer 7 for the stripline pair.

• Place a pair of ground vias near each via pair to minimize the impedance discontinuity.

Route the JESD204B lines on the top side of the board as a differential 100 Ω pair (microstrip). For the ADRV9008-1W/PCBZ, the JESD204B differential signals are routed on inner layers of the board (Layer 5 and Layer 10) as differential 100 Ω pairs (stripline). To minimize potential coupling, these signals are placed on an inner layer using a via embedded in the component footprint pad where the ball connects to the PCB. The ac coupling capacitors (100 nF) on these signals are placed near the connector and away from the chip to minimize coupling. The JESD204B interface can operate at frequencies of up to 12 GHz. Ensure that signal integrity from the chip to the connector is maintained.

DIFF A DIFF B DIFF A DIFF B

TIGHTLY COUPLEDDIFFERENTIAL LINES

LOOSELY COUPLEDDIFFERENTIAL LINES 16

830-

452

Figure 179. Routing JESD204B, Diff A and Diff B Correspond to Differential Positive Signals or Negative Signals (One Differential Pair)





Rev. 0 | of 68

1683

0-45

3

Figure 180. Isolation Structures on the ADRV9008-1W-PCBZ

ISOLATION TECHNIQUES USED ON THE ADRV9008-1W/PCBZ Isolation Goals

Significant isolation challenges were overcome in designing the ADRV9008-1W/PCBZ. The following isolation requirement is used to accurately evaluate the ADRV9008-1 receiver performance: receiver to receiver, 65 dB out to 6 GHz.

To meet these isolation goals with significant margin, isolation structures are introduced.

Figure 180 shows the isolation structures used on the ADRV9008-1W/PCBZ. These structures consist of a combination of slots and square apertures. These structures are present on every copper layer of the PCB stack. The advantage of using square apertures is that signals can be routed between the openings without affecting the isolation benefits of the array of apertures. When using these isolation structures, make sure to place ground vias around the slots and apertures.

Figure 181 outlines the methodology used on the ADRV9008-1W/PCBZ. When using slots, ground vias must be placed at the ends of the slots and along the sides of the slots. When using square apertures, at least one single ground via must be placed adjacent to each square. These vias must be through-hole vias from the top to the bottom layer. The function of these vias is to steer return current to the ground planes near the apertures.

For accurate slot spacing and square apertures layout, use simulation software when designing a PCB for the ADRV9008-1

receivers. Spacing between square apertures must be no more than 1/10 of a wavelength. Calculate the wavelength using Equation 1:

×300 (m) =

(MHz) R

WavelengthFrequency E

(1)

where ER is the dielectric constant of the isolator material. For RO4003C material, microstrip structure (+ air) ER = 2.8. For FR4-370HR material, stripline structure ER = 4.1.

For example, if the maximum RF signal frequency is 6 GHz, and ER = 2.8 for RO4003C material, microstrip structure (+ air), the minimum wavelength is approximately 29.8 mm.

To follow the 1/10 wavelength spacing rule, square aperture spacing must be 2.98 mm or less.

Isolation Between JESD204B Lines

The JESD204B interface uses eight line pairs that can operate at speeds of up to 12 GHz. When configuring the PCB layout, ensure that these lines are routed according to the rules outlined in the JESD204B Trace Routing Recommendations section. In addition, use isolation techniques to prevent crosstalk between different JESD204B lane pairs.

Figure 182 shows a technique used on the ADRV9008-1W/PCBZ that involves via fencing. Placing ground vias around each JESD204B pair provides isolation and decreases crosstalk. The spacing between vias is 1.2 mm.











Rev. 0 | of 68

1683

0-45

4

Figure 181. Current Steering Vias Placed Next to Isolation Structures

1.24mm

1683

0-45

5

Figure 182. Via Fencing Around JESD204B Lines, PCB Layer 10

Figure 182 shows the rule provided in Equation 1. JESD204B lines are routed on Layer 5 and Layer 10 so that the lines use stripline structures. The dielectric material used in the inner layers of the ADRV9008-1W/PCBZ PCB is FR4-370HR.

For accurate spacing of the JESD204B fencing vias, use layout simulation software. Input the following data into Equation 1 to calculate the wavelength and square aperture spacing:

• Maximum JESD204B signal frequency is approximately 12 GHz.

• For FR4-370HR material, stripline structure, ER = 4.1, the minimum wavelength is approximately 12.4 mm.

To follow the 1/10 wavelength spacing rule, spacing between vias must be 1.24 mm or less. The minimum spacing recommendation according to transmission line theory is 1/4 wavelength.

RF PORT INTERFACE INFORMATION This section details the RF receiver interfaces for optimal device performance. This section also includes data for the anticipated ADRV9008-1 RF port impedance values and examples of impedance matching networks used in the evaluation platform. This section also provides information on board layout techniques and balun selection guidelines.

The ADRV9008-1 is a highly integrated receiver device. External impedance matching networks are required on the receiver port to achieve performance levels indicated in the Specifications section.

Analog Devices recommends the use of simulation tools in the design and optimization of impedance matching networks. To achieve the closest match between computer simulated results and measured results, accurate models of the board environment, SMD components (including baluns and filters), and ADRV9008-1 port impedances are required.

RF Port Impedance Data

This section provides the port impedance data for the receivers in the ADRV9008-1 integrated receiver. Note the following:

• ZO is defined as 50 Ω. • The ADRV9008-1 ball pads are the reference plane for

this data. • Single-ended mode port impedance data is not available.

However, a rough assessment is possible by taking the differential mode port impedance data and dividing both the real and imaginary components by 2.




Rev. 0 | of 68

0

5.0

–5.0

2.0

1.0

–1.0

–2.0

0.5

–0.5

0.2

–0.2

m15FREQUENCY = 100MHzS(1,1) = 0.390/–1.819IMPEDANCE = 113.933 – j3.331m16FREQUENCY = 300MHzS(1,1) = 0.390/–5.495IMPEDANCE = 112.803 – j9.931m17FREQUENCY = 500MHzS(1,1) = 0.388/–9.198IMPEDANCE = 110.398 – j16.107m18FREQUENCY = 1GHzS(1,1) = 0.377–18.643IMPEDANCE = 100.377 – j28.250m19FREQUENCY = 2GHzS(1,1) = 0.336/–39.123IMPEDANCE = 74.966 – j35.800

FREQUENCY (0Hz TO 6GHz)

M21

M23

m20FREQUENCY = 3GHzS(1,1) = 0.267/–64.650IMPEDANCE = 55.102 – j28.685m21FREQUENCY = 4GHzS(1,1) = 0.186/–104.336IMPEDANCE = 42.821 – j16.026m22FREQUENCY = 5GHzS(1,1) = 0.164/–173.106IMPEDANCE = 35.977 – j1.455m23FREQUENCY = 6GHzS(1,1) = 0.266/130.063IMPEDANCE = 32.890 + j14.399

S(1,

1)

M20

M19 M18

M17M16M15M22

1683

0-45

9

Figure 183. Receiver 1 and Receiver 2 SEDZ and Parallel Equivalent Differential Impedance (PEDZ) Data

0

5.0

–5.0

2.0

1.0

–1.0

–2.0

0.5

–0.5

0.2

–0.2

m1FREQUENCY = 100MHzS(1,1) = 0.018/–149.643IMPEDANCE = 48.491 – j0.866m2FREQUENCY = 750MHzS(1,1) = 0.074/–123.043IMPEDANCE = 45.753 – j5.744m3FREQUENCY = 1.5GHzS(1,1) = 0.147/–138.745IMPEDANCE = 39.362 – j7.804m4FREQUENCY = 3GHzS(1,1) = 0.292/–175.424IMPEDANCE = 27.426 – j1.397m5FREQUENCY = 6GHzS(1,1) = 0.538/123.271IMPEDANCE = 18.885 – j23.935m6FREQUENCY = 12GHzS(1,1) = 0.757/46.679IMPEDANCE = 40.002 – j103.036

M4

M3M2

M1

M5

FREQUENCY (100MHz TO 12GHz)

M6

350

300

250

200

150

100

50

00 42 6 8 10 12

R_P

EDZ

FREQUENCY (GHz)L_

OR

_C_P

EX_

STA

TUS

900

800

700

600

500

400

300

200

100

0

R_PEDZL_OR_C_PEX_STATUS

m7FREQUENCY = 5GHzL_OR_C_PE = 1.336m8FREQUENCY = 5GHzR_PEDZ = 31.172m9FREQUENCY = 5GHzX_STATUS = 1

1683

0-46

1

Figure 184. RF_EXT_LO_I/O± SEDZ and PEDZ Data



Rev. 0 | of 68

0

5.0

–5.0

2.0

1.0

–1.0

–2.0

0.5

–0.5

0.2

–0.2

m1FREQUENCY = 100MHzS(1,1) = 0.999/–1.396IMPEDANCE = 159.977 – j4.099E3m2FREQUENCY = 250MHzS(1,1) = 0.999/–3.480IMPEDANCE = 30.567 – j1.645E3m3FREQUENCY = 500MHzS(1,1) = 0.999/–6.952IMPEDANCE = 9.723 – j823.070m4FREQUENCY = 750MHzS(1,1) = 0.998/–10.431IMPEDANCE = 5.273 – j547.733m5FREQUENCY = 1GHzS(1,1) = 0.999/–13.925IMPEDANCE = 3.521 – j409.400

M4M3M2M1

M5

FREQUENCY (0.000Hz TO 1.100GHz)

13E+5

4.0E+4

6.0E+4

9.0E+4

1.1E+5

1.2E+5

8.0E+4

5.0E+4

7.0E+4

1.0E+5

0 0.3 0.5 0.7 0.90.1 0.2 0.4 0.6 0.8 1.0 1.1

R_P

EDZ

FREQUENCY (GHz)

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

L_O

R_C

_PE

X_ST

ATU

S

R_PEDZL_OR_C_PEX_STATUS

m7FREQUENCY = 1GHzL_OR_C_PE = 0.389m8FREQUENCY = 1GHzR_PEDZ = 4.761E4m9FREQUENCY = 1GHzX_STATUS = 0

1683

0-46

2

Figure 185. REF_CLK_IN± SEDZ and PEDZ Data—On Average, the Real Part of Parallel Equivalent Differential Impedance (RP) = ~70 kΩ



Rev. 0 | of 68

Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File

Analog Devices supplies the port impedance as an .s1p file that can be downloaded from the ADRV9008-1 product page. This format allows simple interfacing to the ADS by using the data access component. In Figure 186, Term1 is the single-ended input or output, and Term2 is the differential input or output RF port on the ADRV9008-1. The pi on the single-ended side and the differential pi configuration on the differential side allow maximum flexibility in designing matching circuits. The pi configuration is suggested for all design layouts because the pi configuration can step the impedance up or down as needed with appropriate component population.

The mechanics of setting up a simulation for impedance measurement and impedance matching is as follows:

1. The data access component block reads the RF port .s1p file. This file is the device RF port reflection coefficient.

2. The two equations convert the RF port reflection coefficient to a complex impedance. The result is the RX_SEDZ variable.

3. The RF port calculated complex impedance (RX_SEDZ) is used to define the Term2 impedance.

4. Term2 is used in a differential mode, and Term1 is used in a single-ended mode.

Setting up the simulation this way allows one to measure the input reflection (S11), output reflection (S22), and through reflection (S21) of the three port system without complex math operations within the display page.

For the highest accuracy, the electromagnetic momentum (EM) modeling result of the PCB artwork and S parameters (S11, S22, and S21) of the matching components and balun must be used in the simulations.

1683

0-46

3

Figure 186 Simulation Setup in ADS with SEDZ .s1p Files and DataAccessComponent



Rev. 0 | of 68

General Receiver Path Interface

The ADRV9008-1 receivers can support up to a 200 MHz bandwidth.

The ADRV9008-1 receivers support a wide range of operation frequencies. In the case of the receiver channels, the differential signals interface to an integrated mixer. The mixer input pins have a dc bias of approximately 0.7 V and may need to be ac-coupled, depending on the common-mode voltage level of the external circuit.

Important considerations for the receiver port interface are as follows:

• The device to be interfaced (filter, balun, transmit/receive (T/R) switch, external low noise amplifier (LNA), external PA, and so on).

• The receiver maximum safe input power is 23 dBm (peak). • The receiver optimum dc bias voltage is 0.7 V bias to

ground. • The board design (reference planes, transmission lines,

impedance matching, and so on).

Figure 187 and Figure 188 show possible differential receiver port interface circuits. The options in Figure 187 and Figure 188 are valid for all receiver inputs operating in differential mode, though only the Receiver 1 signal names are indicated. Impedance matching may be necessary to obtain data sheet performance levels.

Given wide RF bandwidth applications, SMD balun devices function well. Decent loss and differential balance are available in a relatively small (0603, 0805) package.

RX1_IN–

RX1_IN+

RECEIVERINPUT

STAGE(MIXER OR LNA)

1683

0-47

0

Figure 187. Differential Receiver Interface Using a Transformer

CC

CC

RECEIVERINPUT

STAGE(MIXER OR LNA)

1683

0-47

1

RX1_IN–

RX1_IN+

Figure 188. Differential Receiver Interface Using a Transmission Line Balun

Impedance Matching Network Examples

Impedance matching networks are required to achieve the ADRV9008-1 data sheet performance levels. This section provides a description of the matching network topology and components used on the ADRV9008-1W/PCBZ.

Device models, board models, and balun and SMD component models are required to build an accurate system level simulation. The board layout model can be obtained from an EM simulator. The balun and SMD component models can be obtained from the device vendors or built locally. Contact Analog Devices applications engineering for ADRV9008-1 modeling details.

The impedance matching network provided in this section is not evaluated in terms of mean time to failure (MTTF) in high volume production. Consult with component vendors for long-term reliability concerns. Consult with balun vendors to determine appropriate conditions for dc biasing.

Figure 190 shows three elements in parallel marked do not install (DNI). However, only one set of SMD component pads is placed on the board. For example, the R202, L202, and C202 components only have one set of SMD pads for one SMD component. Figure 190 shows that, in a generic port impedance matching network, the shunt or series elements may be a resistor, inductor, or capacitor.




Rev. 0 | of 68

1683

0-47

2

Rx IN

Rx TOPOLOGY

Rx +UNBAL_IN

BAL_OUT1

BAL_OUT2NC_66 5 2

GND GND_DC_FEED_RFGND

Rx –R3280Ω

1 13

42 3 4 5

Figure 189. Impedance Matching Topology

RX2

RX1

DNI

0Ω

DNI DNI

18pF

TCM1-83X+

DNI10pF 27pF

TCM1-83X+

DNI

0Ω

0Ω

DNI

0Ω

0Ω 18pF 0Ω

DNI

DNI

C249

C248

C242DNI

T202

C24327pF

T201

C241C240

J201

J202

C208

R209

C210DNI C211

R213

R212

C214

C201 C203

R202

R206

R205

C207C204

RX1_BAL–

RX2_UNBAL

RX1_UNBAL

RX2_BAL+

RX1_BAL+

RX2_IN-

RX2_IN+

RX1_IN-

RX1_IN+

RX2_BAL–

54

32

6 1

6 1

54

32

5432

5432

1

1

AGNDAGND AGND

NC

AGND

NC

AGND

AGNDAGND AGND

1683

0-40

0

Figure 190. Receiver 1 (RX1) and Receiver 2 (RX2) Generic Matching Network Topology



Rev. 0 | of 68

Table 9 and shows the selected balun and component values used for three matching network sets. Refer to the ADRV9008-1 schematics for a wideband matching example that operates across the entire device frequency range with somewhat reduced performance.

The RF matching used in the ADRV9008-1W/PCBZ allows the ADRV9008-1 to operate across the entire chip frequency range with slightly reduced performance.

Table 9. Receiver 1 and Receiver 2 Evaluation Board Matching Components for Frequency Band 75 MHz to 6000 MHz Component Value C201, C208 Do not install (DNI) R202, R209 0 Ω C203, C210 DNI C248, C249 18 pF C204, C211 DNI R205/R206, R212/R213 0 Ω C207, C214 DNI T201, T202 Mini circuits TMC1-83X+




Rev. 0 | of 68

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1. 03-0

2-20

15-A

0.80

0.80 REF

0.44 REF

ABCDEFG

91011121314 8 7 56 4 23 1

BOTTOM VIEW

10.40 SQ

HJKLMNP

DETAIL A

TOP VIEW

DETAIL A

COPLANARITY0.12

0.500.450.40

BALL DIAMETER

SEATINGPLANE

12.1012.00 SQ11.90

A1 BALLPAD CORNER

1.271.181.09

7.755 REF

8.090 REF

0.910.840.77

0.390.340.29

PKG

-004

723

A1 BALLCORNER

PIN A1INDICATOR

Figure 191. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-196-13) Dimensions shown in millimeters

ORDERING GUIDE Model1 Temperature Range2 Package Description Package Option ADRV9008BBCZ-1 −40°C to +85°C 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-196-13 ADRV9008BBCZ-1REEL −40°C to +85°C 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] BC-196-13 ADRV9008-1W/PCBZ Pb-Free Evaluation Board, 75 MHz to 6000 MHz 1 Z = RoHS Compliant Part. 2 See the Thermal Management section.

©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16830-0-9/18(0)



integrated dual rf receivers data sheet adrv9008-1 · integrated dual rf receivers data sheet...

Documents