Order Number: 326776-003

Intel 7 Series / C216 Chipset Family Platform Controller Hub (PCH)Datasheet

June 2012

2 Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.A "Mission Critical Application" is any application in which failure of the Intel Product could result, directly or indirectly, in personal injury or death. SHOULD YOU PURCHASE OR USE INTEL'S PRODUCTS FOR ANY SUCH MISSION CRITICAL APPLICATION, YOU SHALL INDEMNIFY AND HOLD INTEL AND ITS SUBSIDIARIES, SUBCONTRACTORS AND AFFILIATES, AND THE DIRECTORS, OFFICERS, AND EMPLOYEES OF EACH, HARMLESS AGAINST ALL CLAIMS COSTS, DAMAGES, AND EXPENSES AND REASONABLE ATTORNEYS' FEES ARISING OUT OF, DIRECTLY OR INDIRECTLY, ANY CLAIM OF PRODUCT LIABILITY, PERSONAL INJURY, OR DEATH ARISING IN ANY WAY OUT OF SUCH MISSION CRITICAL APPLICATION, WHETHER OR NOT INTEL OR ITS SUBCONTRACTOR WAS NEGLIGENT IN THE DESIGN, MANUFACTURE, OR WARNING OF THE INTEL PRODUCT OR ANY OF ITS PARTS.Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined". Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The information here is subject to change without notice. Do not finalize a design with this information.The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548-4725, or go to: http://www.intel.com/design/literature.htm.I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips Corporation.No computer system can provide absolute security under all conditions. Intel Trusted Execution Technology (Intel TXT) requires a computer system with Intel Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). Intel TXT also requires the system to contain a TPM v1.s. For more information, visit http://www.intel.com/technology/security Intel Virtualization Technology requires a computer system with an enabled Intel processor, BIOS, virtual machine monitor (VMM). Functionality, performance or other benefits will vary depending on hardware and software configurations. Software applications may not be compatible with all operating systems. Consult your PC manufacturer. For more information, visit http://www.intel.com/go/virtualization Intel, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.*Other names and brands may be claimed as the property of others.Copyright 2012, Intel Corporation

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Contents

1 Introduction ............................................................................................................ 431.1 About This Manual ............................................................................................. 431.2 Overview ......................................................................................................... 46

1.2.1 Capability Overview................................................................................ 471.3 Intel 7 Series / C216 Chipset Family SKU Definition ............................................. 54

2 Signal Description ................................................................................................... 572.1 Direct Media Interface (DMI) to Host Controller ..................................................... 592.2 PCI Express* .................................................................................................... 592.3 PCI Interface .................................................................................................... 602.4 Serial ATA Interface........................................................................................... 632.5 LPC Interface.................................................................................................... 662.6 Interrupt Interface ............................................................................................ 662.7 USB Interface ................................................................................................... 672.8 Power Management Interface.............................................................................. 692.9 Processor Interface............................................................................................ 732.10 SMBus Interface................................................................................................ 732.11 System Management Interface............................................................................ 742.12 Real Time Clock Interface................................................................................... 742.13 Miscellaneous Signals ........................................................................................ 752.14 Intel High Definition Audio Link ......................................................................... 762.15 Controller Link .................................................................................................. 772.16 Serial Peripheral Interface (SPI) .......................................................................... 772.17 Thermal Signals ................................................................................................ 782.18 Testability Signals ............................................................................................. 782.19 Clock Signals .................................................................................................... 792.20 LVDS Signals .................................................................................................... 812.21 Analog Display /VGA DAC Signals ........................................................................ 822.22 Intel Flexible Display Interface (Intel FDI) ........................................................ 822.23 Digital Display Signals........................................................................................ 832.24 General Purpose I/O Signals ............................................................................... 852.25 Manageability Signals ........................................................................................ 902.26 Power and Ground Signals.................................................................................. 902.27 Pin Straps ........................................................................................................ 932.28 External RTC Circuitry........................................................................................ 97

3 PCH Pin States......................................................................................................... 993.1 Integrated Pull-Ups and Pull-Downs ..................................................................... 993.2 Output and I/O Signals Planes and States........................................................... 1013.3 Power Planes for Input Signals .......................................................................... 113

4 PCH and System Clocks ......................................................................................... 1194.1 Platform Clocking Requirements ........................................................................ 1194.2 Functional Blocks ............................................................................................ 1224.3 Clock Configuration Access Overview ................................................................. 1234.4 Straps Related to Clock Configuration ................................................................ 123

5 Functional Description ........................................................................................... 1255.1 PCI-to-PCI Bridge (D30:F0) .............................................................................. 125

5.1.1 PCI Bus Interface ................................................................................. 1255.1.2 PCI Bridge As an Initiator ...................................................................... 126

5.1.2.1 Memory Reads and Writes........................................................ 1265.1.2.2 I/O Reads and Writes .............................................................. 1265.1.2.3 Configuration Reads and Writes ................................................ 1265.1.2.4 Locked Cycles ........................................................................ 1265.1.2.5 Target / Master Aborts............................................................. 1265.1.2.6 Secondary Master Latency Timer............................................... 1265.1.2.7 Dual Address Cycle (DAC) ........................................................ 1275.1.2.8 Memory and I/O Decode to PCI................................................. 127

5.1.3 Parity Error Detection and Generation ..................................................... 1275.1.4 PCIRST#............................................................................................. 1285.1.5 Peer Cycles ......................................................................................... 128

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5.1.6 PCI-to-PCI Bridge Model ........................................................................1285.1.7 IDSEL to Device Number Mapping ...........................................................1295.1.8 Standard PCI Bus Configuration Mechanism..............................................1295.1.9 PCI Legacy Mode ..................................................................................129

5.2 PCI Express* Root Ports (D28:F0,F1,F2,F3,F4,F5, F6, F7) .....................................1295.2.1 Interrupt Generation .............................................................................1305.2.2 Power Management...............................................................................130

5.2.2.1 S3/S4/S5 Support ...................................................................1305.2.2.2 Resuming from Suspended State...............................................1315.2.2.3 Device Initiated PM_PME Message .............................................1315.2.2.4 SMI/SCI Generation.................................................................131

5.2.3 SERR# Generation ................................................................................1325.2.4 Hot-Plug..............................................................................................132

5.2.4.1 Presence Detection..................................................................1325.2.4.2 Message Generation ................................................................1325.2.4.3 Attention Button Detection .......................................................1335.2.4.4 SMI/SCI Generation.................................................................133

5.3 Gigabit Ethernet Controller (B0:D25:F0) .............................................................1345.3.1 GbE PCI Express* Bus Interface..............................................................135

5.3.1.1 Transaction Layer....................................................................1355.3.1.2 Data Alignment.......................................................................1355.3.1.3 Configuration Request Retry Status ...........................................136

5.3.2 Error Events and Error Reporting ............................................................1365.3.2.1 Data Parity Error .....................................................................1365.3.2.2 Completion with Unsuccessful Completion Status.........................136

5.3.3 Ethernet Interface ................................................................................1365.3.3.1 82579 LAN PHY Interface .........................................................136

5.3.4 PCI Power Management.........................................................................1375.3.4.1 Wake Up ................................................................................137

5.3.5 Configurable LEDs.................................................................................1395.3.6 Function Level Reset Support (FLR).........................................................140

5.3.6.1 FLR Steps...............................................................................1405.4 LPC Bridge (with System and Management Functions) (D31:F0).............................140

5.4.1 LPC Interface .......................................................................................1405.4.1.1 LPC Cycle Types......................................................................1415.4.1.2 Start Field Definition................................................................1425.4.1.3 Cycle Type / Direction (CYCTYPE + DIR).....................................1425.4.1.4 Size.......................................................................................1425.4.1.5 SYNC.....................................................................................1435.4.1.6 SYNC Time-Out.......................................................................1435.4.1.7 SYNC Error Indication ..............................................................1435.4.1.8 LFRAME# Usage......................................................................1435.4.1.9 I/O Cycles ..............................................................................1445.4.1.10 Bus Master Cycles ...................................................................1445.4.1.11 LPC Power Management ...........................................................1445.4.1.12 Configuration and PCH Implications ...........................................144

5.5 DMA Operation (D31:F0) ..................................................................................1455.5.1 Channel Priority....................................................................................145

5.5.1.1 Fixed Priority ..........................................................................1455.5.1.2 Rotating Priority ......................................................................146

5.5.2 Address Compatibility Mode ...................................................................1465.5.3 Summary of DMA Transfer Sizes .............................................................146

5.5.3.1 Address Shifting When Programmed for 16-Bit I/O Count by Words1465.5.4 Autoinitialize ........................................................................................1475.5.5 Software Commands .............................................................................147

5.6 LPC DMA ........................................................................................................1475.6.1 Asserting DMA Requests ........................................................................1475.6.2 Abandoning DMA Requests.....................................................................1485.6.3 General Flow of DMA Transfers ...............................................................1495.6.4 Terminal Count.....................................................................................1495.6.5 Verify Mode .........................................................................................1495.6.6 DMA Request Deassertion ......................................................................1495.6.7 SYNC Field / LDRQ# Rules .....................................................................150

5.7 8254 Timers (D31:F0)......................................................................................1515.7.1 Timer Programming ..............................................................................1515.7.2 Reading from the Interval Timer .............................................................152

5.7.2.1 Simple Read ...........................................................................152

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5.7.2.2 Counter Latch Command.......................................................... 1535.7.2.3 Read Back Command .............................................................. 153

5.8 8259 Interrupt Controllers (PIC) (D31:F0) .......................................................... 1545.8.1 Interrupt Handling................................................................................ 155

5.8.1.1 Generating Interrupts.............................................................. 1555.8.1.2 Acknowledging Interrupts ........................................................ 1555.8.1.3 Hardware/Software Interrupt Sequence ..................................... 156

5.8.2 Initialization Command Words (ICWx)..................................................... 1565.8.2.1 ICW1 .................................................................................... 1565.8.2.2 ICW2 .................................................................................... 1575.8.2.3 ICW3 .................................................................................... 1575.8.2.4 ICW4 .................................................................................... 157

5.8.3 Operation Command Words (OCW)......................................................... 1575.8.4 Modes of Operation .............................................................................. 157

5.8.4.1 Fully Nested Mode................................................................... 1575.8.4.2 Special Fully-Nested Mode........................................................ 1585.8.4.3 Automatic Rotation Mode (Equal Priority Devices)........................ 1585.8.4.4 Specific Rotation Mode (Specific Priority).................................... 1585.8.4.5 Poll Mode............................................................................... 1585.8.4.6 Edge and Level Triggered Mode ................................................ 1595.8.4.7 End of Interrupt (EOI) Operations ............................................. 1595.8.4.8 Normal End of Interrupt........................................................... 1595.8.4.9 Automatic End of Interrupt Mode .............................................. 159

5.8.5 Masking Interrupts ............................................................................... 1595.8.5.1 Masking on an Individual Interrupt Request................................ 1595.8.5.2 Special Mask Mode.................................................................. 160

5.8.6 Steering PCI Interrupts ......................................................................... 1605.9 Advanced Programmable Interrupt Controller (APIC) (D31:F0) .............................. 160

5.9.1 Interrupt Handling................................................................................ 1605.9.2 Interrupt Mapping ................................................................................ 1615.9.3 PCI/PCI Express* Message-Based Interrupts ............................................ 1625.9.4 IOxAPIC Address Remapping ................................................................. 1625.9.5 External Interrupt Controller Support ...................................................... 162

5.10 Serial Interrupt (D31:F0) ................................................................................. 1625.10.1 Start Frame......................................................................................... 1635.10.2 Data Frames........................................................................................ 1635.10.3 Stop Frame ......................................................................................... 1635.10.4 Specific Interrupts Not Supported Using SERIRQ ...................................... 1645.10.5 Data Frame Format .............................................................................. 164

5.11 Real Time Clock (D31:F0)................................................................................. 1655.11.1 Update Cycles...................................................................................... 1655.11.2 Interrupts ........................................................................................... 1665.11.3 Lockable RAM Ranges ........................................................................... 1665.11.4 Century Rollover .................................................................................. 1665.11.5 Clearing Battery-Backed RTC RAM .......................................................... 166

5.12 Processor Interface (D31:F0) ............................................................................ 1685.12.1 Processor Interface Signals and VLW Messages ........................................ 168

5.12.1.1 INIT (Initialization) ................................................................. 1685.12.1.2 FERR# (Numeric Coprocessor Error).......................................... 1695.12.1.3 NMI (Non-Maskable Interrupt) .................................................. 1695.12.1.4 Processor Power Good (PROCPWRGD) ....................................... 169

5.12.2 Dual-Processor Issues........................................................................... 1695.12.2.1 Usage Differences ................................................................... 169

5.12.3 Virtual Legacy Wire (VLW) Messages....................................................... 1705.13 Power Management ......................................................................................... 170

5.13.1 Features ............................................................................................. 1705.13.2 PCH and System Power States ............................................................... 1715.13.3 System Power Planes............................................................................ 1735.13.4 SMI#/SCI Generation ........................................................................... 173

5.13.4.1 PCI Express* SCI.................................................................... 1755.13.4.2 PCI Express* Hot-Plug............................................................. 175

5.13.5 C-States ............................................................................................. 1765.13.6 Dynamic PCI Clock Control (Mobile Only)................................................. 176

5.13.6.1 Conditions for Checking the PCI Clock........................................ 1765.13.6.2 Conditions for Maintaining the PCI Clock .................................... 1765.13.6.3 Conditions for Stopping the PCI Clock ........................................ 1765.13.6.4 Conditions for Re-Starting the PCI Clock .................................... 177

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5.13.6.5 LPC Devices and CLKRUN# .......................................................1775.13.7 Sleep States ........................................................................................177

5.13.7.1 Sleep State Overview...............................................................1775.13.7.2 Initiating Sleep State ...............................................................1775.13.7.3 Exiting Sleep States.................................................................1785.13.7.4 PCI Express* WAKE# Signal and PME Event Message ...................1805.13.7.5 Sx-G3-Sx, Handling Power Failures............................................1805.13.7.6 Deep Sx.................................................................................181

5.13.8 Event Input Signals and Their Usage .......................................................1825.13.8.1 PWRBTN# (Power Button) ........................................................1825.13.8.2 RI# (Ring Indicator) ................................................................1845.13.8.3 PME# (PCI Power Management Event) .......................................1845.13.8.4 SYS_RESET# Signal ................................................................1845.13.8.5 THRMTRIP# Signal ..................................................................184

5.13.9 ALT Access Mode ..................................................................................1855.13.9.1 Write Only Registers with Read Paths in ALT Access Mode.............1865.13.9.2 PIC Reserved Bits....................................................................1885.13.9.3 Read Only Registers with Write Paths in ALT Access Mode.............188

5.13.10System Power Supplies, Planes, and Signals.............................................1885.13.10.1Power Plane Control with SLP_S3#,

SLP_S4#, SLP_S5#, SLP_A# and SLP_LAN#...............................1885.13.10.2SLP_S4# and Suspend-To-RAM Sequencing................................1895.13.10.3PWROK Signal ........................................................................1895.13.10.4BATLOW# (Battery Low) (Mobile Only).......................................1895.13.10.5SLP_LAN# Pin Behavior............................................................1905.13.10.6RTCRST# and SRTCRST#.........................................................1905.13.10.7SUSPWRDNACK/SUSWARN#/GPIO30 Pin Behavior ......................191

5.13.11Legacy Power Management Theory of Operation .......................................1915.13.11.1APM Power Management (Desktop Only) ....................................1915.13.11.2Mobile APM Power Management (Mobile Only) .............................192

5.13.12Reset Behavior .....................................................................................1925.14 System Management (D31:F0) ..........................................................................194

5.14.1 Theory of Operation ..............................................................................1945.14.1.1 Detecting a System Lockup.......................................................1945.14.1.2 Handling an Intruder ...............................................................1945.14.1.3 Detecting Improper Flash Programming......................................1955.14.1.4 Heartbeat and Event Reporting using SMLink/SMBus....................195

5.14.2 TCO Modes ..........................................................................................1965.14.2.1 TCO Legacy/Compatible Mode...................................................1965.14.2.2 Advanced TCO Mode................................................................197

5.15 General Purpose I/O (D31:F0) ...........................................................................1985.15.1 Power Wells .........................................................................................1985.15.2 SMI# SCI and NMI Routing ....................................................................1985.15.3 Triggering............................................................................................1985.15.4 GPIO Registers Lockdown ......................................................................1985.15.5 Serial POST Codes over GPIO .................................................................199

5.15.5.1 Theory of Operation.................................................................1995.15.5.2 Serial Message Format .............................................................200

5.16 SATA Host Controller (D31:F2, F5).....................................................................2015.16.1 SATA 6 Gb/s Support ............................................................................2025.16.2 SATA Feature Support ...........................................................................2025.16.3 Theory of Operation ..............................................................................203

5.16.3.1 Standard ATA Emulation...........................................................2035.16.3.2 48-Bit LBA Operation ...............................................................203

5.16.4 SATA Swap Bay Support ........................................................................2035.16.5 Hot Plug Operation................................................................................2035.16.6 Function Level Reset Support (FLR).........................................................204

5.16.6.1 FLR Steps...............................................................................2045.16.7 Intel Rapid Storage Technology Configuration.........................................204

5.16.7.1 Intel Rapid Storage Technology RAID Option ROM .....................2055.16.8 Intel Smart Response Technology .........................................................2055.16.9 Power Management Operation ................................................................206

5.16.9.1 Power State Mappings..............................................................2065.16.9.2 Power State Transitions............................................................2065.16.9.3 SMI Trapping (APM).................................................................207

5.16.10SATA Device Presence ...........................................................................2075.16.11SATA LED ............................................................................................208

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5.16.12AHCI Operation.................................................................................... 2085.16.13SGPIO Signals ..................................................................................... 209

5.16.13.1Mechanism ............................................................................ 2095.16.13.2Message Format ..................................................................... 2105.16.13.3LED Message Type .................................................................. 2105.16.13.4SGPIO Waveform.................................................................... 212

5.16.14External SATA...................................................................................... 2135.17 High Precision Event Timers.............................................................................. 213

5.17.1 Timer Accuracy .................................................................................... 2135.17.2 Interrupt Mapping ................................................................................ 2145.17.3 Periodic vs. Non-Periodic Modes ............................................................. 2145.17.4 Enabling the Timers.............................................................................. 2155.17.5 Interrupt Levels ................................................................................... 2155.17.6 Handling Interrupts .............................................................................. 2165.17.7 Issues Related to 64-Bit Timers with 32-Bit Processors.............................. 216

5.18 USB EHCI Host Controllers (D29:F0 and D26:F0)................................................. 2175.18.1 EHC Initialization.................................................................................. 217

5.18.1.1 BIOS Initialization................................................................... 2175.18.1.2 Driver Initialization ................................................................. 2175.18.1.3 EHC Resets ............................................................................ 217

5.18.2 Data Structures in Main Memory............................................................. 2175.18.3 USB 2.0 Enhanced Host Controller DMA................................................... 2185.18.4 Data Encoding and Bit Stuffing............................................................... 2185.18.5 Packet Formats .................................................................................... 2185.18.6 USB 2.0 Interrupts and Error Conditions.................................................. 218

5.18.6.1 Aborts on USB 2.0-Initiated Memory Reads ................................ 2195.18.7 USB 2.0 Power Management .................................................................. 219

5.18.7.1 Pause Feature ........................................................................ 2195.18.7.2 Suspend Feature..................................................................... 2195.18.7.3 ACPI Device States ................................................................. 2195.18.7.4 ACPI System States ................................................................ 220

5.18.8 USB 2.0 Legacy Keyboard Operation ....................................................... 2205.18.9 USB 2.0 Based Debug Port .................................................................... 220

5.18.9.1 Theory of Operation ............................................................... 2215.18.10EHCI Caching....................................................................................... 2255.18.11Intel USB Pre-Fetch Based Pause ......................................................... 2255.18.12Function Level Reset Support (FLR) ........................................................ 225

5.18.12.1FLR Steps .............................................................................. 2255.18.13USB Overcurrent Protection ................................................................... 226

5.19 Integrated USB 2.0 Rate Matching Hub .............................................................. 2275.19.1 Overview ............................................................................................ 2275.19.2 Architecture......................................................................................... 227

5.20 xHCI Controller (D20:F0) ................................................................................. 2275.21 SMBus Controller (D31:F3) ............................................................................... 228

5.21.1 Host Controller..................................................................................... 2285.21.1.1 Command Protocols ................................................................ 229

5.21.2 Bus Arbitration..................................................................................... 2325.21.3 Bus Timing .......................................................................................... 233

5.21.3.1 Clock Stretching ..................................................................... 2335.21.3.2 Bus Time Out (The PCH as SMBus Master) ................................. 233

5.21.4 Interrupts / SMI#................................................................................. 2335.21.5 SMBALERT# ........................................................................................ 2345.21.6 SMBus CRC Generation and Checking...................................................... 2345.21.7 SMBus Slave Interface .......................................................................... 235

5.21.7.1 Format of Slave Write Cycle ..................................................... 2365.21.7.2 Format of Read Command........................................................ 2375.21.7.3 Slave Read of RTC Time Bytes .................................................. 2395.21.7.4 Format of Host Notify Command ............................................... 240

5.22 Thermal Management ...................................................................................... 2415.22.1 Thermal Sensor ................................................................................... 241

5.22.1.1 Internal Thermal Sensor Operation............................................ 2415.22.2 PCH Thermal Throttling ......................................................................... 2425.22.3 Thermal Reporting Over System Management Link 1 Interface (SMLink1) .... 243

5.22.3.1 Supported Addresses............................................................... 2445.22.3.2 I2C Write Commands to the Intel ME ....................................... 2455.22.3.3 Block Read Command.............................................................. 2455.22.3.4 Read Data Format................................................................... 247

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5.22.3.5 Thermal Data Update Rate........................................................2475.22.3.6 Temperature Comparator and Alert............................................2475.22.3.7 BIOS Set Up ...........................................................................2495.22.3.8 SMBus Rules...........................................................................2495.22.3.9 Case for Considerations............................................................250

5.23 Intel High Definition Audio Overview (D27:F0)...................................................2525.23.1 Intel High Definition Audio Docking (Mobile Only)....................................252

5.23.1.1 Dock Sequence .......................................................................2525.23.1.2 Exiting D3/CRST# When Docked ...............................................2535.23.1.3 Cold Boot/Resume from S3 When Docked...................................2545.23.1.4 Undock Sequence....................................................................2545.23.1.5 Normal Undock .......................................................................2545.23.1.6 Surprise Undock......................................................................2555.23.1.7 Interaction between Dock/Undock and Power Management States .2555.23.1.8 Relationship between HDA_DOCK_RST# and HDA_RST#..............255

5.24 Intel ME and Intel ME Firmware 8.0 ...............................................................2565.24.1 Intel ME Requirements ........................................................................257

5.25 Serial Peripheral Interface (SPI) ........................................................................2585.25.1 SPI Supported Feature Overview ............................................................258

5.25.1.1 Non-Descriptor Mode ...............................................................2585.25.1.2 Descriptor Mode......................................................................258

5.25.2 Flash Descriptor ...................................................................................2595.25.2.1 Descriptor Master Region .........................................................261

5.25.3 Flash Access ........................................................................................2625.25.3.1 Direct Access Security..............................................................2625.25.3.2 Register Access Security ..........................................................262

5.25.4 Serial Flash Device Compatibility Requirements ........................................2635.25.4.1 PCH SPI Based BIOS Requirements............................................2635.25.4.2 Integrated LAN Firmware SPI Flash Requirements........................2635.25.4.3 Intel Management Engine Firmware SPI Flash Requirements .......2635.25.4.4 Hardware Sequencing Requirements ..........................................264

5.25.5 Multiple Page Write Usage Model.............................................................2655.25.5.1 Soft Flash Protection................................................................2655.25.5.2 BIOS Range Write Protection ....................................................2665.25.5.3 SMI# Based Global Write Protection...........................................266

5.25.6 Flash Device Configurations ...................................................................2665.25.7 SPI Flash Device Recommended Pinout....................................................2665.25.8 Serial Flash Device Package ...................................................................267

5.25.8.1 Common Footprint Usage Model ................................................2675.25.8.2 Serial Flash Device Package Recommendations ...........................267

5.26 Fan Speed Control Signals (Server/Workstation Only)...........................................2685.26.1 PWM Outputs (Server/Workstation Only) .................................................2685.26.2 TACH Inputs (Server/Workstation Only)...................................................268

5.27 Feature Capability Mechanism ...........................................................................2685.28 PCH Display Interfaces and Intel Flexible Display Interconnect.............................269

5.28.1 Analog Display Interface Characteristics...................................................2705.28.1.1 Integrated RAMDAC.................................................................2705.28.1.2 DDC (Display Data Channel) .....................................................271

5.28.2 Digital Display Interfaces .......................................................................2715.28.2.1 LVDS (Mobile only)..................................................................2715.28.2.2 High Definition Multimedia Interface ..........................................2735.28.2.3 Digital Video Interface* (DVI*) .................................................2745.28.2.4 DisplayPort* ...........................................................................2755.28.2.5 Embedded DisplayPort* ...........................................................2755.28.2.6 DisplayPort* Aux Channel.........................................................2755.28.2.7 DisplayPort* Hot-Plug Detect (HPD)...........................................2765.28.2.8 Integrated Audio over HDMI and DisplayPort* .............................2765.28.2.9 Intel Serial Digital Video Out (Intel SDVO)..............................276

5.28.3 Mapping of Digital Display Interface Signals .............................................2775.28.4 Multiple Display Configurations ...............................................................2795.28.5 High-bandwidth Digital Content Protection* (HDCP*).................................2815.28.6 Intel Flexible Display Interconnect ........................................................281

5.29 Intel Virtualization Technology ........................................................................2815.29.1 Intel VT-d Objectives ..........................................................................2825.29.2 Intel VT-d Features Supported..............................................................2825.29.3 Support for Function Level Reset (FLR) in PCH ..........................................2825.29.4 Virtualization Support for PCHs IOxAPIC..................................................282

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5.29.5 Virtualization Support for High Precision Event Timer (HPET)...................... 2836 Ballout Definition................................................................................................... 285

6.1 Desktop PCH Ballout ........................................................................................ 2856.2 Mobile PCH Ballout .......................................................................................... 2976.3 Mobile SFF PCH Ballout .................................................................................... 309

7 Package Information ............................................................................................. 3237.1 Desktop PCH package ...................................................................................... 3237.2 Mobile PCH Package......................................................................................... 3257.3 Mobile SFF PCH Package................................................................................... 327

8 Electrical Characteristics ....................................................................................... 3298.1 Thermal Specifications ..................................................................................... 329

8.1.1 Desktop Storage Specifications and Thermal Design Power (TDP) ............... 3298.1.2 Mobile Storage Specifications and Thermal Design Power (TDP).................. 329

8.2 Absolute Maximum Ratings............................................................................... 3308.3 PCH Power Supply Range ................................................................................. 3318.4 General DC Characteristics ............................................................................... 3318.5 Display DC Characteristics ................................................................................ 3448.6 AC Characteristics ........................................................................................... 3468.7 Power Sequencing and Reset Signal Timings ....................................................... 3628.8 Power Management Timing Diagrams................................................................. 3658.9 AC Timing Diagrams ........................................................................................ 370

9 Register and Memory Mapping............................................................................... 3819.1 PCI Devices and Functions................................................................................ 3829.2 PCI Configuration Map ..................................................................................... 3839.3 I/O Map ......................................................................................................... 383

9.3.1 Fixed I/O Address Ranges ..................................................................... 3839.3.2 Variable I/O Decode Ranges .................................................................. 386

9.4 Memory Map................................................................................................... 3879.4.1 Boot-Block Update Scheme.................................................................... 389

10 Chipset Configuration Registers............................................................................. 39110.1 Chipset Configuration Registers (Memory Space) ................................................. 391

10.1.1 RPCRoot Port Configuration Register .................................................... 39310.1.2 RPFNRoot Port Function Number and Hide for PCI

Express* Root Ports Register ................................................................. 39410.1.3 FLRSTATFunction Level Reset Pending Status Register............................ 39510.1.4 TRSRTrap Status Register................................................................... 39610.1.5 TRCRTrapped Cycle Register ............................................................... 39610.1.6 TWDRTrapped Write Data Register....................................................... 39710.1.7 IOTRnI/O Trap Register (03) ............................................................. 39710.1.8 V0CTLVirtual Channel 0 Resource Control Register ................................. 39810.1.9 V0STSVirtual Channel 0 Resource Status Register .................................. 39810.1.10V1CTLVirtual Channel 1 Resource Control Register ................................. 39910.1.11V1STSVirtual Channel 1 Resource Status Register .................................. 39910.1.12RECRoot Error Command Register ....................................................... 39910.1.13LCAPLink Capabilities Register ............................................................. 40010.1.14LCTLLink Control Register ................................................................... 40010.1.15LSTSLink Status Register.................................................................... 40110.1.16TCTLTCO Configuration Register .......................................................... 40110.1.17D31IPDevice 31 Interrupt Pin Register.................................................. 40210.1.18D30IPDevice 30 Interrupt Pin Register.................................................. 40310.1.19D29IPDevice 29 Interrupt Pin Register.................................................. 40310.1.20D28IPDevice 28 Interrupt Pin Register.................................................. 40310.1.21D27IPDevice 27 Interrupt Pin Register.................................................. 40510.1.22D26IPDevice 26 Interrupt Pin Register.................................................. 40510.1.23D25IPDevice 25 Interrupt Pin Register.................................................. 40510.1.24D22IPDevice 22 Interrupt Pin Register.................................................. 40610.1.25D20IPDevice 20 Interrupt Pin Register.................................................. 40610.1.26D31IRDevice 31 Interrupt Route Register ............................................. 40710.1.27D29IRDevice 29 Interrupt Route Register ............................................. 40810.1.28D28IRDevice 28 Interrupt Route Register ............................................. 40910.1.29D27IRDevice 27 Interrupt Route Register ............................................. 41010.1.30D26IRDevice 26 Interrupt Route Register ............................................. 41110.1.31D25IRDevice 25 Interrupt Route Register ............................................. 412

10 Datasheet

10.1.32D22IRDevice 22 Interrupt Route Register ..............................................41310.1.33D20IRDevice 20 Interrupt Route Register ..............................................41410.1.34OICOther Interrupt Control Register .....................................................41510.1.35PRSTSPower and Reset Status Register.................................................41610.1.36PM_CFGPower Management Configuration Register.................................41710.1.37DEEP_S3_POLDeep Sx From S3 Power Policies Register ..........................41810.1.38DEEP_S4_POLDeep Sx From S4 Power Policies Register ..........................41810.1.39DEEP_S5_POLDeep Sx From S5 Power Policies Register ..........................41810.1.40PMSYNC_CFGPMSYNC Configuration .....................................................41910.1.41RCRTC Configuration Register..............................................................41910.1.42HPTCHigh Precision Timer Configuration Register ...................................42010.1.43GCSGeneral Control and Status Register ...............................................42010.1.44BUCBacked Up Control Register ...........................................................42210.1.45FDFunction Disable Register ................................................................42310.1.46CGClock Gating Register .....................................................................42510.1.47FDSWFunction Disable SUS Well Register ..............................................42610.1.48DISPBDFDisplay Bus, Device and Function

Initialization Register ............................................................................42610.1.49FD2Function Disable 2 Register............................................................42710.1.50MISCCTLMiscellaneous Control Register ................................................42710.1.51USBOCM1Overcurrent MAP Register 1...................................................42810.1.52USBOCM2Overcurrent MAP Register 2...................................................42910.1.53RMHWKCTLRate Matching Hub Wake Control Register .............................430

11 PCI-to-PCI Bridge Registers (D30:F0)....................................................................43311.1 PCI Configuration Registers (D30:F0) .................................................................433

11.1.1 VID Vendor Identification Register (PCI-PCID30:F0).............................43411.1.2 DID Device Identification Register (PCI-PCID30:F0) .............................43411.1.3 PCICMDPCI Command Register (PCI-PCID30:F0).................................43411.1.4 PSTSPCI Status Register (PCI-PCID30:F0) ..........................................43511.1.5 RIDRevision Identification Register (PCI-PCID30:F0)............................43711.1.6 CCClass Code Register (PCI-PCID30:F0).............................................43711.1.7 PMLTPrimary Master Latency Timer Register

(PCI-PCID30:F0)................................................................................43711.1.8 HEADTYPHeader Type Register (PCI-PCID30:F0) .................................43811.1.9 BNUMBus Number Register (PCI-PCID30:F0) ......................................43811.1.10SMLTSecondary Master Latency Timer Register

(PCI-PCID30:F0)................................................................................43811.1.11IOBASE_LIMITI/O Base and Limit Register

(PCI-PCID30:F0)................................................................................43911.1.12SECSTSSecondary Status Register (PCI-PCID30:F0) ............................44011.1.13MEMBASE_LIMITMemory Base and Limit Register

(PCI-PCID30:F0)................................................................................44111.1.14PREF_MEM_BASE_LIMITPrefetchable Memory Base

and Limit Register (PCI-PCID30:F0) .....................................................44111.1.15PMBU32Prefetchable Memory Base Upper 32 Bits

Register (PCI-PCID30:F0) ...................................................................44211.1.16PMLU32Prefetchable Memory Limit Upper 32 Bits

Register (PCI-PCID30:F0) ...................................................................44211.1.17CAPPCapability List Pointer Register (PCI-PCID30:F0) ..........................44211.1.18INTRInterrupt Information Register (PCI-PCID30:F0) ...........................44211.1.19BCTRLBridge Control Register (PCI-PCID30:F0)...................................44311.1.20SPDHSecondary PCI Device Hiding Register

(PCI-PCID30:F0)................................................................................44411.1.21DTCDelayed Transaction Control Register

(PCI-PCID30:F0)................................................................................44511.1.22BPSBridge Proprietary Status Register

(PCI-PCID30:F0)................................................................................44611.1.23BPCBridge Policy Configuration Register

(PCI-PCID30:F0)................................................................................44711.1.24SVCAPSubsystem Vendor Capability Register

(PCI-PCID30:F0)................................................................................44811.1.25SVIDSubsystem Vendor IDs Register (PCI-PCID30:F0) .........................448

12 Gigabit LAN Configuration Registers ......................................................................44912.1 Gigabit LAN Configuration Registers

(Gigabit LAN D25:F0) ...................................................................................449

Datasheet 11

12.1.1 VIDVendor Identification Register (Gigabit LAND25:F0).......................................................................... 450

12.1.2 DIDDevice Identification Register (Gigabit LAND25:F0).......................................................................... 450

12.1.3 PCICMDPCI Command Register(Gigabit LAND25:F0).......................................................................... 451

12.1.4 PCISTSPCI Status Register (Gigabit LAND25:F0).......................................................................... 452

12.1.5 RIDRevision Identification Register (Gigabit LAND25:F0).......................................................................... 453

12.1.6 CCClass Code Register (Gigabit LAND25:F0).......................................................................... 453

12.1.7 CLSCache Line Size Register (Gigabit LAND25:F0).......................................................................... 453

12.1.8 PLTPrimary Latency Timer Register (Gigabit LAND25:F0).......................................................................... 453

12.1.9 HEADTYPHeader Type Register (Gigabit LAND25:F0).......................................................................... 453

12.1.10MBARAMemory Base Address Register A (Gigabit LAND25:F0).......................................................................... 454

12.1.11MBARBMemory Base Address Register B(Gigabit LAND25:F0).......................................................................... 454

12.1.12MBARCMemory Base Address Register C(Gigabit LAND25:F0).......................................................................... 455

12.1.13SVIDSubsystem Vendor ID Register(Gigabit LAND25:F0).......................................................................... 455

12.1.14SIDSubsystem ID Register(Gigabit LAND25:F0).......................................................................... 455

12.1.15ERBAExpansion ROM Base Address Register(Gigabit LAND25:F0).......................................................................... 455

12.1.16CAPPCapabilities List Pointer Register (Gigabit LAND25:F0).......................................................................... 456

12.1.17INTRInterrupt Information Register(Gigabit LAND25:F0).......................................................................... 456

12.1.18MLMGMaximum Latency/Minimum Grant Register(Gigabit LAND25:F0).......................................................................... 456

12.1.19CLIST1Capabilities List Register 1(Gigabit LAND25:F0).......................................................................... 456

12.1.20PMCPCI Power Management Capabilities Register (Gigabit LAND25:F0).......................................................................... 457

12.1.21PMCSPCI Power Management Control and StatusRegister (Gigabit LAND25:F0) ............................................................. 458

12.1.22DRData Register (Gigabit LAND25:F0).......................................................................... 459

12.1.23CLIST2Capabilities List Register 2(Gigabit LAND25:F0).......................................................................... 459

12.1.24MCTLMessage Control Register(Gigabit LAND25:F0).......................................................................... 459

12.1.25MADDLMessage Address Low Register(Gigabit LAND25:F0).......................................................................... 460

12.1.26MADDHMessage Address High Register(Gigabit LAND25:F0).......................................................................... 460

12.1.27MDATMessage Data Register(Gigabit LAND25:F0).......................................................................... 460

12.1.28FLRCAPFunction Level Reset Capability(Gigabit LAND25:F0).......................................................................... 460

12.1.29FLRCLVFunction Level Reset Capability Length and Version Register (Gigabit LAND25:F0) .................................................. 461

12.1.30DEVCTRLDevice Control Register (Gigabit LAND25:F0)......................... 46112.2 Gigabit LAN Capabilities and Status Registers (CSR)............................................. 462

12.2.1 GBECSR1Gigabit Ethernet Capabilities and Status Register 1 ................... 46212.2.2 GBECSR2Gigabit Ethernet Capabilities and Status Register 2 ................... 46312.2.3 GBECSR3Gigabit Ethernet Capabilities and Status Register 3 ................... 46312.2.4 GBECSR4Gigabit Ethernet Capabilities and Status Register 4 ................... 46312.2.5 GBECSR5Gigabit Ethernet Capabilities and Status Register 5 ................... 46412.2.6 GBECSR6Gigabit Ethernet Capabilities and Status Register 6 ................... 46412.2.7 GBECSR7Gigabit Ethernet Capabilities and Status Register 7 ................... 464

12 Datasheet

12.2.8 GBECSR8Gigabit Ethernet Capabilities and Status Register 8....................46512.2.9 GBECSR9Gigabit Ethernet Capabilities and Status Register 9....................465

13 LPC Interface Bridge Registers (D31:F0) ...............................................................46713.1 PCI Configuration Registers (LPC I/FD31:F0) ....................................................467

13.1.1 VIDVendor Identification Register (LPC I/FD31:F0) ..............................46813.1.2 DIDDevice Identification Register (LPC I/FD31:F0)...............................46813.1.3 PCICMDPCI COMMAND Register (LPC I/FD31:F0).................................46913.1.4 PCISTSPCI Status Register (LPC I/FD31:F0)........................................46913.1.5 RIDRevision Identification Register (LPC I/FD31:F0) ............................47013.1.6 PIProgramming Interface Register (LPC I/FD31:F0) .............................47013.1.7 SCCSub Class Code Register (LPC I/FD31:F0) .....................................47013.1.8 BCCBase Class Code Register (LPC I/FD31:F0)....................................47113.1.9 PLTPrimary Latency Timer Register (LPC I/FD31:F0) ............................47113.1.10HEADTYPHeader Type Register (LPC I/FD31:F0) ..................................47113.1.11SSSub System Identifiers Register (LPC I/FD31:F0).............................47113.1.12CAPPCapability List Pointer Register (LPC I/FD31:F0) ...........................47213.1.13PMBASEACPI Base Address Register (LPC I/FD31:F0)...........................47213.1.14ACPI_CNTLACPI Control Register (LPC I/F D31:F0) .............................47313.1.15GPIOBASEGPIO Base Address Register (LPC I/F D31:F0) .....................47313.1.16GCGPIO Control Register (LPC I/F D31:F0) ........................................47413.1.17PIRQ[n]_ROUTPIRQ[A,B,C,D] Routing Control Register

(LPC I/FD31:F0) ................................................................................47513.1.18SIRQ_CNTLSerial IRQ Control Register

(LPC I/FD31:F0) ................................................................................47613.1.19PIRQ[n]_ROUTPIRQ[E,F,G,H] Routing Control Register

(LPC I/FD31:F0) ................................................................................47713.1.20LPC_IBDFIOxAPIC Bus:Device:Function

(LPC I/FD31:F0) ................................................................................47713.1.21LPC_HnBDF HPET n Bus:Device:Function

(LPC I/FD31:F0) ................................................................................47813.1.22LPC_I/O_DECI/O Decode Ranges Register

(LPC I/FD31:F0) ................................................................................47913.1.23LPC_ENLPC I/F Enables Register (LPC I/FD31:F0) ................................48013.1.24GEN1_DECLPC I/F Generic Decode Range 1 Register

(LPC I/FD31:F0) ................................................................................48113.1.25GEN2_DECLPC I/F Generic Decode Range 2 Register

(LPC I/FD31:F0) ................................................................................48113.1.26GEN3_DECLPC I/F Generic Decode Range 3 Register

(LPC I/FD31:F0) ................................................................................48213.1.27GEN4_DECLPC I/F Generic Decode Range 4 Register

(LPC I/FD31:F0) ................................................................................48213.1.28ULKMC USB Legacy Keyboard / Mouse

Control Register(LPC I/FD31:F0) ..........................................................48313.1.29LGMR LPC I/F Generic Memory Range Register

(LPC I/FD31:F0) ................................................................................48413.1.30BIOS_SEL1BIOS Select 1 Register

(LPC I/FD31:F0) ................................................................................48513.1.31BIOS_SEL2BIOS Select 2 Register

(LPC I/FD31:F0) ................................................................................48613.1.32BIOS_DEC_EN1BIOS Decode Enable

Register (LPC I/FD31:F0) ....................................................................48713.1.33BIOS_CNTLBIOS Control Register

(LPC I/FD31:F0) ................................................................................48913.1.34FDCAPFeature Detection Capability ID Register

(LPC I/FD31:F0) ................................................................................49013.1.35FDLENFeature Detection Capability Length Register

(LPC I/FD31:F0) ................................................................................49013.1.36FDVERFeature Detection Version Register

(LPC I/FD31:F0) ................................................................................49013.1.37FVECIDXFeature Vector Index Register

(LPC I/FD31:F0) ................................................................................49013.1.38FVECDFeature Vector Data Register

(LPC I/FD31:F0) ................................................................................49113.1.39Feature Vector Space ............................................................................491

13.1.39.1FVEC0Feature Vector Register 0 .............................................49113.1.39.2FVEC1Feature Vector Register 1 .............................................492

Datasheet 13

13.1.39.3FVEC2Feature Vector Register 2 ............................................. 49213.1.39.4FVEC3Feature Vector Register 3 ............................................. 492

13.1.40RCBARoot Complex Base Address Register (LPC I/FD31:F0)................................................................................ 493

13.2 DMA I/O Registers........................................................................................... 49413.2.1 DMABASE_CADMA Base and Current Address Registers .......................... 49513.2.2 DMABASE_CCDMA Base and Current Count Registers ............................. 49613.2.3 DMAMEM_LPDMA Memory Low Page Registers....................................... 49613.2.4 DMACMDDMA Command Register ........................................................ 49713.2.5 DMASTADMA Status Register .............................................................. 49713.2.6 DMA_WRSMSKDMA Write Single Mask Register...................................... 49813.2.7 DMACH_MODEDMA Channel Mode Register ........................................... 49813.2.8 DMA Clear Byte Pointer Register............................................................. 49913.2.9 DMA Master Clear Register .................................................................... 49913.2.10DMA_CLMSKDMA Clear Mask Register .................................................. 49913.2.11DMA_WRMSKDMA Write All Mask Register ............................................ 500

13.3 Timer I/O Registers ......................................................................................... 50013.3.1 TCWTimer Control Word Register......................................................... 50113.3.2 SBYTE_FMTInterval Timer Status Byte Format Register........................... 50313.3.3 Counter Access Ports Register ................................................................ 504

13.4 8259 Interrupt Controller (PIC) Registers ........................................................... 50413.4.1 Interrupt Controller I/O MAP .................................................................. 50413.4.2 ICW1Initialization Command Word 1 Register........................................ 50513.4.3 ICW2Initialization Command Word 2 Register........................................ 50613.4.4 ICW3Master Controller Initialization Command

Word 3 Register ................................................................................... 50613.4.5 ICW3Slave Controller Initialization Command

Word 3 Register ................................................................................... 50713.4.6 ICW4Initialization Command Word 4 Register........................................ 50713.4.7 OCW1Operational Control Word 1 (Interrupt Mask)

Register .............................................................................................. 50813.4.8 OCW2Operational Control Word 2 Register............................................ 50813.4.9 OCW3Operational Control Word 3 Register............................................ 50913.4.10ELCR1Master Controller Edge/Level Triggered Register ........................... 51013.4.11ELCR2Slave Controller Edge/Level Triggered Register ............................. 511

13.5 Advanced Programmable Interrupt Controller (APIC)............................................ 51213.5.1 APIC Register Map................................................................................ 51213.5.2 INDIndex Register ............................................................................. 51213.5.3 DATData Register .............................................................................. 51313.5.4 EOIREOI Register .............................................................................. 51313.5.5 IDIdentification Register ..................................................................... 51413.5.6 VERVersion Register .......................................................................... 51413.5.7 REDIR_TBLRedirection Table Register................................................... 515

13.6 Real Time Clock Registers................................................................................. 51713.6.1 I/O Register Address Map...................................................................... 51713.6.2 Indexed Registers ................................................................................ 518

13.6.2.1 RTC_REGARegister A ............................................................ 51913.6.2.2 RTC_REGBRegister B (General Configuration) .......................... 52013.6.2.3 RTC_REGCRegister C (Flag Register) ...................................... 52113.6.2.4 RTC_REGDRegister D (Flag Register) ...................................... 521

13.7 Processor Interface Registers ............................................................................ 52213.7.1 NMI_SCNMI Status and Control Register............................................... 52213.7.2 NMI_ENNMI Enable (and Real Time Clock Index)

Register .............................................................................................. 52313.7.3 PORT92Init Register........................................................................... 52313.7.4 COPROC_ERRCoprocessor Error Register .............................................. 52313.7.5 RST_CNTReset Control Register........................................................... 524

13.8 Power Management Registers ........................................................................... 52513.8.1 Power Management PCI Configuration Registers

(PMD31:F0) ...................................................................................... 52513.8.1.1 GEN_PMCON_1General PM Configuration 1 Register

(PMD31:F0) ........................................................................ 52613.8.1.2 GEN_PMCON_2General PM Configuration 2 Register

(PMD31:F0) ........................................................................ 52713.8.1.3 GEN_PMCON_3General PM Configuration 3 Register

(PMD31:F0) ........................................................................ 528

14 Datasheet

13.8.1.4 GEN_PMCON_LOCKGeneral Power Management Configuration Lock Register..........................................................................531

13.8.1.5 BM_BREAK_EN_2 Register #2 (PMD31:F0) ..............................53113.8.1.6 BM_BREAK_EN Register (PMD31:F0).......................................53213.8.1.7 PMIRPower Management Initialization Register (PMD31:F0).....53313.8.1.8 GPIO_ROUTGPIO Routing Control Register

(PMD31:F0) .........................................................................53313.8.2 APM I/O Decode Register .......................................................................534

13.8.2.1 APM_CNTAdvanced Power Management Control Port Register .....53413.8.2.2 APM_STSAdvanced Power Management Status Port Register ......534

13.8.3 Power Management I/O Registers ...........................................................53513.8.3.1 PM1_STSPower Management 1 Status Register.........................53513.8.3.2 PM1_ENPower Management 1 Enable Register ..........................53813.8.3.3 PM1_CNTPower Management 1 Control Register .......................53913.8.3.4 PM1_TMRPower Management 1 Timer Register .........................54013.8.3.5 GPE0_STSGeneral Purpose Event 0 Status Register...................54013.8.3.6 GPE0_ENGeneral Purpose Event 0 Enables Register...................54313.8.3.7 SMI_ENSMI Control and Enable Register..................................54513.8.3.8 SMI_STSSMI Status Register..................................................54713.8.3.9 ALT_GP_SMI_ENAlternate GPI SMI Enable Register ...................54913.8.3.10ALT_GP_SMI_STSAlternate GPI SMI Status Register..................55013.8.3.11GPE_CNTLGeneral Purpose Control Register .............................55013.8.3.12DEVACT_STS Device Activity Status Register...........................55113.8.3.13PM2_CNTPower Management 2 Control Register .......................551

13.9 System Management TCO Registers ...................................................................55213.9.1 TCO_RLDTCO Timer Reload and Current Value Register...........................55213.9.2 TCO_DAT_INTCO Data In Register .......................................................55313.9.3 TCO_DAT_OUTTCO Data Out Register...................................................55313.9.4 TCO1_STSTCO1 Status Register...........................................................55313.9.5 TCO2_STSTCO2 Status Register...........................................................55513.9.6 TCO1_CNTTCO1 Control Register .........................................................55613.9.7 TCO2_CNTTCO2 Control Register .........................................................55713.9.8 TCO_MESSAGE1 and TCO_MESSAGE2 Registers .......................................55713.9.9 TCO_WDCNTTCO Watchdog Control Register .........................................55813.9.10SW_IRQ_GENSoftware IRQ Generation Register.....................................55813.9.11TCO_TMRTCO Timer Initial Value Register .............................................558

13.10 General Purpose I/O Registers...........................................................................55913.10.1GPIO_USE_SELGPIO Use Select Register...............................................56013.10.2GP_IO_SELGPIO Input/Output Select Register .......................................56013.10.3GP_LVLGPIO Level for Input or Output Register......................................56113.10.4GPO_BLINKGPO Blink Enable Register...................................................56113.10.5GP_SER_BLINKGP Serial Blink Register .................................................56213.10.6GP_SB_CMDSTSGP Serial Blink Command

Status Register.....................................................................................56213.10.7GP_SB_DATAGP Serial Blink Data Register ............................................56313.10.8GPI_NMI_ENGPI NMI Enable Register ...................................................56313.10.9GPI_NMI_STSGPI NMI Status Register ..................................................56313.10.10GPI_INVGPIO Signal Invert Register....................................................56413.10.11GPIO_USE_SEL2GPIO Use Select 2 Register .........................................56413.10.12GP_IO_SEL2GPIO Input/Output Select 2 Register .................................56513.10.13GP_LVL2GPIO Level for Input or Output 2 Register................................56513.10.14GPIO_USE_SEL3GPIO Use Select 3 Register .........................................56613.10.15GP_IO_SEL3GPIO Input/Output Select 3 Register .................................56613.10.16GP_LVL3GPIO Level for Input or Output 3 Register................................56713.10.17GP_RST_SEL1 GPIO Reset Select Register ..........................................56713.10.18GP_RST_SEL2 GPIO Reset Select Register ..........................................56813.10.19GP_RST_SEL3 GPIO Reset Select Register ..........................................568

14 SATA Controller Registers (D31:F2) .......................................................................56914.1 PCI Configuration Registers (SATAD31:F2) ........................................................569

14.1.1 VIDVendor Identification Register (SATAD31:F2) ..................................57114.1.2 DIDDevice Identification Register (SATAD31:F2) ..................................57114.1.3 PCICMDPCI Command Register (SATAD31:F2) .....................................57114.1.4 PCISTS PCI Status Register (SATAD31:F2) .........................................57214.1.5 RIDRevision Identification Register (SATAD31:F2) ................................57314.1.6 PIProgramming Interface Register (SATAD31:F2) .................................573

14.1.6.1 When Sub Class Code Register (D31:F2:Offset 0Ah) = 01h ...........573

Datasheet 15

14.1.6.2 When Sub Class Code Register (D31:F2:Offset 0Ah) = 04h .......... 57314.1.6.3 When Sub Class Code Register (D31:F2:Offset 0Ah) = 06h .......... 574

14.1.7 SCCSub Class Code Register (SATAD31:F2) ........................................ 57414.1.8 BCCBase Class Code Register

(SATAD31:F2SATAD31:F2) ................................................................ 57414.1.9 PMLTPrimary Master Latency Timer Register

(SATAD31:F2).................................................................................... 57414.1.10HTYPEHeader Type Register

(SATAD31:F2).................................................................................... 57514.1.11PCMD_BARPrimary Command Block Base Address

Register (SATAD31:F2) ....................................................................... 57514.1.12PCNL_BARPrimary Control Block Base Address Register

(SATAD31:F2).................................................................................... 57514.1.13SCMD_BARSecondary Command Block Base Address

Register (SATAD31:F2) ....................................................................... 57614.1.14SCNL_BARSecondary Control Block Base Address

Register (SATAD31:F2) ....................................................................... 57614.1.15BARLegacy Bus Master Base Address Register

(SATAD31:F2).................................................................................... 57714.1.16ABAR/SIDPBAAHCI Base Address Register/Serial ATA

Index Data Pair Base Address (SATAD31:F2).......................................... 57714.1.16.1When SCC is not 01h............................................................... 57714.1.16.2When SCC is 01h .................................................................... 578

14.1.17SVIDSubsystem Vendor Identification Register (SATAD31:F2).................................................................................... 578

14.1.18SIDSubsystem Identification Register (SATAD31:F2) ............................ 57814.1.19CAPCapabilities Pointer Register (SATAD31:F2).................................... 57814.1.20INT_LNInterrupt Line Register (SATAD31:F2) ...................................... 57914.1.21INT_PNInterrupt Pin Register (SATAD31:F2)........................................ 57914.1.22IDE_TIMIDE Timing Register (SATAD31:F2) ........................................ 57914.1.23SIDETIMSlave IDE Timing Register (SATAD31:F2)................................ 58014.1.24SDMA_CNTSynchronous DMA Control Register

(SATAD31:F2).................................................................................... 58014.1.25SDMA_TIMSynchronous DMA Timing Register

(SATAD31:F2).................................................................................... 58014.1.26IDE_CONFIGIDE I/O Configuration Register

(SATAD31:F2).................................................................................... 58114.1.27PIDPCI Power Management Capability Identification

Register (SATAD31:F2) ....................................................................... 58114.1.28PCPCI Power Management Capabilities Register

(SATAD31:F2).................................................................................... 58214.1.29PMCSPCI Power Management Control and Status

Register (SATAD31:F2) ....................................................................... 58214.1.30MSICIMessage Signaled Interrupt Capability

Identification Register (SATAD31:F2) .................................................... 58314.1.31MSIMCMessage Signaled Interrupt Message

Control Register (SATAD31:F2) ............................................................ 58314.1.32MSIMA Message Signaled Interrupt Message

Address Register (SATAD31:F2) ........................................................... 58514.1.33MSIMDMessage Signaled Interrupt Message

Data Register (SATAD31:F2)................................................................ 58514.1.34MAPAddress Map Register (SATAD31:F2) ............................................ 58614.1.35PCSPort Control and Status Register (SATAD31:F2).............................. 58714.1.36SCLKCGSATA Clock Gating Control Register .......................................... 58914.1.37SGCSATA General Configuration Register.............................................. 59014.1.38SATACR0SATA Capability Register 0 (SATAD31:F2) .............................. 59114.1.39SATACR1SATA Capability Register 1 (SATAD31:F2) .............................. 59114.1.40FLRCIDFLR Capability ID Register (SATAD31:F2) ................................. 59214.1.41FLRCLVFLR Capability Length and Version Register (SATAD31:F2).......... 59214.1.42FLRCFLR Control Register (SATAD31:F2)............................................. 59314.1.43ATCAPM Trapping Control Register (SATAD31:F2) ................................ 59314.1.44ATSAPM Trapping Status Register (SATAD31:F2) ................................. 59414.1.45SPScratch Pad Register (SATAD31:F2)................................................ 59414.1.46BFCSBIST FIS Control/Status Register (SATAD31:F2) ........................... 59514.1.47BFTD1BIST FIS Transmit Data1 Register (SATAD31:F2) ........................ 59714.1.48BFTD2BIST FIS Transmit Data2 Register (SATAD31:F2) ........................ 597

14.2 Bus Master IDE I/O Registers (D31:F2) .............................................................. 598

16 Datasheet

14.2.1 BMIC[P,S]Bus Master IDE Command Register (D31:F2) ..........................59914.2.2 BMIS[P,S]Bus Master IDE Status Register (D31:F2)................................60014.2.3 BMID[P,S]Bus Master IDE Descriptor Table Pointer

Register (D31:F2).................................................................................60114.2.4 AIRAHCI Index Register (D31:F2) ........................................................60114.2.5 AIDRAHCI Index Data Register (D31:F2)...............................................601

14.3 Serial ATA Index/Data Pair Superset Registers.....................................................60214.3.1 SINDXSerial ATA Index Register (D31:F2).............................................60214.3.2 SDATASerial ATA Data Register (D31:F2) ..............................................603

14.3.2.1 PxSSTSSerial ATA Status Register (D31:F2) .............................60314.3.2.2 PxSCTLSerial ATA Control Register (D31:F2) ............................60414.3.2.3 PxSERRSerial ATA Error Register (D31:F2)...............................605

14.4 AHCI Registers (D31:F2) ..................................................................................60614.4.1 AHCI Generic Host Control Registers (D31:F2)..........................................607

14.4.1.1 CAPHost Capabilities Register (D31:F2) ...................................60714.4.1.2 GHCGlobal PCH Control Register (D31:F2) ...............................60914.4.1.3 ISInterrupt Status Register (D31:F2) ......................................61014.4.1.4 PIPorts Implemented Register (D31:F2) ..................................61114.4.1.5 VSAHCI Version Register (D31:F2)..........................................61214.4.1.6 EM_LOCEnclosure Management Location Register (D31:F2)........61214.4.1.7 EM_CTRLEnclosure Management Control Register (D31:F2)........61214.4.1.8 CAP2HBA Capabilities Extended Register..................................61314.4.1.9 RSTFIntel RST Feature Capabilities Register ...........................614

14.4.2 Port Registers (D31:F2).........................................................................61614.4.2.1 PxCLBPort [5:0] Command List Base Address Register

(D31:F2)................................................................................61914.4.2.2 PxCLBUPort [5:0] Command List Base Address Upper

32-Bits Register (D31:F2) ........................................................61914.4.2.3 PxFBPort [5:0] FIS Base Address Register (D31:F2) ..................61914.4.2.4 PxFBUPort [5:0] FIS Base Address Upper 32-Bits

Register (D31:F2) ...................................................................62014.4.2.5 PxISPort [5:0] Interrupt Status Register (D31:F2) ....................62014.4.2.6 PxIEPort [5:0] Interrupt Enable Register (D31:F2) ....................62214.4.2.7 PxCMDPort [5:0] Command Register (D31:F2) .........................62314.4.2.8 PxTFDPort [5:0] Task File Data Register (D31:F2).....................62614.4.2.9 PxSIGPort [5:0] Signature Register (D31:F2) ...........................62614.4.2.10PxSSTSPort [5:0] Serial ATA Status Register (D31:F2) ..............62714.4.2.11PxSCTL Port [5:0] Serial ATA Control Register (D31:F2) ...........62814.4.2.12PxSERRPort [5:0] Serial ATA Error Register (D31:F2) ................62914.4.2.13PxSACTPort [5:0] Serial ATA Active Register (D31:F2)...............63114.4.2.14PxCIPort [5:0] Command Issue Register (D31:F2) ....................631

15 SATA Controller Registers (D31:F5) .......................................................................63315.1 PCI Configuration Registers (SATAD31:F5) ........................................................633

15.1.1 VIDVendor Identification Register (SATAD31:F5) .................................63415.1.2 DIDDevice Identification Register (SATAD31:F5) .................................63415.1.3 PCICMDPCI Command Register (SATAD31:F5) .....................................63515.1.4 PCISTS PCI Status Register (SATAD31:F5) .........................................63615.1.5 RIDRevision Identification Register (SATAD31:F5) ...............................63615.1.6 PIProgramming Interface Register (SATAD31:F5) .................................63715.1.7 SCCSub Class Code Register (SATAD31:F5) .........................................63715.1.8 BCCBase Class Code Register

(SATAD31:F5SATAD31:F5).................................................................63715.1.9 PMLTPrimary Master Latency Timer Register

(SATAD31:F5) ....................................................................................63815.1.10PCMD_BARPrimary Command Block Base Address

Register (SATAD31:F5)........................................................................63815.1.11PCNL_BARPrimary Control Block Base Address Register

(SATAD31:F5) ....................................................................................63815.1.12SCMD_BARSecondary Command Block Base Address

Register (SATA D31:F5) .......................................................