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5/23/13 3:ntels Silvermont Architecture Targets Low-Power Applications

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Intels Silvermont Architecture Targets Low-Power ApplicationsWilliam Wong

Tue, 2013-05-07 10:45

The Intel Silvermont architecture will be delivered on the companys 22-nm Tri-

Gate transistor technology (see Moores Law Continues With 22-nm 3D

Transistors at electronicdesign.com). Silvermont increases peak performance by

factor of three over current Atom technology while reducing power requirements b

a factor for five when delivering the same performance. The architecture targets

applications that Arm has currently dominated. It will also take over in areas wher

the Atom has been strong, including microservers.

Intel is also promising to churn out a new version every year, which would beat th

current tick-tock cycle. A number of Silvermont system-on-chip solutions should be available before the end of the year.

The Avoton series targets microservers. Rangeley is optimized for communication infrastructure applications. The Baytra

version of Silvermont targets larger mobile devices like tablets. And, Merrifield is for smaller devices like smart phones.

The Silvermont is designed to scale to eight cores. One big change is the move to out-of-order execution (see the figure).

Intel has plenty of experience here with its higher-end processors. This will improve single-core performance. Out-of-ord

execution is already used by AMDs Jaguar core (see Low-Power, Single-Chip APU Delivers High Performance at

electronicdesign.com) and Arms Cortex-A15 (see Arm Delivers More Multicore Multimedia at electronicdesign.com)
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Silvermont will implement more instructions in hardware. It has improved branch prediction support including prediction

of indirect branches. Also, its loop stream buffer allows the core to shut down the fetch and decode sections if the loop

instructions fit into the buffer, improving performance while reducing power requirements.

Intel is following the pack in moving from symmetric multithreading (SMT), also known as hyperthreading, to a thread pe

core. This provides a more balanced execution and is better for real-time embedded applications, but it means that a quad-

core chip is needed to run four threads. Four cores will be faster than a pair of hyperthreaded cores because a singlehyperthreaded core only added a fraction of a cores performance to the mix.

Intel will pair two cores with a shared L2 cache. Cores also connect to an in-die interconnect (IDI). The IDI is the same

that is used on the latest Intel Core processors. It is important in reducing latency with the on-chip memory controller.

Older Atoms had a front-side bus (FSB) interface that was slower and did not allow the chips to benefit from the on-chip

memory controller. The IDI and processor core clocks are decoupled, allowing more flexibility when the cores are slowed

down.

There will be new instructions with the architecture including SSE4.1 and 4.2 extensions and AES-NI encryption. High-

end Intel chips will still have an edge on vector calculations with AVX (see Intels AVX Scales To 1024-Bit Vector Math

at electronicdesign.com). AVX tends to be overkill for most embedded applications.

On the other hand, improved virtualization support is part of Silvermont, such as full support for Intels VT-x2 suite

including extended page table support. This will be handy for microservers and enable better security support using

separation hypervisor kernels on smart phones.

Silvermonts other high-end features include TSC-deadline timer support, which is the third APIC mode that had only bee

found in newer Intel chips. Real-time instruction tracing is also supported. The facility is very useful in real-time
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debugging.

The chips will have more power modes. Silvermont will also balance power utilization across the CPU and graphics cores

(GFX) in boost mode, which is similar to the Turbo Boost mode on the Core series. The CPUs then will be able to

accelerate when the GFX is not running full tilt.

The chips will support the C6 deep sleep mode. In this case, the core is completely shut down. Developers can utilize a

range of C6 substates that also control how the L2 cache operates. It can even be shut down.

Silvermont takes direct aim at the 32-bit and future 64-bit Arm-based chips. Intel has the advantage of a tried-and-true 64

bit, virtualized architecture. It can easily run all popular operating systems including Windows, Linux, and variants like

Android. Developers will have a more limited selection of chips from Intel compared to the plethora of options and custom

chips built around Arms architectures.

Silvermont looks to be Intels most disruptive technology if it can displace Arm in even a few major accounts. Intel has

definitely raised the performance bar while reducing power consumption.

Source URL:http://electronicdesign.com/microprocessors/intel-s-silvermont-architecture-targets-low-power-application
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