interconnection network organization and its impact on performance

8/7/2019 Interconnection Network Organization and Its Impact on Performance

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Interconnection Network Organization

and its Impact on Performance and

Cost in Shared Memory Multiprocessor

By Sunil Kim, Alexander, Veidenbaum



Introduction

This paper presents a detailed comparative

study of:

different network organizations

behavior and

design trade-offs

with respect to:

performance and

cost for a shared memory multiprocessor



Presentation Plan

We have selected following sub topics to

present in this short duration presentation:

System model

Performance metrics

Experiment and analysis

Conclusion



System Model

In this study onlyinterconnection

network

organization isvaried.

Scalar

Processor



Shared Memory and Cache

Shared memory is physically distributed and

directly addressable by each processor

Memory module operation is pipelined to

perform a memory access

Memory cycle time depends on the message

length and data path width

All messages have an 8-byte message header

All non-shared data and instructions are

stored in a separate local memory



Scalar Processor

Standard RISC processor

Instruction execute in one cycle with the

exception of:

integer multiplication and division

floating-point addition, multiplication and division



Crossbar Switch

non-blocking switch usednumber of queues equal to

the number of output ports

message header containsthe destination tag

minimum switch latency

three cycles



Networks

Three different

topologies are studied:

a multidimensional

torus

a multistage shuffle

exchange (MSX)



Networksa single stage shuffle

exchange (SSX)A node is connected to a

network using multiplexor

and de-multiplexor module

DMUX

Wires connecting switches incur a one clock

cycle delay

The DMUX causes an additional one cycle delay

and also has infinite queues



Performance Metrics

Read miss latency is used as the main

performance metric

Read miss latency is the sum of the delays

experienced in the network memory and

cache interface as shown in the followingequation:

L= Ds x PL + Dm + Ta



Performance Metrics L= Ds x PL + Dm + Ta, where

L: Read miss latency Ds: Stage delay

PL: Average message path length hops for around trip to memory

Dm: Memory delay, Dm = Tmw + Lml

Tmw: Memory waiting time

Lml: Memory module latency cycles

Ta: Assembly time at a cache seen by a processor,

Ta=128 / Wc

Wc: Channel width



Experiments and Analysis

System and network performance of the three

network topologies is studied varying switch

size, channel width and system size

� Switch sizes of 4x4, 8x8 and 16x16 channel

widths of 1,2,4 and 8 bytes and system sizes of 64, 128 and 256 processors are examined



Stage Delay (Ds)



Memory Waiting Time (Tmw)



Memory Waiting Time (only Tmw)



Relative Read Miss Latency Difference Performance

difference between

networks for system

size of 128

SSX/TORUS is

defined as:

(LTORUS-LSSX)/LTORUS*100

LSSX are the read

miss latency of SSX



Conclusion Read miss latency used as main performance

metric Switch size and channel width are two very

important network organization parametersaffecting Ds and Wm

For fixed switch size and channel width MSXnetworks performed better than the othernetworks

Increasing channel width resulted in the largestperformance gain for SSX networks, increase hassmallest effect in multi-dimensional TORUSnetworks



Conclusion (Cont)

Finally MSX networks was the best network

topology (ignoring cost)

Otherwise SSX network was the best network

topology

TORUS networks was seriously limited by

longer average message path length

interconnection network organization and its impact on performance

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