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Interleaved hybrid control concept for multiphase DC-DC converters
G. Tsolaridis, J. Biela Power Electronic Systems Laboratory, ETH Zürich
Physikstrasse 3, 8092 Zürich, Switzerland
Interleaved Hybrid Control Concept forMultiphase DC-DC Converters
Georgios Tsolaridis and Juergen Biela
Laboratory for High Power Electronic Systems
ETH Zurich, Switzerland
Email: [email protected]
Abstract—DC-DC converters with high dynamic performanceand low current ripple, able to drive highly fluctuating loadsare nowadays required in a range of applications (e.g. accel-erators, plasma research, fusion reactors). In order to fulfillthe requirements of these applications, advanced current controlconcepts have to be employed to harness the full potential of thedesigned topology. In this paper, an interleaved hybrid currentcontrol concept is introduced for multiphase DC-DC converters.The controller combines the time optimal transient behaviorof the hysteretic control with the constant switching frequencyof the PI control along with a phase-shifting controller. Thiscombination results in a highly dynamic performance duringtransients, excellent disturbance rejection capability during loaddisturbances, and minimum ripple during steady state withoutincreasing excessively the complexity of the controller. Theinteractions between the hysteretic controller, the PI controllerand the phase-shifting controller are described and the ability ofthe control scheme to fully utilize the converter’s capabilities isvalidated through detailed simulations.
I. INTRODUCTION
High power, solid state, dynamically controllable current
sources are considered to be a key component for various
modern applications, such as plasma generation [1] or beam
deflecting equipment used in accelerators [2] as well as for a
range of research activities, such as test equipment to facilitate
the development of next generation HVDC circuit breakers
for future grids [3]. Designing a flexible and highly dynamic
current source can be challenging and requires the combination
of an optimally designed power electronic converter topology
along with an advanced control concept that exploits the
converter’s full dynamic potential.
In [4] a novel current source topology was introduced which
is based on a multiphase interleaved buck-type converter for
shaping arbitrary current waveforms, connected in series to a
TABLE I: Parameters of the multiphase system
Output voltage vc 0V .. 400V
Output current iload 0A .. 400A
Upper voltage level V1 675V
Lower voltage level V2 125V
Load range @ iload Rload 0.1Ω .. 1.0Ω
Switching frequency fs 20kHz
Number of phases n 6
Phase inductance Li 250μH
Capacitance Cout 10μF
1C
2C
6 x interleaved
loadRoutCcv
LpR i
loadi
L,ii outi
1V
2V
1,iS
2,iS
Fig. 1: 6-phase interleaved two-level buck-type converter topology with splitDC link (V1 & V2), for improved load current dynamics at low output voltages.
Marx-type voltage generator, to generate high output voltages.
Multiphase interleaved buck converters are also widely used
in other industrial applications due to their simple, robust and
compact design [5]–[8].
In [1] and [4], such a multiphase topology was used,
where the focus was on the design and optimization of the
converter, for a current source application. The multiphase
interleaved operation of the current shaping converter ensures
low ripple in steady state while the small inductance value
of the buck converter results in a high dynamic capability.
However, with simple standard control concepts the achievable
current gradient and the robustness of the system under
dynamically changing loads is very limited. In order to fully
utilize the performance of such a multiphase converter (c.f.
Fig. 1-Table I), an improved current control strategy aimed
for multiphase DC-DC converters is presented in this paper.
The most widely used control approach for DC-DC convert-
ers is the average current control method, which was analyzed
for multiphase systems in [9]. This method makes use of the
information of the average current of each phase in order to
provide precise reference tracking while ensuring equal current
sharing even in case of parameter mismatches. However, the
maximum achievable bandwidth of this concept is limited due
to the inevitable closed-loop delays. The concept was applied
in multiphase converters implemented as a conventional PID
control [1] or as a state feedback control [10].
Another common control solution, that is usually preferred
due to its simplicity and its low-cost implementation, is
the peak current control [11]. However, in its conventional
978-1-5090-2998-3/17/$31.00 ©2017 IEEE 3069
implementation, its transient response is severely affected by
the need for slope compensation, which is required for stability
in a wide operating region [12].
In contrast, in [13] a hysteretic controller was used for
a multiphase DC-DC converter. Its simple implementation,
time-optimal response and excellent large signal properties
make it particularly attractive. However, in its conventional
form, it suffers from switching frequency jittering (that results
in imprecise interleaving), inaccurate reference tracking and
unequal current sharing [14], [15].
Other non-linear control schemes were also applied in mul-
tiphase DC-DC converters. In [16] a sliding mode controller
was employed for a two-phase interleaved boost converter in
voltage regulation mode showing promising results. However,
the conceptual complexity of the method makes it impractical,
as noted in [17]. An attractive current control scheme, opti-
mized for the interleaving of multiphase DC-DC converters
was introduced in [18] and [19]. This method allows excel-
lent transient performance, inherent stability and very good
disturbance-rejection capability. However, system uncertainties
could severely downgrade its precision and synchronization in
steady state.
In order to overcome these limitations, a hybrid control
concept has been introduced in [20] for single-phase DC-
DC converters and simulations proved its superiority over
benchmark solutions. Based on this concept, an interleaved
hybrid controller for multiphase DC-DC converters, aimed
to overcome the drawbacks of the aforementioned control
schemes without increasing significantly the complexity of the
control system, is presented in this paper.
In section II, the theoretical limits of the static and dynamic
performance of a multiphase interleaved buck-type converter
are defined. In section III, the interleaved hybrid control
concept is presented. Section IV shows simulation results of
a 6-phase interleaved buck-type converter operated with the
proposed controller under various transient scenarios.
II. THEORETICAL DYNAMIC LIMITS
In Fig. 1, a multiphase buck-type converter with split DC
link is shown. This topology is used as a case scenario in
this paper. The split DC-link topology is chosen because it
offers an improved controllability at low/zero current and
an increased step-down performance compared to a standard
buck converter. This section identifies the maximum dynamic
potential of the considered topology as well as its ideal steady
state current ripple, providing a benchmark for the controller’s
performance.
First, the steady state performance of the topology is stud-
ied. The duty cycle D in steady state as well as the peak-to-
peak module current ripple ΔiL,pp can be determined by:
D =V2 + Vc
V1 + V2
ΔiL,pp =V1 + V2
LfsD(1−D) (1)
where Vc is the average value of the instantaneous output
voltage vc. The output current ripple can be dramatically
reduced, by applying a 2πn phase shift between the modules.
0 50 100 150 200 250 300 350 4000
10
20
30
40
50
L,ppiModule ripple Δ
ppΔi
out,ppiConverter ripple Δ load,ppiLoad ripple Δ
Peak
-pea
k cu
rrent
ripp
le
(A)
out,pp,maxiΔ
out,pp,maxΔi= 6thrIΔ
Output voltage (V)cV
Fig. 2: Peak-to-peak module current ripple ΔiL,pp (black), converter outputcurrent ripple Δiout,pp (red) and load current ripple Δiload,pp for 1Ω load(blue-solid) and 0.1Ω load (blue-dashed). In addition, the maximum converteroutput current ripple Δiout,pp,max is shown (red-dashed) along with the currentthreshold ΔIthr (c.f. section III).
In this case, the converter output current ripple Δiout,pp is not
dependent on the RloadCout output network and is given by:
Di = D − 1
n�n ·D� Δiout,pp =
V1 + V2
LfsDi(1−Di) (2)
where �x� is the floor function of variable x. If the phases areinterleaved, the frequency of the current ripple at the output of
the converter, is n-times higher than the switching frequency
of the individual modules. As a worst case assumption, the
triangular converter current ripple is modelled as sinusoidal
current with an amplitude equal to the peak value of the
triangular ripple Δiout,pp at the frequency ωripple = 2πnfs. TheRloadCout network at the converter output acts as a first order
low pass filter and the load current ripple is given by:
Δiload,pp(ωripple) = Δiout,pp1√
1 + (RloadCoutωripple)2
(3)
The current ripple as a function of the output voltage is shown
in Fig. 2, assuming that the module currents are interleaved.
50 100 150 200 250 300 350 4000
4
8
12
16
20
~10
~8
refI
Fig. 3: Maximum load current gradient for different transients as a function ofthe reference current. Considered transients are: i) Step-up: 0→Iref ii) Step-down: Iref→0A. This figure sets the benchmark for the maximum dynamicperformance of the converter.
3070
The transient operation of the considered converter is gov-
erned by the system of differential equations in (4), where
Vin ∈ {V1,−V2}.⎡⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎣
diL,1dtdiL,2dt...
diL,ndtdvcdt
⎤⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎦=
⎡⎢⎢⎢⎢⎢⎢⎢⎢⎣
−Rp
L10 . . . 0 − 1
L1
0 −Rp
L2. . . 0 − 1
L2
... 0. . .
......
0 0 . . . −Rp
Ln− 1
Ln
1Cout
1Cout
. . . 1Cout
− 1RloadCout
⎤⎥⎥⎥⎥⎥⎥⎥⎥⎦
⎡⎢⎢⎢⎢⎢⎢⎣
iL,1
iL,2...
iL,n
vc
⎤⎥⎥⎥⎥⎥⎥⎦+
⎡⎢⎢⎢⎢⎢⎢⎢⎣
Vin
L1
Vin
L2
...Vin
Ln
0
⎤⎥⎥⎥⎥⎥⎥⎥⎦
(4)
An analytic solution gives only limited insight in the sys-
tem’s performance due to its complexity. Therefore, the system
is solved numerically and the load current gradient during a
step-up/down transient is given in Fig. 3 for different operating
conditions. According to Fig. 3, the maximum current gradient
of the studied converter ranges from 3A/μs to 16A/μs. There,the resistive load influences the gradient of the load current
because it changes the time constant of the output filter.
Furthermore, a step-down with low resistive load is slower
due to the low output voltage. In order to improve the worst
case step-down performance, an enhanced buck-type topology
with split DC-link has been introduced in [21] (c.f. Fig. 1).
Fig. 4 gives an overview of the trade-off between the
current gradient and the current ripple as a function of the
module inductance Li and the output capacitance Cout. The
depicted result assumes a 6-phase interleaved topology, with
a switching frequency of 20kHz and a nominal load of 1Ω
Additionally, by monitoring the change of the output volt-
age, the control system can detect load disturbances faster,
especially when a low output capacitance Cout is used (e.g.
current source applications), as highlighted in [20]. Since the
voltage derivative can be sensitive to noise, the weighted
voltage derivative acting as a low pass filter, is used:
dvc[k] = 0.5dvc[k − 1] + 0.5(vc[k]− vc[k − 1]) (5)
10 50 100 150 200 250 3001
3
5
7
9
11
13
15= 6, fs = 20kHzn
10A/μs
20A/μs
30A/μs
Studied converter
2%3%
Increased dynamics
Reducedripple
out
CC
apac
itanc
e
iLInductance
Fig. 4: Contour lines of load current gradient during a step-up 0A→400Awith a resistive load 1.0Ω (black-solid). In addition, the contour lines for worst
case ΔIload,pp(%) =ΔIload,pp
Imin(blue-dashed) are shown. For this calculation
a minimum operating current Imin = 100A is chosen.
0 50 100 150 200 250 300 350 400-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
=loadR
loadRLower
c,maxdv
c,maxdv= 10thrVΔ
cV
/dt
cdv
Fig. 5: Maximum steady state output voltage derivative dvc/dt calculated asin (5). The derivative depends on the load resistance and only the result forthe highest considered load resistance is shown (Rload = 1Ω). In addition,the maximum steady state value dvc,max (red-dashed) is used for the tuningof the voltage threshold ΔVthr (c.f. section III).
In steady state, the ripple of the output current iout is causingan output voltage ripple and the expected steady state voltage
derivative can be calculated based on (4). The result for the
studied converter is shown in Fig. 5, as a function of the output
voltage. The maximum steady state value dvc,max is used in
order to specify a voltage threshold (ΔVthr) which is later
introduced in the proposed control system (ΔVthr=10dvc,max).
III. INTERLEAVED HYBRID CONTROL OPERATION
In the previous section the theoretical limits of the selected
multiphase converter regarding its current ripple and its current
gradient are defined. If an ideal controller is used, the potential
of the topology can be capitalized both when it comes to its
dynamic as well as its steady state performance.
In general, the hysteretic controller provides excellent tran-
sient performance but particularly its digital implementation
suffers from switching frequency jittering that prevents the
interleaving of the module currents in steady state [15].
Moreover, its precision in steady state is severely downgraded
due to parasitic elements and sensing delays [20]. On the other
hand, the PI control ensures accurate current sharing between
the individual phases, precision in steady state and design sim-
plicity. Additionally, due to its constant switching frequency, it
can provide interleaved operation when it is combined with a
phase-shifting controller. However, its transient performance is
limited due to the unavoidable closed loop delays that decrease
the achievable bandwidth. Additionally, keeping the module
currents interleaved during transients prohibits the exploitation
of the full dynamic potential of the topology.
The hybrid combination of the aforementioned controllers
(PI & hysteretic), results in a control concept with excellent
transient as well as steady state performance. Fig. 6 gives
an overview of the proposed interleaved hybrid controller for
a 2-phase system, but the extension to an n-phase system
is straightforward, by adding identical slave modules. Each
module’s control system consists of an average current mode
(PI combined with phase-shifting controller) and an adaptive
hysteretic mode along with a supervisor that determines which
3071
Inductor
+ PWM
Band Calculation
Master
PI Controller
+- PWM
Adaptive Hysteretic Control
Average Current Control
+
h,1S
L,1V
Moving Average
Hysteretic Modulator
Reset
ResetCapacitor
outi
1L
1HL,1i
L,1i
∗swf
cv
∗swf
I∗
I
cv
cV
Inductor
+ PWM
Band Calculation
Slave
PI Controller
+- PWM
Adaptive Hysteretic Control
Average Current Control
+
h,2S
L,2V
Moving Average
Hysteretic Modulator
Reset
Reset
Reset 2L
2HL,2i
L,2i
∗swf
cv
slavef
I∗
I cV
Mas
ter
Mod
ule
Slav
e M
odul
e 1
+ +
Phase Shifting Control
∗swf
outC
loadi
Load
Moving Average
cV
sw∗f=avgf
sw∗f=avgf
sw∗6f=avgf
State Machine L,2i
cvI∗
outi
L,1i
L,2i
Phase Shift Measurement
L,1i
L,2i
Δf
Supervisor
Slav
e M
odul
e i
Load
ResetState
Machine L,1i
cvI∗
outi
Supervisor
Fig. 6: Schematic of the proposed interleaved hybrid control scheme. Twomodules are shown (master & slave). The slave module consists of: i) anaverage current mode controller (PI control and phase-shifting control) whichis enabled during steady state and ii) an adaptive hysteretic mode controllerwhich is enabled during transients. Note: The band calculation block of theslave module needs to measure the time-shift between its current and themaster’s current Δt in order to adapt the hysteresis band as in (9).
control mode is enabled. The next sections describe the
operation principle of each control mode and their interactions.
A. Steady State Operation
In steady state the average current mode is enabled, consist-
ing of a PI controller and a phase-shifting controller, as shown
in Fig. 6. It should be noted that any other average current
control scheme can be used (e.g. state feedback control etc.)
but here a PI controller is considered for simplicity. Since
the PI controller is a well-investigated concept this section
describes only the operation of the phase-shifting control.
At the start of each switching cycle, the relative phase
difference Δφ, between the master’s module current iL,master
and the slave’s module current iL,slave, is measured. As shown
in Fig. 7, Δφ=1 is defined such that iL,slave is lagging iL,master
by one switching period, while Δφ=−1 is defined such that
iL,slave is leading iL,master by one switching period. It is then
clear that: |Δφ| ≤ 1. Similarly, the relative reference phase
shift of each slave module Δφ∗ depends on the total number
of phases n and is given by:
Δφ∗ ∈{−n− 1
n, . . . ,− 1
n,1
n, . . . ,
n− 1
n
}(6)
The interleaving is achieved by adjusting the switching fre-
quency of the slave module fslave. A switching frequency
L,masteri L,slavei L,slave∗i
∗
(master)PWM (slave)PWM
0
1
D
φΔφΔ
0
(master)PWM counter
(slave)PWM counter
max∗cslavec
Mod
ule
curr
ent
t
t
t
Note: Smaller resolution
sw∗f
slavef
b)
a)
c)
Fig. 7: Operation of the phase-shifting controller. a) Master and slave modulecurrents b) Master and slave digital PWM c) Master and slave PWM counters.In this scenario, the measured phase-shift Δφ is smaller than the referencephase-shift Δφ∗ so the slave’s PWM maximum counter cslave is increasedaccording to (7), decreasing the switching frequency fslave, and shifting iL,slaveto its reference position i∗L,slave, within one period.
adjustment of a digital PWM, simply requires a change in the
resolution of its clock, as shown in Fig. 7b). This modification
is implemented with a change in the maximum value of the
counter of the slave’s PWM cslave compared to the reference
maximum counter value c∗max of the master’s PWM, as shown
in Fig. 7c). The value of cslave is then given by:
cslave = c∗max + (Δφ∗ −Δφ) c∗max (7)
With this method, the interleaving is ideally achieved within
one switching cycle. However, it should be noted that a distur-
bance is introduced in the converter output current iout duringthe switching cycle in which the resolution change occurs.
In order to avoid high disturbances, the switching frequency
change can be saturated. This means that more than one
switching cycles are required before achieving interleaving.
B. Transient Operation
The proposed interleaved hybrid controller makes use of the
excellent large signal properties of the hysteretic controller,
when a transient is detected according to the mode-shifting
conditions described in the next section. As a case scenario,
the operation of the interleaved hybrid controller under a step
reference change is described and shown in Fig. 8 for a system
with two modules.
At t=t0: A reference change is detected and the hysteretic
controller is enabled, i.e. the status of the signal Sh,1 for the
master and Sh,2 for the slave (Fig. 6) is changed from 0 to 1.
Initially, the hysteresis band is set to a low value (H0) in order
to avoid a large overshoot of the converter output current iout,since the interleaved operation is lost and the current ripples
of iL,1 and iL,2 add up. Setting the hysteresis band to a low
H0 value could cause a temporary increase in the switching
3072
t
t
t
ResetReset
c,ssV
0t 1t 2t 3t 4t 5t
cV
1,1S1,2S
Steady-state
(master)PWM (slave)PWM
b)
c)
d)
t
= 1h,2S
ssH
Δt
∗I
L,1i
0H
Hysteresis band
= 0h,2S= 0h,2S= 0h,1S = 1h,1S = 0h,1S
L,2i
2H1H
ΔH
a)
outi
out,maxiΔ
e)
t
Fig. 8: Operation of the interleaved hybrid controller during a step currentchange for a system with two modules: a) Master and slave module currents,b) Converter output current iout, c) Switching pulses of the upper switch of themaster and slave module, d) Average converter output voltage Vc and steadystate voltage Vc,ss and e) PWM counter of the master and slave module.
frequency that only lasts however for one switching cycle. The
initial band H0 can be set based on the maximum allowed
overshoot of the converter output current Δiout,max, as H0 =Δiout,max
n , since in the worst case the current ripples of all the
module currents add up. As shown in Fig. 8b, the maximum
limit of Δiout,max is not hit due to the small phase-shift between
iL,1 and iL,2. However, the ripple of iout is relatively large as
the interleaved operation is lost.
At t = t1: The current of the master module reaches its
peak value I∗+H0 for the second time and the average con-
verter output voltage Vc is almost settled. The hysteresis band
calculation block samples the average voltage Vc and updates
the hysteresis band of the master module to approximately its
steady state value Hss:
Hss =1
2Lfs
(1− V2 + Vc
V1 + V2
)(V2 + Vc) (8)
At t= t2: The slave’s current also reaches its peak value
I∗ + H0 and the time shift Δt between the two currents
is measured. The slave’s band calculation block then re-
calculates the hysteretic band of the slave module and adjusts
it by ΔH , in order to restore the interleaved operation of the
system in the next switching period. The adjustment ΔH can
be calculated based on (9), where Δt∗ is the ideal time shift
for interleaved operation.
ΔH = (Δt∗ −Δt)S1S2
S2 − S1
(9)
In (9), S1 and S2 are the slopes of the triangular current rise
and fall which are given in (10) for the considered converter.
S1 =V1 − Vc
LS2 =
−V2 − Vc
L(10)
At t = t3: The interleaved operation is achieved and the
hysteretic band of the slave becomes equal to the steady state
value Hss. It can be observed in Fig. 8b that the ripple of
iout reduces significantly after the adaptation. It should be
noted that possible inaccuracies in the phase-shift between
the module currents must be expected due to the non-ideal
characteristics of the hysteretic control and the fact that the
average output voltage Vc is affected by the band adaptations
(phase-coupling). However, the error is relatively small and is
corrected by the phase-shifting controller at steady state, as
previously described.
At t = t4: The master’s current reaches the lower limit
of the hysteresis band and Vc has settled, so the signal Sh,1
changes its status enabling the average current mode and the
PWM clock of the master module is reset.
At t=t5: The slave’s current reaches the lower limit of the
hysteresis band and the signal Sh,2 changes its status setting
the slave module to average current mode and the PWM clock
of the slave is reset.
C. Control Algorithm
The flowchart of the proposed adaptive hybrid controller
is shown in Fig. 9, where the states of the supervising state
machine and the step-by-step operation of the average mode
as well as the adaptive hysteretic mode are given. When the
system is at steady state the supervisor of each module checks
the mode-shifting conditions a)-c) (i.e. same for all modules)
[20].
a) |I∗[k]− I∗[k − 1]| ≤ ΔI∗
b) |iL − I∗| ≤ ΔIthr
c) |dvc| ≤ ΔVthr
If one of these conditions is violated, the supervisors change
their output signal Sh,i from 0 to 1 and all the modules enter
the hysteretic mode simultaneously.
Condition a) checks the reference current which is a known
input for the controller. The knowledge of the reference current
helps in distinguishing between fast transients that require the
use of the hysteretic mode and slower transients that can be
handled by the average current mode and therefore do not
result in temporary loss of the interleaved operation. More
details regarding the choice of ΔI∗ can be found in [20].
3073
(initialize, reset clks)Start
= 0h,iSAverage Current Mode
Controller
Slave Module ?
Phase-Shifting
PWM
FalseTrue
Conditionsa), b), c)
True False
Adaptive Hysteretic Mode = 1h,iS
Set
0H=H
= 0cyclesN
= 1cyclesN
> 1cyclesN
L,maxi=L,ii
Slave Module ?
Modulator
Conditionsi), ii), iii)
True False
True False
Set SetΔH=H ssH=H
L,mini=L,ii
cyclesNIncrease
False True
TrueFalse
Check cyclesN
Fig. 9: Flowchart of the interleaved hybrid controller. In average currentmode, the supervisor checks the conditions a)-c) based on the output convertercurrent iout, the weighted derivative dvc/dt and the reference current I∗. Inhysteretic mode, the supervisor checks the mode-shifting conditions i)-iii)based on the module current iL,i the number of hysteretic cycles Ncycles, andthe weighted derivative dvc/dt.
Conditions b) and c) check the output converter current ioutand the weighted voltage derivative dvc, that was introduced
in section II, in order to detect a possible violation of the
thresholds ΔIthr and ΔVthr, which could be caused by load
disturbances. The fine tuning of the thresholds ΔIthr and ΔVthr
depends on the requirements of the application and exemplary
configurations are shown in Fig. 2 and Fig. 5 [20].
When the control system is in adaptive hysteretic mode, the
supervisor of each module checks the mode-shifting conditions
i)-iii):
i) iL,i = iL,min = I∗−H
ii) Ncycles ≥ 2
iii) |dvc|<ΔVthr
If all of these conditions are met, the supervisors change
their output signal Sh,i from 1 to 0, so that the average current
mode is activated again and the integral part of the controller
along with the PWM clock are reset. In contrast to the previous
case, each module’s supervisor changes its output signal Sh,i
at a different time instant, as can be seen in Fig. 8 too.
Condition i) ensures that the mode-shifting happens at the
start of a new switching cycle and the sawtooth PWM counter
is reset as shown in Fig. 8e). In this way, the control output of
the average mode controller is immediately applied, turning
on Si,1 resulting in an increasing iL,i. Moreover, conditionii) checks the number of hysteretic cycles of the module.
As shown in Fig. 9 the adaptation of the hysteretic band
occurs when Ncycles = 1. Therefore, this condition ensures
that the adaptation has occurred before a mode-shift happens,
so the phase-shift of the module currents is near-optimal
before the controller can change to average current mode.
Finally, condition iii) ensures that the output voltage has
settled before the mode can be changed. The control output of
the average mode is almost at its steady state value and only
small adaptations are needed.
IV. SIMULATION RESULTS
For evaluating the performance of the proposed controller
time domain simulation results are presented for the consid-
ered topology, shown in Fig. 1. Fig. 10a) and Fig. 11a) show
the output current of the converter iout, as well as the load
current iload while Fig. 10b) and Fig. 11b) show the module
currents iL,i during a step-up and a step-down transient. The
maximum theoretically achievable current gradient for the
step-up/down was calculated in section II (10A/μs and 8A/μsrespectively). It can be seen that the usage of the hysteretic
control during the transient, fully exploits the potential of the
converter by generating a load current with the maximum
achievable gradient, verifying the time-optimal transient re-
sponse of the designed control system. Additionally, the initial
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8Time (ms)
0
100
200
300
400
500
Cur
rent
(A)
-50
0.25 0.3 0.35 0.4 0.45 0.5 0.55Time (ms)
385
400
415
Cur
rent
(A)
outi
loadi
∗I
A/μs~10
Mode-shifting
= 1hS = 0hS
Imperfect interleaving
Optimal ripple
-50
0
50
100
Cur
rent
(A)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8Time (ms)
30405060708090
100
Cur
rent
(A)
0.1 0.15 0.2 0.25Time (ms)
Hysteretic band adaptationMaster module
0H
ssH
= 0h,6S= 0h,5S
= 0h,1S
a)
b)
Disturbance due tophase-shifting
= 0hS
Fig. 10: a) Current waveforms during a step-up transient 0A→ 400A withnominal load (1Ω). The use of the hybrid controller ensures the generationof a load current with 10A/μs gradient, equal to the theoretical maximum,shown in Fig. 3. b) Module currents iL,i during the step-up.
3074
adaptation of the hysteretic band H0 (c.f. section III), results
in small initial overshoot in Fig. 10a) and Fig. 11a).
Moreover, in both figures the ability of the controller to
return to optimal interleaving shortly after the transient, is
emphasized. It should be noted that in both cases, the hys-
teretic band adaptation does not lead to an optimal interleaving
but it reduces significantly the current ripple. The non-ideal
interleaving occurs due to the non-idealities of the hysteretic
controller as well as due to the change of the output voltage
vc during the switching cycle. However, the use of the phase-
shifting control ensures that optimal interleaving is achieved
within one switching cycle, as soon as the controller returns
to average current mode.
In addition, Fig. 12 and Fig. 13 depict the performance of
the controller under sudden load changes from Rload = 1Ω to
Rload = 0.1Ω and Rload = 0.5Ω to Rload = 1Ω. In Fig. 12a) the
controller switches to hysteretic mode as soon as the voltage
derivative (Fig. 12b) exceeds the pre-set threshold value of
ΔVthr, which is set to be 10 times higher than the calculated
maximum steady state value duc,max, shown in Fig. 5. The
module current ripples initially add-up and result in a high
output current ripple. However, the output current is kept
within ±40A of its set value despite the major voltage change.
In Fig. 13, the voltage derivative constraint is not violated
(Fig. 13b) and the controller does not switch to the hysteretic
mode before the threshold current ΔIthr is violated. ΔIthr isset to be 6 times higher (48A) than the maximum expected
-100
0
100
200
300
400
500
Cur
rent
(A)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8Time (ms)
-30
0
30
Cur
rent
(A)
0.25 0.3 0.35 0.4 0.45 0.5 0.55Time (ms)
Mode-shifting
Imperfect interleaving
Optimal ripple
Disturbance due tophase-shifting
outi
loadi
∗I
= 1hS = 0hS
A/μs~8
-50
0
50
100
Cur
rent
(A)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8Time (ms)
0.15 0.2 0.25 0.3 0.35Time (ms)
-30
0
30
Cur
rent
(A)
0.125
Hysteretic band adaptationMaster module
ssH = 0h,1S= 0h,3S
a)
b)
= 1hS = 0hS
Fig. 11: a) Current waveforms during a step-down transient 400A→0A atnominal load (1Ω). The use of the hybrid controller ensures the generationof a load current with approximately 8A/μs gradient, equal to the theoreticalmaximum shown in Fig. 3. b) Module currents iL,i during the step-down.
0
100
200
300
400
500
Cur
rent
(A)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4Time (ms)
0.45 0.5
outi = 1hS = 0hS
Hysteretic band adaptationImperfect interleaving
0.05 0.1 0.15 0.2 0.25 0.3Time (ms)
405060708090
100110
Cur
rent
(A)
Hysteretic band adaptation
Master module0H
= 0h,6S3ΔH
ssH
= 0h,3S
thrΔI
0
100
200
300
400
450
Vol
tage
(V)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4Time (ms)
0.45 0.5
10-8-6-4-2024
0.05 0.1 0.15 0.2 0.25 0.3Time (ms)
thrΔV
a)
b)
= 1hS= 0hS = 0hS
Fig. 12: a) Current waveforms for a load step from Rload = 1Ω→ 0.1Ω,at t= 0.1ms b) Output voltage and weighted voltage derivative during theload disturbance. The violation of ΔVthr causes the controller to change tohysteretic mode immediately after the occurrence of the fault.
converter current ripple Δiout,pp,max (Fig. 2). In both Fig. 12
and Fig. 13 it should be highlighted that the oscillations that
arise during the transient result from the imperfect interleaving
and do not compromise the stability of the system, which is
inherently given due to the bounded nature of the hysteretic
controller.
Finally, the transient performance of the proposed controller
is compared with an optimally tuned multiphase PI controller,
in Fig. 14. It can be seen that the PI fails to exploit the full
potential of the topology as it is able to generate a converter
output current gradient of only 2.5A/μs compared to 14A/μsof the proposed method for the same transient. Furthermore,
the disturbance rejection performance of the two controllers
is compared for a load changes from Rload = 1Ω to Rload =0.1Ω based on the Integral of Absolute Error (IAE) index,
highlighting the superiority of the proposed control scheme.
V. CONCLUSION
In this paper, a new interleaved hybrid current controller
for DC-DC converters is presented. The controller makes
use of the hysteretic mode during transients for near-optimal
transient response and of the PI controller during steady
state for accuracy and precise interleaving. The performance
of the controller is evaluated with time domain simulations
and the capabilities of the controller are compared with
the theoretical maximum limits that the studied converter
topology can achieve. Furthermore, emphasis is laid on the
3075
0
100
200
300
400
500C
urre
nt (A
)
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4Time (ms)
0.45 0.5
outi= 1hS = 0hS
thrΔI
Hysteretic band adaptation
30405060708090
100110
Cur
rent
(A)
0.05 0.1 0.15 0.2 0.25 0.3Time (ms)
Hysteretic band adaptation
0H
= 0h,3SssH
= 0h,5S
150
200
250
300
350
400
450
Vol
tage
(V)
-1
0
1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4Time (ms)
0.45 0.5
0.05 0.1 0.15 0.2 0.25 0.3Time (ms)
a)
b)
= 3.2thrΔV
Fig. 13: a) Current waveforms for a load step from Rload = 0.5Ω→1Ω, att=0.1ms. The violation of ΔIthr causes the controller to change to hystereticmode. b) Voltage waveform and weighted voltage derivative during the loaddisturbance. The voltage threshold is not violated in this case.
fast detection and rejection of large signal load disturbances
as well as on minimizing the disturbance during the mode-
shifting instances between the different control modes. In
addition, the performance of the controller is compared with a
benchmark multiphase PI controller revealing the superiority
of the proposed concept. Finally it can be concluded that
the proposed controller manages to harness the full dynamic
potential of the topology, achieving minimum ripple in steady
Cur
rent
(A)
0 1 2 3 4 5 6Time (ms)
-100
0
100
200
300
400
500
600
700
IAE = 4.8
IAE = 26.8
Fig. 14: Comparison of transient and disturbance rejection performance of theproposed hybrid controller versus a benchmark multiphase PI controller, withoptimized gains (MATLAB optimization). At t = 4.1ms a load change fromRload = 1Ω to Rload = 0.1Ω occurs. The Integral of Absolute Error (IAE)index of each controller is noted on the graphs, calculated as:
∫∞t0
|e(t)|dt,where e(t) = I(t)− I∗ and t0 = 5ms in the simulated case.
state while maintaining a simple design which makes it
particularly attractive for multiphase DC-DC converters.
ACKNOWLEDGEMENT
The authors would like to thank the SCCER Furies/CTI
(project number: 25197.1 PFEN-I) and Ampegon AG for their
financial support.
REFERENCES
[1] C. Carstensen and J. Biela, “A three-level buck converter with a widevoltage operation range for hardware-in-the-loop test systems,” IEEETrans. on Power Electronics, 2016.
[2] E. Dallago, G. Venchi, S. Rossi, M. Pullia, T. Fowler, and M. Larsen,“The power supply for the beam chopper magnets of a medical syn-chrotron,” in 37th IEEE Power Electronics Spec. Conf., 2006.
[3] C. M. Franck, “HVDC circuit breakers: A review identifying futureresearch needs,” IEEE Trans. on Power Delivery, 2011.
[4] M. M. Walter, J. Biela, C. Carstensen, and C. M. Franck, “A new Methodfor Investigating the Arc Behaviour in HVDC Circuit Breakers basedon a novel Current Source,” 2012.
[5] D. Gerber and J. Biela, “Interleaving of a soft-switching boost converteroperated in boundary conduction mode,” IEEE Trans. on Plasma Sci-ence, vol. 43, no. 10, 2015.
[6] L. Ni, D. J. Patterson, and J. L. Hudgins, “High power current sensorlessbidirectional 16-phase interleaved DC-DC converter for hybrid vehicleapplication,” IEEE Trans. on Power Electronics, vol. 27, no. 3, 2012.
[7] N. Wassinger, S. Maestri, R. G. Retegui, J.M.Cravero, M. Benedetti, andD.Carrica, “Multiple-stage converter topology for high-precision high-current pulsed sources,” IEEE Trans. on Power Electr., vol. 26, 2011.
[8] M. Esteki, B. Poorali, E. Adib, and H. Farzanehfard, “Interleaved buckconverter with continuous input current, extremely low output currentripple, low switching losses, and improved step-down conversion ratio,”IEEE Trans. on Industrial Electronics, vol. 62, no. 8, 2015.
[9] R. Li, “Modeling average-current-mode-controlled multi-phase buckconverters,” in IEEE Power Electronics Spec. Conf., 2008.
[10] H. S. Bae, J. H. Yang, J. H. Lee, and B. H. Cho, “Digital state feedbackcontrol and feed-forward compensation for a parallel module DC-DCconverter using the pole placement technique,” in 23rd IEEE AppliedPower Electr. Conf. (APEC), 2008.
[11] L. Huber, B. T. Irving, and M. M. Jovanovic, “Closed-loop controlmethods for interleaved DCM/CCM boundary boost PFC converters,”in 24th IEEE Applied Power Electronics Conf. (APEC), 2009.
[12] Y. Qiu, J. Sun, M. Xu, K. Lee, and F. C. Lee, “Bandwidth improvementsfor peak-current controlled voltage regulators,” IEEE Trans. on PowerElectronics, vol. 22, no. 4, 2007.
[13] J. Abu-Qahouq, H. Mao, and I. Batarseh, “Multiphase voltage-modehysteretic controlled DC-DC converter with novel current sharing,” IEEETrans. on Power Electronics, vol. 19, no. 6, 2004.
[14] C. Song and J. L. Nilles, “Accuracy analysis of hysteretic current-modevoltage regulator,” in 20th IEEE Applied Power Electr. Conf., 2005.
[15] W. Stefanutti and P. Mattavelli, “Fully digital hysteresis modulationwith switching-time prediction,” IEEE Trans. on Industry Applications,vol. 42, no. 3, 2006.
[16] R. Giral, L. Martinez-Salamero, R. Leyva, and J. Maixe, “Sliding-modecontrol of interleaved boost converters,” IEEE Trans. on Circuits andSystems, vol. 47, no. 9, 2000.
[17] S. C. Tan, Y. M. Lai, and C. K. Tse, “General design issues of sliding-mode controllers in DC-DC converters,” IEEE Trans. on IndustrialElectronics, vol. 55, no. 3, 2008.
[18] M. Khazraei and M. Ferdowsi, “Modeling and analysis of projectedcross point control; a new current-mode-control approach,” IEEE Trans.on Industrial Electronics, vol. 60, no. 8, 2013.
[19] P. Antoszczuk, R. G. Retegui, M. Funes, and D. Carrica, “Optimizedimplementation of a current control algorithm for multiphase interleavedpower converters,” IEEE Trans. on Industrial Inform., vol. 10, 2014.
[20] G. Tsolaridis and J. Biela, “Hybrid control concept for highly dynamicbuck converter systems,” European Conf. on Power Electr. and Appl.(EPE), 2017.
[21] G. Tsolaridis and J. Biela, “Modular highly dynamic and ultra-low ripplearbitrary current source for plasma research,” in IEEE Pulsed PowerConf., 2017.
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