P R O D U C T B R I E F

IP00C755

Product Description

The IP00C755 has 2 independent channels of de-interlacer and scaler, both with PiP output. One of the great features of this device is the embedded frame memory function that can make the overall design easier to implement and reduce the footprint. It can also be used as a downscaling scaler from 4K to 1080P.

Features

Dual Input (2 out of 4 ports)30-bit RGB/YUV4:4:4, 20-bit YUV4:2:2, 10-bit YUV4:2:2 (BT656) @166MHz LV-CMOS (2-port) supporting dual (EVEN/ODD) and DDR input @160MHz high speed LVDS (2-port)/83MHz x 2 LVDS (1-port)Single Output (2 ports)30-bit RGB/YUV4:4:4, 20-bit YUV4:2:2, 10-bit YUV4:2:2 (BT656) @166MHz LV-CMOS (1-port)/166MHz high speed LVDS (2-port)/83MHz x2 LVDS (1-port)ScalingZoom/Shrink: Polyphase, 10bit/pixel, embedded ROM (64 sets)De-interlacerAll major cadences supported, motion adaptive filter based on Y, U, V

Image Quality Control • Color management• Uniformity correction (by region and per-pixel) • Bias/Gain/Gamma• H/V edge enhancement (9symbol)• Dithering for 10 or 8bit output

Horizontal Active Pixels2048 pixelsNoise Reduction3D (H, V, Temporal)/Mosquito/Block NR, chroma error filterImage ManipulationMirror/flip/90-degree image, vertical keystone, 2-ch overlay, alpha blending, color key blendingxvYCC/Bt-2020Fully supportedCPU Interface8-bit parallel/4-wire serial

Frame Memory　　　　　　DDR2-SDRAM 1Gbit embedded. No external memoryBit Map OSD256 color, OSD 90-degree rotation, OSD scroll Power Supply3.3V/1.8V/1.2V

Package 496-pin BGA (1.0mm pitch), 27mmx27mm

IP00C755 Block Diagram

Internal DDR2 Memory

Internal DDR2 Memory

InputCSC

TemporalFilter

De-interlacer

Zoom/Shrink

TimingControl

ImageQuality

InputCSC

TemporalFilter

De-interlacer

Zoom/Shrink

TimingControl

ImageQuality

OSD

OSD

Port 1(LVDS)

LVDS and/or LVCMOS

C755

Port 1(LVCMOS)

Dual Input De-interlacer/Scaler with Built-in Memory

Ch1Data

Select

Port 1(LVDS)

Port 1(LVCMOS)

Ch1Data

Select

OverlayOutput

DataSelect

IP00C755 Dual Input De-interlacer/Scaler with Built-in Memory

The information presented herein is subject to change and is intended for general information only. Copyright © 2015 i-Chips. All rights reserved. Printed in the USA. BR C755 1215

For more information please visit: www.i-chips.com or info@i-chips.co.jp

i-Chips Technology, Inc. • 1-2-6, Shioe Amagasaki Hyogo, 661-0976 Japan • Tel: 81-6-6492-7277 • Fax: 81-6-6492-7388

Application Diagrams

i-Chips Technology, Inc.

1920x1200(WUXGA)

Dual Input & Single Output System -PiP-

1 2

Dual Input & Dual Output System

4K to 1080p Downscaling System

1080p

1

2

4K 30Hz(4K 60Hz)

CPU

LVCMOS

LVCMOS

DDR

1920x1200(WUXGA)

CPU

Rx C755

C755

480i,720p,

1080p/i

CPU

C755

HDMI, DP,Analog VGA, etc.

HDMI, DP,Analog VGA, etc.

Rx

Rx

1

2

LVCMOS

480i,720p,

1080p/iHDMI, DP,

Analog VGA, etc.

Rx

Rx

1

2