international journal of digital application ...ijdacr.com/uploads/papers/nip.pdfthe ip of ahb...

IJDACR

ISSN: 2319-4863

International Journal of Digital Application & Contemporary research

Website: www.ijdacr.com (Volume 3, Issue 9, April 2015)

Design of High Speed AHB Memory Controller with

Verilog

Nibedita Panda

M.Tech. Scholar

Digital Electronics

Chouksey Engineering College, Bilaspur (India)

[email protected]

Prof. Rahul Gedam

Electronics and Communication Department

Chouksey Engineering College, Bilaspur (India)

[email protected]

Abstract – In this paper, the design and implementation

of an AMBA based Memory controller is proposed.

The AMBA based Memory controller gives an ease of

integration for sub-frame extraction of various data

structures in SOC. AMBA based interaction deals with

role specific operation. It is majorly categorized in two

dedicated feature i.e. decision (AHB MASTER) and

response (AHB SLAVE). Moreover AHB master

enables transfer types i.e. burst mode and AHB

Master-to-AHB Slave supports incrementing and

wrapping addressing modes and completes data

transfer which the data width of read and write is

different by asymmetric asynchronous FIFO. A bridge

between AHB Master and AHB slave with application

of memory controller has been shown and there digital

efficiency in terms of area and speed is discussed.

Control structure is designed with finite state machine.

The IP of AHB Master and AHB Slave is implemented

and its interface with memory controller has been

designed and tested.

Keywords – AMBA, AHB MASTER, AHB SLAVE,

FIFO.

I. INTRODUCTION

As increasing numbers of companies adopting the

AMBA system, it has rapidly emerged as the de-

facto standard for SoC interconnection and IP

library development. AMBA enhances a reusable

design methodology by defining a common

backbone for SoC modules.

AHB is a new generation of AMBA bus which

is intended to address the requirements of high-

performance synthesizable designs. It is a high

performance system bus that supports multiple bus

masters and provides high bandwidth operation.

AMBA AHB implements the features required for

high performance, high clock frequency systems

including:

Burst transfers

Split transactions

Single-cycle bus master handover

Single-clock edge operation

Non-tristate implementation

Wider data bus configurations (64/128 bits)

Bridging between this higher level of bus and the

current ASB/APB can be done efficiently to ensure

that any existing designs can be easily integrated. An

AMBA AHB design may contain one or more bus

masters, typically a system would contain at least the

processor and test interface. However, it would also

be common for a Direct Memory Access (DMA) or

Digital Signal Processor (DSP) to be included as bus

masters. The external memory interface, APB

Bridge and any internal memory are the most

common AHB slaves. Any other peripheral in the

system could also be included as an AHB slave.

However, low-bandwidth peripherals typically

reside on APB.

Figure 1: AMBA AHB Block diagram

A typical AMBA AHB system design contains the

following components:

AHB Master

AHB Slave

AHB Arbiter

AHB Decoder

mailto:[email protected]

mailto:[email protected]

IJDACR

ISSN: 2319-4863



II. ARCHITECTURE OF AHB MEMORY

CONTROLLER

Figure 2 shows the top level implementation of AHB

compliant Memory controller. Data is initiated by

master and communicated through slave to memory

controller. Initially master generates the data and

control signals and further those controls cannot

directly communicate with any given generic

memory, hence data processed through slave .further

data passes through slave interface .we have used

FIFO for data and control buffering so that even

slave and memory are in different CLK then also our

communication is full proof. It reduces the

complexity. Further data is communicated through

ram or rom depends upon the read and write

communication.

Figure 2: Top architecture of AHB memory controller

AHB Bus Master

An AHB bus master has the most complex bus

interface in an AMBA system. Typically an AMBA

system designer would use predesigned bus masters

and therefore would not need to be concerned with

the detail of the bus master interface. Example bus

master the example bus master (EBM), e.g.

Master32 and e.g. master64, consists of:

An AHB-LITE core that generates a fixed set

of transfers in a continuous way

An AHB-LITE to AHB wrapper that enables

its connection to a standard AHB bus.

Figure 3: Top architecture of AHB master

AHB

Master

AHB

Slave

AHB

Slave

Interface

Data

ADD

Counter

Memory

Controller

Interface

RAM

ROM

FIFO

2:1

Mux

Address

Generator

2:1

Mux

Counter

Controller

Interface of various

control

Sel

Sel

CPU

add

Hsize

HTrans

HAdder

HAdder

Reg

IJDACR

ISSN: 2319-4863



Figure 3 shows the top structure of AHB master. It

contains mainly address generator and controller.

The address generator block is responsible for the

address generation according to the HBurst. Initially

the first address is given by CPU then it passes to

mux then depends on the selection it send sends it

data to address generation block ,the number of

address generated is govern by counter, counter

decides how much address is required depends upon

the HBURST. There is controller which is

implemented by Finite state machine.it take cares of

the entire operation of different blocks.

Figure 4: Address generator of master

WRAP4

LOGICAL

BLOCK

WRAP8

LOGICAL

BLOCK

WRAP16

LOGICAL

BLOCK

INCR,

INCR4

INCR8,

INCR16

LOGICAL

BLOCK

8:1 mux

BURST

&

OUTPUT

32 bit

Adder

2:1

Mu

x

Hsize

Mux

NON_SEQ HSIZE [2:0]

HBURST [2:0]

as_Haddr [31:0]

Sum

output

From

HADDR

[31:0]

SUM

IJDACR

ISSN: 2319-4863



The above figure 4 shows the structural

implementation of Address generator block. Which

is a combination of 2:1 multiplexer and 8:1

multiplexer. In this architecture the initial address is

given by CPU and further the next address is

generated by various block like INCR, WRAP

depends upon the HBURST. The adder block add

the CPU address or next generated address with

some constant value depends upon the hsizemux.

AHB Bus Slave

An AHB bus slave responds to transfers initiated by

bus masters within the system. The slave uses a

HSELx select signal from the decoder to determine

when it should respond to a bus transfer. All other

signals required for the transfer, such as the address

and control information, will be generated by the bus

master.

Figure 5: Slave Interface

The fig 5 shows the state diagram of slave interface.

It is a finite state machine implementation initial

condition is reset state which is an idle state when no

operation is there. When start signals arrived then

this FSM triggers, depends upon the hready and

hwrite signal it decides in which further state it has

to move. If hraedy is low then it will be start state

only, if hready is one then depends upon hwriteit

move to read or write state, if Hwrite is one then

state moves to write otherwise it moves to read state.

If hready will become low between these states then

it moves to wait state, and it will remains in these

sate until hready will become one .if any error occurs

which is indicated by Hresp then state moves to error

state.

Wait

Start

Wait

Read

HWrite

HReady

HRead

HReady

Start

Error

Reset

IJDACR

ISSN: 2319-4863



Figure 6: Memory controller

The fig 6 shows the state diagram of memory

controller. It is a finite state machine implementation

initial condition is reset state which is an idle state

when no operation is there. When start signals

arrived then this FSM triggers, depends upon the

instruction its operation is decided by CMD state.

According to instruction it moves to ram read, ram

write and rom read operation.

Memory Controller

The two main tasks for the core memory controller

are to handle all the timings between different

commands and to keep track of which rows that are

currently activated. The activation of rows are time

consuming and therefore the core memory controller

has a look ahead functionality where the arbitrator

can notify which command that is in turn to be

executed after the current one has finished. This

makes it possible to activate the row in advance if

the next command is not accessing the same bank or

chip as the current command.

FIFO

FIFO is a method of processing and retrieving data.

In a FIFO system, the first items entered are the first

ones to be removed. In other words, the items are

removed in the same order they are entered.

CMD

RESET

ROM

Read

RAM

Read

RAM

Write

IJDACR

ISSN: 2319-4863



Figure 7: FIFO

In Figure 7, two modules (called the source and the

sink) are connected to one another. When data is

being passed from module to module, the source is

the module that is outputting data. The sink is the

module that is receiving that data.

Figure 7 also shows three signals between the two:

Data, FIFO Full, and FIFO Empty. Data is the wire

that actually passes data from the source to the sink.

FIFO Full and FIFO Empty are known as

handshaking signals which allow the source and the

sink to communicate with regards to when it is time

to pass the data.

The FIFO Full signal indicates that the FIFO is full,

put valid data on the Data line. FIFO Full is what is

called a state signal: it is high only when data is

valid. If data is not valid on the Data line during a

particular cycle, Valid should be low during that

cycle.

The FIFO Empty signal indicates that the FIFO is

Empty to receive new data. FIFO Empty can be

asserted as soon as the sink is ready to receive new

data. Whenever the sink is not ready to receive new

data, Ready should be low.

The FIFO Interface handshake ensures that data

passes from the source to the sink only when the

source has valid data to pass and when the sink is

ready to receive that data. In other words, when

FIFO Full and FIFO Empty are both high, data on

Data will be latched into the sink on the next rising

edge.

RAM

Random-Access memory (RAM) is a form

of computer data storage. A random-access device

allows stored data to be accessed directly in any

random order. In contrast, other data storage media

such as hard disks, CDs, DVDs and magnetic tape,

as well as early primary memory types such as drum

memory, read and write data only in a predetermined

order, consecutively, because of mechanical design

limitations. Therefore the time to access a given data

location varies significantly depending on its

physical location. Today, random-access memory

takes the form of integrated circuits. Strictly

speaking, modern types of DRAM are not random

access, as data is read in bursts, although the

name DRAM / RAM has stuck. However, many

types of SRAM, ROM, OTP, and NOR flash are

still random access even in a strict sense. RAM is

normally associated with volatile types of memory

(such as DRAM memory modules), where its stored

information is lost if the power is removed.

ROM

Read only memory devices are a special case of

memory where, in normal system operation, the

memory is read but not changed. Read only

memories are non-volatile, that is, stored

information is retained when the power is removed.

As in computer terminology read means transferring

data instruction from an input source to the

computers main memory (or CPU) and write is

transferring data/instructions from computers main

memory to an output device. Therefore, Read only

means data/instruction can be retrieved from the

ROM Chip but cannot be modified.

The read only memory cell usually consists of a

single transistor. The threshold voltage of the

transistor determines whether it is a“1” or “0.”

During the read cycle, a voltage is placed on the gate

of the cell. Depending on the programmed threshold

voltage, the transistor will or will not drive a current.

The sense amplifier will transform this current, or

lack of current, into a “1”or “0.” Figure 9-1 shows

the basic principle of how a Read Only Memory

works.

Figure 8: Read only memory

Module

A

(Source)

Module B

(Sink)

FIFO Full

DATA

FIFO Empty

IJDACR

ISSN: 2319-4863



III. SIMULATIONS AND RESULTS

Simulation is carried out using Xilinx13.1 ISE.

Figure 9: RTL view of memory controller

Figure 10: Simulation result of FIFO

Figure 5.11: Simulation result of AHB Master

Figure 5.12: Simulation result of memory controller

Figure 5.13: Simulation result of ROM

Figure 5.14: Simulation result of Slave and slave interface

IV. CONCLUSION

AHB based Memory Controller is designed in this

paper. The design has been implemented using

Verilog HDL for SOC solution. The design has

taken care of balance between area and speed.

Master IP has been implanted and its address

IJDACR

ISSN: 2319-4863



generator block is implemented with Single adder

instead of 64 typical adder hence we have manage to

reduce the area with help of proper design. Every

implementation is in structural approach hence it

becomes a well-documented frame. There is

separate implementation of slave and slave interface

with inter faces the memory controller further. To

avoid the handshaking complexity, we have used

FIFO for memory controller interface and slave

interface. Even it increases the latency but at the

same time it makes design simple and bottleneck

problem free. The design has been synthesized on

XILINX 13.1 Spartan 3, and simulated in

MODELSIM.

REFERENCE [1] Shilpa Rao and Arati S. Phadke, “Implementation of

AMBA compliant Memory Controller on a FPGA”,

IJETEE, 2013.

[2] Archana C. Sharma1, Prof.Zoonubiya Ali, “Construct High-Speed SDRAM Memory Controller Using

Multiple FIFO's for AHB Memory Slave Interface”, IJETAE, 2013.

[3] S. Lakshma Reddy, A .Krishna Kumari, “Architecture

of An AHB Compliant SDRAM Memory Controller”, International Journal of Innovations in Engineering

and Technology, 2013.

[4] Arun G, Vijaykumar T, “Improving Memory Access time by Building an AMBA AHB compliant Memory

Controller”, IJARCET, 2012.

[5] S.Ramakrishna, K.Venugopal, B.VijayBhasker, R.Surya Prakash Rao, “Hdl Implementation of Amba-

Ahb Compatible Memory Controller”, IJCER, 2012.

[6] Jayapraveen.DandT.GeethaPriya, “Design of memory controller based on AMBA AHB protocol”, Elixir

International Journal, 2012.

[7] Ch.Vijayalakshmi, Mr B.Raghavaiah, “Implementation of AMBA AHB Compliant Memory

Controller with Peripherals”, ICITEC, 2012.

[8] KareemullahShaik, Mohammad Mohiddin, Md. Zabirullah, “A Reduced Latency Architecture for

Obtaining High System Performance”, IJRTE, 2012.

[9] Hu Yueli; Yang Ben, “Building an AMBA AHB Compliant Memory Controller”, IEEE, 2011.

[10] Varshavishwarkama, Abhishekchoubey, ArvindSahu,

“Implementation of AMBA AHB protocol for high capacity memory management using VHDL”, IJCSE,

2011.

[11] Zhao, B., “High speed DDR memory interface design”, IEEE, 2009.

[12] McGee, S.W.; Klenke, R.H.; Aylor, J.H.; Schwab,

A.J., “Design of a processor bus interface ASIC for

the stream memory controller”, IEEE, 1994.

[13] Arm amba 2 speci_cation. [Online]. Available:

[14] http://www.arm.com/products/solutions/AMBA Spec.html

[15] Datta and V. Singhal, \Formal veri_cation of a public-

domain ddr2 controller de-sign," VLSI Design, 2008. VLSID 2008. 21st International Conference on, pp.

475{480,Jan. 2008.

[16] KeesGoossens, Om Prakash Gangwal, Jens R¨over, and A. P. Niranjan. Interconnectand Memory

Organization in SOCs for advanced Set-Top

Boxesand TV-Evolution, Analysis, and Trends. In

JariNurmi, HannuTenhunen,JouniIsoaho, and Axel

Jantsch, editors, Interconnect-Centric Designfor

Advanced SoC and NoC, chapter 15, pages 399–423. Kluwer, April 2004.

[17] Shashisekhar Ramagundam, Sunil R. Das, Scott

Morton, Satyendra N. Biswas, Voicu Groza, Mansour H. Assaf, and Emil M. Petriu, “Design and

Implementation of High-Performance Master/Slave

Memory Controller with Microcontroller Bus Architecture”, IEEE International Conference on

Instrumentation and Measurement Technology

(I2MTC) Proceedings, pp. 10 – 15, May 2014.

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