International Symposium on Low Power Electronics and Design A Hybrid Display Frame Buffer Architecture for Energy-Efficient Display Subsystem Kyungtae Han, Alexander Min, Nithyananda Jeganathan, and Paul Diefenbaugh Intel DRAM-Based display subsystem DRAM is used as a display frame buffer to transport display contents to display panel. Power consumption of DRAM frame buffering is significant as the resolution of screen is growing (4K, 8K display). 2 Status Quo Lots of static area in typical display contents 3 Insights *fps: Frame per Second (max: 60), SL: Scan-line, MB: Macro-block, P: Pixel in changed frame # of Read >> # of Write Read Dominance (Intensive) - Data reading from the display frame is much more frequent than the writing of new data onto the frame buffer Energy efficient memory for data read Phase Change Memory (PCM) Asymmetric power consumption in PCM High power required for changing its structure for write 4 Insights - II PCM consumes less energy for data read than data write (E read