Upload File

introduction

50
Introduction Introduction 29/8 - 2008 INF5062: Programming asymmetric multi-core processors

Upload: dinah

Post on 05-Jan-2016

33 views

Category:

Documents


2 download

Report

DESCRIPTION

INF5062: Programming asymmetric multi-core processors. Introduction. 29/8 - 2008. Disclaimer. Asymmetric and heterogeneous multi-core processors This is a developing terminology Asymmetric Multi-core chips Entirely identical instruction set - PowerPoint PPT Presentation

TRANSCRIPT

Page 1: Introduction

Introduction Introduction

29/8 - 2008

INF5062:Programming asymmetric multi-core processors

Page 2: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Disclaimer

Asymmetric and heterogeneous multi-core processors−This is a developing terminology−Asymmetric

• Multi-core chips• Entirely identical instruction set• Asymmetry in speeds, frequencies, power consumption, etc.

−Heterogenous• Multi-core chips• Heterogeneous instruction sets

“Heterogeneous” is nowadays better;the course name will change next year

Page 3: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Overview

Course topic and scope

Background for the use and parallel processing using heterogeneous multi-core processors

Examples of heterogeneous architectures

Page 4: Introduction

INF5062:The Course

Page 5: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

People

Håvard Espeland (TA)email: haavares @ ifi

Pål Halvorsenemail: paalh @ ifi

Carsten Griwodzemail: griff @ ifi

Page 6: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

About INF5062: Topic & Scope

Content: The course gives …

− … an overview of heterogeneous multi-core processors in general and three variants in particular (architectures and use)

− … an introduction to working with heterogenous multi-core processors

• Intel IXP 2400 network processor card

• nVIDIA’s G80 family of GPUs and the CUDA programming framework

• The Cell Broadband Engine Architecture

− … some ideas of how to use/program heterogeneous multi-core processors(regular and guest lectures)

Page 7: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

About INF5062: Topic & Scope Tasks:

An important part of the course are lab-assignments where the students program each of the three examples of heterogeneous multi-core processors

1. On the Intel IXP

• Protocol statistics – download and run wwpingbump and then extend it to give processor, interface and protocol statistics

2. On the Cell processor

• Video encoding – download Motion JPEG compression software and improve its performance by using the Cell processor’s SBEs

3. On the nVIDIA graphics cards

• Video encoding – the same goal as above, but exploit the parallelity of the G80 architecture

Page 8: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

About INF5062: Exam Prerequisite – mandatory assignments:

− Lab assignment 2: solve task 2 or 3− Present it to the class

2 graded assignments (counting 33% each):− Lab assignment 1: solve task 1

• Deliver code• Make a demonstration to the class• Explain your design and code

− Lab assignments 3: solve task 2 and 3• Deliver code• Demonstrate that lab assignment to the class that was not shown in the

mandatory assignment• Explain your design and code

Final oral exam (counting 33%): early December 2008− Content of the lectures− Content of lab assignments− The experimental platforms used− The own code

Page 9: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Available Resources

Resources will be placed at

−http://www.ifi.uio.no/~griff/INF5062−Login: inf5062−Password: ixp

−Manuals, papers, code example, …

Page 10: Introduction

Background and Motivation:

Moore’s Law

Page 11: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Motivation: Intel View

Soon >billion transistors integrated

Page 12: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Motivation: Intel View

Soon >billion transistors integrated Clock frequency can still increase

Page 13: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Motivation: Intel View

Soon >billion transistors integrated Clock frequency can still increase Future applications will demand TIPS

Page 14: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Motivation: Intel View

Soon >billion transistors integrated Clock frequency can still increase Future applications will demand TIPS Power? Heat?

Page 15: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Motivation: Intel View

Soon >billion transistors integrated Clock frequency can still increase Future applications will demand TIPS Power? Heat?

Page 16: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Motivation“Future applications will demand TIPS”

“Think platform beyond a single processor”

“Exploit concurrency at multiple levels”

“Power will be the limiter due to complexity and leakage”

Distribute workload on multiple cores

Page 17: Introduction

Background and Motivation:

Symmetric multi-processing

Page 18: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

QuickTime™ and a decompressor

are needed to see this picture.

Symmetric Multi-Core Processors

Intel Dual-Core Xeon

Page 19: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

QuickTime™ and a decompressor

are needed to see this picture.

Symmetric Multi-Core Processors

Phenom X4

Page 20: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

QuickTime™ and a decompressor

are needed to see this picture.

Symmetric Multi-Core Processors

UltraSparc

Page 21: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Intel Multi-Core Processors

Symmetric multi-processors allow multi-threaded applications to achieve higher performance at less die area and power consumption than single-core processors

Page 22: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Symmetric Multi-Core Processors Good

− Growing computational power

Problematic− Growing die sizes− Some cores used much more than others− Individual cores frequently unused− Many core parts frequently unused

Why not spread the load better?− Functions exist only once per core− Parallel programming is hard

Asymmetric multi-core processors

Page 23: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Asymmetric Multi-Core Processors

Asymmetric multi-processors consume power and provide increased computational power only on demand

Highly parallel Moderately parallelSequential

Page 24: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Honogeneous Multi-Core Processors

Operating systems scale only to a limited number of threads

Where does the increase in core numbers stop? How many applications need more than 64 threads? Performance? software limits are the issue

Application-specific engines? Intel Academic Forum 2006: YES But: Programming model?????

Page 25: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Motivation“Future applications will demand TIPS”

“Think platform beyond a single processor”

“Exploit concurrency at multiple levels”

“Power will be the limiter due to complexity and leakage”

Distributed workload on multiple cores + simple processors are easier to program

+consume less energy

heterogeneous multi-core processors

Page 26: Introduction

Background and Motivation:

History of heterogeneous multi-

processing

Page 27: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Co-Processors

The original IBM PC included a socket for an Intel 8087 floating point co-processor (FPU)− 50-fold speed up of floating point operations

Intel kept the co-processor up to i486− 486DX contained an optimized i487 block− Still separate pipeline (pipeline flush when starting and ending use)− Communication over an internal bus

Commodore Amiga was one of the earlier machines that used multiple processors− Motorola 680x0 main processor− Blitter (block image transferrer - moving data, fill operations, line

drawing, performing boolean operations)− Copper (Co-Processor - change address for video RAM on the fly)− And finally: IBM PowerPC - relegate the 680x0 to a co-processor job

Page 28: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Graphics Processing Units (GPUs)

bussconnect

or & memory

hub

GPU:a dedicated graphics rendering device

2D3D

First GPUs,

80s: for early 2D operations Amiga and Atari used a blitter, Amiga had also the copper

90s: 3D hardware for game consoles like PS and N64 3dfx Voodoos 3D add-on card for PCs

Page 29: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Graphics Processing Units (GPUs)

bussconnect

or & memory

hubNew powerful GPUs, e.g.,:

Nvidia GeForce GX280 30 400 MHz core 1 GB memory memory BW: 141+ GBps 1.296 GHz

similar to other manufacturers …

Page 30: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

General Purpose Computing on GPU The

− high arithmetic precision − extreme parallel nature− optimized, special-purpose instructions− available resources− …

… of the GPU allows for general, non-graphics related operations to be performed on the GPU

Generic computing workload is off-loadedfrom CPU and to GPU

More generically: Heterogeneous multi-core processing

Page 31: Introduction

Background and Motivation:

Heterogeneousmulti-processing

nVIDIA GPUs

Page 32: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

nVIDIA G92 nVIDIA GT280 (latest

and greatest)

− 1.4 billion transistors− 240 shaders

− 512 bit memory bus (GDDR3)

− 141,7 GB/s memory bandwidth

− 933 Gflops

− PCI Express 2.0

Page 33: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

nVIDIA G92

Streaming Multiprocessor (SM)

Store to

SP0 RF0

SP1 RF1

SP2 RF2

SP3 RF3

SP4RF4

SP5RF5

SP6RF6

SP7RF7

Constant L1 Cache

L1 Fill

Load from Memory

Load Texture

SFU

SFU

Instruction Fetch

Instruction L 1 Cache

Thread / Instruction Dispatch

L1 Fill

Work

Control

Results

Shared Memory

Store to Memory

Stream Multiprocessor− Per TPC (3 clusters)

• 16bK cache (in TEX)

− Per SM• 16 kB level 1 cache• 64 kB shared memory

− Global• 256 kB level 2 cache

Number of stream multiprocessors− 1 - Quadro NVS 130M− 16 - GeForce 8800 Ultra / GTX− 30 - GeForce GTX 280− 4x30 - Tesla S1070

Page 34: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Memory Bandwidth for CPU and GPU

Marketed as GPGPUs

Page 35: Introduction

Background and Motivation:

Heterogeneousmulti-processing

The Cell Broadband Engine

Page 36: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

STI (Sony, Toshiba, IBM) Cell Motivation for the Cell

− Cheap processor− Energy efficient− For games and media processing− Short time-to-market

Conclusion− Use a multi-core chip− Design around an existing, power-

efficient design− Add simple cores specific for game

and media processing requirements

Page 37: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

STI (Sony, Toshiba, IBM) Cell Cell is a 9-core processor

− combining a light-weight general-purpose processor with multiple co-processors into a coordinated whole

− Power Processing Element (PPE) • conventional Power processor• not supposed to perform all

operations itself, acting like a controller

• running conventional OSes• 16 KB instruction/data level 1

cache• 512 KB level 2 cache

Page 38: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

STI (Sony, Toshiba, IBM) Cell

− Synergistic Processing Elements (SPE)

• specialized co-processors for specific types of code, i.e., very high performance vector processors

• local stores• can do general purpose

operations• the PPE can start, stop, interrupt

and schedule processes running on an SPE

− Element Interconnect Bus (EIB)• internal communication bus • connects on-chip system

elements: PPE & SPEs the memory controller (MIC) two off-chip I/O interfaces

• 25.6 GBps each way

Page 39: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

STI (Sony, Toshiba, IBM) Cell−memory controller

• Rambus XDRAM interface to Rambus XDR memory

• dual channels at 12.8 GBps 25.6 GBps

−I/O controller• Rambus FlexIO interface

which can be clocked independently

• dual configurable channels

• maximum ~ 76.8 GBps

Page 40: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

STI (Sony, Toshiba, IBM) Cell

− Cell has in essence traded running everything at moderate speed for the ability to run certain types of code at high speed

−used for example in• Sony PlayStation 3:

3.2 GHz clock 7 SPEs for general operations 1 SPE for security for the OS

• Toshiba home cinema: decoding of 48 HDTV MPEG streams

dozens of thumbnail videos simultaneously on screen

• IBM blade centers: 3.2 GHz clock Linux ≥ 2.6.11

Page 41: Introduction

Background and Motivation:

Heterogeneousmulti-processing

IXP Network Processor

Page 42: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

Review of General Data Path on Conventional Computer Hardware Architectures

communicationsystem

application

user space

kernel space

sending:

communicationsystem

application

receiving:

communicationsystem

application

forwarding:

transport (TCP/UDP)

network(IP)

link

Chec

ksum

min

g

Copy

ing

Frag

men

tatio

nIn

terr

upts

Page 43: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

IXA: Internet Exchange Architecture

IXA−a broad term to describe the Intel network

architecture−HW & SW, control- & data plane

IXP: Internet Exchange Processor−processor that implements IXA

−IXP1200 is the first IXP chip (4 versions)

−IXP2xxx has now replaced the first version

Page 44: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

IXA: Internet Exchange Architecture IXP1200 basic features

− 1 embedded 232 MHz StrongARM− 6 packet 232 MHz µengines− onboard memory − 4 x 100 Mbps Ethernet ports− multiple, independent busses− low-speed serial interface− interfaces for external memory

and I/O busses− …

Page 45: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

IXA: Internet Exchange Architecture IXP2400 basic features

− 1 embedded 600 MHz XScale− 8 packet 600 MHz µengines− onboard memory − 3 x 1 Gbps Ethernet ports− multiple, independent busses− low-speed serial interface− interfaces for external memory

and I/O busses− …

Page 46: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

IXP1200 Architecture

RISC processor:- StrongARM running Linux- control, higher layer protocols and exceptions- 232 MHz

Microengines:- low-level devices with limited set of instructions- transfers between memory devices - packet processing- 232 MHz

Access units:- coordinate access to external units

Scratchpad:- on-chip memory- used for IPC and synchronization

Page 47: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

IXP1200 IXP2400

SRAM

FLASH

MEMORYMAPPED

I/O

DRAM

SRAMaccess

SDRAMaccess

SCRATCHmemory

PCIaccess

IXaccess

EmbeddedRISK CPU

(StrongARM)

PCI bus

IX bus

DRAM bus

SRAM bus

microengine 2

microengine 1

microengine 5

microengine 4

microengine 3

microengine 6

multipleindependent

internalbuses

IXP1200

Page 48: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

IXP2400

IXP2400 Architecture

microengine 8

SRAM

coprocessor

FLASH

DRAM

SRAMaccess

SDRAMaccess

SCRATCHmemory

PCIaccess

MSFaccess

EmbeddedRISK CPU(XScale)

PCI bus

receive bus

DRAM bus

SRAM bus

microengine 2

microengine 1

microengine 5

microengine 4

microengine 3

multipleindependent

internalbusesslowport

access

…

transmit bus

RISC processor:- StrongArm XScale- 233 MHz 600 MHz

Microengines- 6 8- 233 MHz 600 MHz

Media Switch Fabric- forms fast path for transfers- interconnect for several IXP2xxx

Receive/transmit buses- shared bus separate busses

Slowport- shared inteface to external units- used for FlashRom during bootstrap

Coprocessors- hash unit- 4 timers- general purpose I/O pins- external JTAG connections (in-circuit tests)- several bulk cyphers (IXP2850 only)- checksum (IXP2850 only)- …

Page 49: Introduction

Background and Motivation:

Heterogeneousmulti-processing

Summary

Page 50: Introduction

INF5062, Pål Halvorsen and Carsten GriwodzUniversity of Oslo

The End: Summary

Heterogeneous multi-core processors are alreadyeverywhere

Challenge: programming−Need to know the capabilities of the system−Different abilities in different cores−Memory bandwidth−Memory sharing efficiency−Need new methods to program the different

components

Next time: how to start programming the Intel IXP


Introducción / Introduction / Introduction

introduzione | introduction | einleitung | introduction · introduzione | introduction | einleitung | introduction | introducción | введе́ние | wstęp en Description Operation

Introduction Section I: Introduction

 · Contents INTRODUCTION Introduction

Introduction and Thesis Introduction - …...1 Introduction and Thesis Introduction: The introduction relates the topic to the main point of the essay. The introduction is composed

Introduction to Transducers, Introduction to Transducers ...engtech.weebly.com/.../more_on_transducers_sensors_actuators.pdf · Introduction to Transducers, Introduction to Transducers,

Systems Analysis I introduction I introduction. 2Systems Analysis - Introduction Contents Introduction Introduction 3 classic phases 3 classic phases

Introduction and Welcome€¦ · Introduction and Welcome Introduction 4

INTRODUCTION SPECIFICATIONS INTRODUCTION

Introduction to Logic Introduction

VisionaryScancombinesarichsetofqualitycontrolandproductivi ... · Introduction Introduction VisionaryScancombinesarichsetofqualitycontrolandproductivityfeatureswithasimpleinterfacedesignedspecificallyforscanningandcodingdepositionexhib-

ection Introduction A Introduction

R as a Web Service Introduction Introduction Introduction

Introduction€¦ · Introduction ThisdocumentprovidesinformationabouttheIOSXEsoftwarereleasefortheCiscoNCS4201andCisco …

INTRODUCTIONS (LEADS) Academic introduction Creative introduction Action introduction Dialogue introduction Overarching societal statements Personal introduction

1 Introduction INTRODUCTION - MICROCSB

1. INTRODUCTION • INTRODUCTION • EINFÜHRUNG • INLEIDING • INTRODUCCIÓN … · 2016-12-16 · 1. INTRODUCTION • INTRODUCTION • EINFÜHRUNG • INLEIDING • INTRODUCCIÓN

Introduction Introduction to Brittle Deformation

INTRODUCTIONS (LEADS) Creative introduction Action introduction Dialogue introduction Personal introduction Question introduction Quotation introduction

Introduction - University of Cambridge · Introduction. Introduction

1. Introduction 1. Introduction 1. Introduction 1 ... · Introduction 1. Introduction 1. Introduction 1. Introduction 6061B0242401. The Phone Screen From the Phone screen, you can

Introduction to Transducers, Introduction to Transducers ... on... · Introduction to Transducers, Introduction to Transducers, Sensors and ActuatorsSensors and Actuators Introduction

1. INTRODUCTION 1.1 Introduction

 · Introduction . 6 . Contents . Introduction

Introduction: Definition Introduction: Philosophy

1 Introduction t 1. Introduction to Nanotechnology - UFAMhome.ufam.edu.br/berti/nanomateriais/Introduction to Nanotechnology... · Introduction t 1. Introduction to Nanotechnology

An Introduction to NSAn Introduction to NS2An Introduction ...teerawat/publications/NS2/02-NS2.pdf · An Introduction to NSAn Introduction to NS2An Introduction to NS2 Textbook: T

1. Introduction 10 - therackonline.com€¦ · 1. Introduction 10 - therackonline.com ... Introduction)

An Introduction for An Introduction for Introduction for ......An Introduction for An Introduction for Introduction for TeachersTeachersTeachers . exChange, Blackburn Cathedral’s

Industry introduction Industry introduction Company introduction Company introduction Production introduction Display time time content

CrowPiwithMineCraftPiEdition · 2 CrowPiwithMineCraftPiEdition-Introduction-MinecraftPiEdition-Introduction-Whatyouwillneed-Introduction-RunningMinecraft-Introduction

Introduction to Elasticsearch and Logstash. - KIT · PDF fileOutline 1 Introduction 2 Logstash Introduction 3 Elasticsearch Introduction 4 Conclusions Introduction Logstash ElasticsearchConclusions

Optimisation des Requêtes. Introduction Introduction

General introduction 1.1 Introduction

Introduction Chapitre 1 · Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .