BASIS OF CPU DESIGN

BASIS OF CPU DESIGNStructured LSI Design with SFL in SN/X CPU

(Applicable to training course)Translated from sfltext book of Shimizu Takahiko Author

Web: http*//www.ip-arch.jp

Email: nshimizu@ip-arch.jp

CHAPTER I LSI DESIGN OVERVIEWLSI 70 LSI 80 LSI CAD90 (RTL)RTL

The integration of LSI has improved along with the refinement of IT processing technology every year. In the 70's, the designer described the layout directly in LSI design. In the 80's, place and route LSI CAD program can be used practically. And designs were done at gate level these days. From the 90s, the logical synthesis was used and the design in register transfer level (RTL) language became the main stream. However, it is assumed that the design in RTL was quite difficult and they started to look for a new design paradigm in recent years. In fact, the highly abstract design hierarchy is always necessary in large-scale development, but there is a limit in cognitive ability of human being. Thats the reason why the change in these design paradigms is an inevitable consequence in order to work on this complexity.

NTTPARTHENON sfl2vlSFLSFLVerilog VerilogPARTHENON LSILSI

Compared to RTL language which has been using worldwide, SFL (Structured Functional description Language) which has been developed by NTT from the 80s is quite abstracted. Though, it is fairly competitive as a description language that is appropriate for large-scale development. However, the unique processing system, PARTHENON of NTT was suspended of sales, and the use of this system inside Japan has been limited to education in university despite it was a description language with an excellent domestic production. A new SFL processing system called sfl2vl can be used in a wide scope. Besides, it can convert what has been designed by SFL language into Verilog and enable logical synthesis and logical simulation by Verilog. It is expected to solve the problem of PARTHENON, which are the lack of library and user interface of logical simulation. This tutorial aims to guide how to use LSI development technique which is appropriate for large-scale LSI development with free tools.

1.1 LSI design flow

LSILSI[2]

For the developers other than LSI professional vender, LSI design is a high cost project.

Maybe a lot of people doubt that: Is it really necessary to develop? However, as a survey by Japan System House Association, half of the embedded system development needs hardware development. An appropriate hardware development can make the development of the entire system easy. It can also become the main factor of the product competitiveness compared to easily copied software.

FPGA

Besides, the integration and speed of FPGA has been improving. The cheap hardware development in mask manufacturing of which reading time is unnecessary is practicable.

1.1LSISFL

Figure 1.1 shows the flow of LSI design. SFL has a capability to describe a wide range from architecture design to verification design. The language is assumed to be good at specializing logical description.

SFL SFL PARTHENONsecondssfl2vl Verilog

Creating specification for verification is the designers work, but it takes a lot of effort to prepare test environment called test script for logical verification. As a feasible hardware description language which can implement parallel description, SFL can also be used to describe test script. It is necessary to make the test script further in order to verify the module of SFL in actual verification work. In PARTHENON, test script is the input data of logical simulator which is called seconds with an original script system.

In sfl2vl, Verilog language is also used for the test script.

1.1.1. Conceptual design

LSI

1.

2.

3.

The first step of LSI design is conceptual designs which focus on grasp all functions and block division.

In this phase, we will discuss on the floor plan and estimate briefly the delay time from the route length of the outline and the number of gates of .

I have made the following documents as deliverables of the conceptual design.

1. Block chart

2. Timing chart

3. Interface specifications

If the development size is small, you can write these documents in hand-writing, but it is quite difficult to cross-check a hand-written document. So the form of document that can be read by a computer is always expected. Moreover, in order to avoid the disagreement between specifications and implemented function, you are expected to implement the function exactly as described in the specifications if possible.

The block chart and the timing chart are chiefly used for the outline design of the function.

The interface specifications are the specifications that become footholds after the detail design, so it is necessary to design carefully. It is also necessary to define not only the signal name but also use methods and timing in the interface specification, and specify data which accompanies the name of each signal of the input, the output, and the control, the width in bits, and the control for minimum information.

SFL declare 1.4 Sample circuit declare

Sample circuit8In1OutTrig In declare

SFL instrin instr_arg

Declare sentence, one syntaxes of SFL, is a part of interface specifications, and can define interface between modules. Let's see the example of the declare sentence which defines the interface of Sample circuit module in Figure 1.4.

In Sample circuit, there is In in eight bits as an input signal, and Out in one bit as an output signal. Besides, there is Trig as a control input terminal to start the circuit. When the control input is started, it can transfer argument value to input signal In.

The declare sentence only defines the interface specification, so may be the implementing at the design initial stage is unclear.

As shown in figure, the detail description method in SFL can specify instr_arg argument in control terminal instrin of the module.

1.1.2. Hierarchical design

SFLdeclare 1.5SFL any

:

The complexity of design can be greatly eased by hierarchically using two or more modules. Top module is designed to divide design into parts, and call out sub modules. Unlike software, when a lot of sub modules are used, separate hardware is generated respectively.

If the module is declared by the declare sentence in SFL, behavioral description which use that module to be a submodule can be used. Figure 1.5 is a part of the hierarchically design SFL description. any is a syntax which executes the condition

Condition: execute statements

When condition of two or more condition executable statements as above is evaluated at the same time, the condition executes all true executable statements in parallel.

init, setup 0x00, curval cirTrig Out Value

Trig Out

Depend on condition init and setup, different arguments 0x00 and curve are given; control terminal Trig of the submodule of module instance name cir is started, and module output signal Out is taken into internal signal Value.

At this time, please remember that it is unnecessary for top module to know information inside the submodule. A top module only has to know that if control terminal Trig is started, the result will be out.

Using this special feature, you can design from top module top down after divide modules hierarchically according to the block chart. If sub modules are not gathered, it is quite inconvenient for logical synthesis and the verification. However, the entire design can be advanced by describing the alternative module of the sub modules by the procedure-oriented language or so on.

1.1.3. Detail design

LSI

In detail design, you will create test specification to test the logical circuit and the logical circuit which actually operates as LSI. Various circuits like the internal control circuit and the circuit which the state changes are implemented inside modules

1.1.4. Logical verification

Like a program, description mistakes and design error might occur in logical circuit. So a small size logical verification is necessary in each detail designed module before the whole is integrated and operated.

When the verification of an individual module is implemented, the system verification which connects the entire circuit is needed, too. In system verification, verification together with common software and long-time simulation is requested,

1.2. Outline of hardware description language SFL

SFL SFL

I would like to explain the outline of the language specification of SFL. Please refer to "SFL language specification" of the Parthenon society issue about details of the language specification.

1.2.1. Features of SFL

SFLRTL RTL

SFL belongs to the language of the register transfer level RTL, but it has some different features from other RTL languages and the circuit diagrams

Control terminal

RTLSFL(instrin instrself ) instruct

In the circuit chart and other RTL languages, it is not shown out whether the signal is used as a control or data. However, in SFL, control signal and general data signal are clearly separated.

The control signal is input from control terminal. The response when the control terminal is started is described in the instruct sentence

SFLinstr_arg

When the control signal is activated, it might result in the transmission of the data of the controlled object. In SFL, argument can be set in control terminal in order to activate control signals with data transfer. Arguments are provided by the instr_arg sentence.

Stage and tasks

SFL(generate, delay)

The control of control terminals is only an action of a single clock cycle. On the other hand, stage is the SFL mechanism which deal with sequence control though more than one the clock. As long as the stage is not started, it is stopped. Theres no action can be done in stopped stage. If you want to start the stage directions, you have to issue (generate, delay) command. If the start instruction is made, stage will be start on the rise of the next clock.

SFL

When the stage is started as there are a control system and a data system in the signal line, the signal of the control system and the data system is separately defined. In SFL, the task is used as the sequence system control signal. The task becomes an effective signal only when you start the stage which shows what should be implemented.

(reg, reg_wr, reg_ws)

You can defined arguments of data system which associated with the task together with control terminals. In order to start the task at the leading to the next clock, unlike the data of control terminals, you can use memory unit which is called register (reg, reg_wr, reg_ws) to hand over data.

1.7SFL

RTL

1.8 SFL

State machine is one of the order controls. If you take the value of a present state variable as a state, you can do actions step by step according to the state transition by describing operation that should be executed in each state. You can also use state machine when operate the same circuit while switching states over multiple clocks.

Figure 1.7 shows the example of the state transition described in SFL.

On the other hand, in general, the control signal is transferred accompanied to data in the pipeline. In gate level and other RTL languages, there are no distinctions between the control signal and data, thats why the control signal will be transmitted to the pipeline latch with data

Figure 1.8 shows the example of the task description in SFL.

Distributed selector

SFL

In SFL, the setting of the value to the terminal doesn't show the connection but means transfer. If the transfer doesnt collide at the same time, you can describe the transfer to the same terminal in different locations in the same module. When a logical synthesis is actually done, different transfer is converted into distributed selector circuit, and the transfer condition will be the selection condition of the selector.

Single-phase Edge trigger model

SFL ()

SFL LSI CAD

In SFL, the logical circuit uses the single phase edge trigger model (cycle based model) which is synchronized with the unspecified master clock. All signals start at the leading edge of the clock. State variation of the order element such as setting value to the register and memory, start and state changing of stages will occur at the leading edge of the next clock. This model is sometimes considered to be a weak point of SFL. However, in the present, it is unnecessary to use the time difference between phases of multiphase clock in the high-level design of a large-scale logical circuit. LSI CAD might be able to fine adjust the combination circuit to improve the pipeline performance, so it is thought that cycle based design is suitable for the design using a logic synthesis tool

1.3. Conclusion

SFL LSI

I have explained the flow of LSI design by SFL. As you increase the scale of development, the problem is not how to create but what to create. Hence, a high-quality language by which the designer thought is united is necessary. So please try to understand hardware description language and improve your design skill.

Chapter II SFL Language Tutorial 1

1. Simulation Environment

In this tutorials, we use following environment (EDA Linux LiveCD). The entry language is SFL and we convet the source code to Verilog. Then with provided Verilog simulation script, we will compile into execution script of Icarus Verilog. The execution script generates text output and optionaly Value Change Dump file (VCD file) for wave form viewer GTKwave.

In EDA Linux LiveCD, we have a directory (KISO1) that holds the tutorial examples with Makefile and execution scripts. We can execute the simulation with:

#. /exe {-wave} file

-wave is an optional parameter and file is a filename without extension.

2. Basic structure of SFL

SFL describes the logic circuit as set of modules. The structure of a module is shown as following. Each definitions and/or descriptions can be eliminate but the order of the definitions should not be altered.

module module_name {

io_facility_defenitions

control_terminal_argument_definitions

core_behavior

control_behavior

stage_beharvior

}Input and output of modules use external terminals:

DirectionTerminal definition commandDescription

InputinputData input terminal

OutputoutputDta output terminal

Bi-directionalbidirectData bi-directional terminal

InputinstrinControl input terminal

OutputinstroutControl output terminal

SFL has following facilities:

Facility definitionDescription

instrselfControl internal terminal

selInternal data terminal

regRegister without reset

reg_wsRegister with power on set

reg_wrRegister with power on reset

memmemory

submodule_nameSubmodule instance definition

SFL has following behavioral definitions:

OperationDescription

Unit operationTransfer a value to terminal, write to register, write to memory, state transition, activate control terminal, generate/transfer/terminate a job

parParallel activation of unit oprations.

altConditional activation of unit operations with priority.

anyConditional activation of unit operations without priority. (All of the matched operation will be activated in parallel)

ifConditional activation of a unit operation.

SFL operators:

OperatorDescriptionOperatorDescription

^Nagate|OR

Bit extraction@EXOR

Bits extraction&AND

/|Bitwise OR||Bit concatination

/&Bitwise AND+Add

/@Bitwise EXOR==Equal

n#Sign extention

SFL provide bit operators and you can make bit twisting logic as Example-2.2.1.

Example-2.2.1 Bit extraction and concatination.

module testbitop {

input a, b;

output f;

f = a || (a&b_:63_4 _+% %__!__. 3_4 ___ ___ 0>_:6 ___ _2+_ _,_ %__!__. _2+_ _,_ %__!__. _2+_ Making the cell base after using Alliance base on SFLVH7 and open source EDA tool is described on this exercise. Sfl2vh changes the description of SFL and out put it to the form of sfl2vh. Alliance converts the VHDL RTL description into the net list of the structural description form. Alliance is composed the description of connection cells that output of the VHDL RTL structure description form is described by circuit for the cell base design, and is a basic block of the circuit. The minimum unit that the system designer handles becomes a logical cell in a standard cell and the gate array, and the circuit shown by the net list is converted into the silicon layout with a tool of the arrangement wiring.

___ #' #' ___ #' _+% It is different in each kind of the cell designer can use and manufacturing trader LSI foundry. Moreover, because characteristic (Power consumption, circuit construction and delay time) of the cell is naturally different, it is necessary to treat sets of cells that match it to manufacturing in the logical synthesis. The file that defines the structure and the basic characteristic etc. of the cell that can use it is called a cell library. Construction design rule of LSI design rule is a big influence in the design of the cells. Then, the cell library in each process that not only the difference by the foundry but also each foundry offers. A huge man-hour is necessary to prepare the cell library of each foundry, and business EDA vender has corresponded.

_+__3_4_+%___ _+%A____3_4 _A__#0.7"0'

0.7"0 VDEC 5 has loaned business EDA to the science purpose free of charge in Japan, but when it sees worldwide is made for trial purposes for the education, business EDA use is difficult, and best problem is attempt to maintain the system design rule. It is scalable CMOS rule of MOSIS that centers on the United States, and for one thing, the design rule that two or more venders can use has been opened to the public. The user can make the library that doesn't depend on the vender by designing an original cell library according to CMOS.

%__!__. %__!__. #0@_!;' %__!__. _ ____.7"0 ___

34Alliance used by this manuscript has taken a unique technique to the design rule and the cell library. The primitive cell is script library called SXLIB in Alliance, and it is designed with only virtual arrangement information. It is possible to matching virtual cell library to a lot of design rules to by describing the design rule file. The design rule file prepared in Alliance standard is a library for CMOS that is a virtual six aluminum layer 10 micrometer process of a virtual foundry.

Figure 4.1: LSI Design follow with Alliance and sfl2vh.

Layout of EDA tool is described as the following:

Sfl2vh : convert SFL source file into VHDL behaviour.

Vasy : convert VHDL behaviour into VHDL data follow.

Boom : optimize data follow description.

Boog : logical synthesis.

Loon : cell drive ability adjustment

Ocp : cell placer

Nero : router

Ring : Ring synthesis and chip router

S2r : Create real layout

4.2 Logical synthesis

Try to make the logical synthesis by go to synthe-vhdl directory.

4.2.1 Simple logical circuit

Let make andlogic.sfl sample with 2 inputs and 1 output and operator AND.

Example 4.2.1

Input the next command :

A large amount of message appears and the logical synthesis is completed. Information on the area, delay time, and the use logic cell is shown in the message of the logical synthesis as follows.

Area on file andlogic.vst . 1250 lamda (with cell over routing).

Details

a2_x2: 1 (100%)

Total : 1

Critical path (no warranty) 324 ps from b to f

Viewing circuit map after synthesis

Creating circuit by command as follow.

Figure 4.2 shows result of synthesis of AND circuit with 2 input values.

Display layout LSI after Arrangement wiring

When we execute arrangement wiring command the layout of circuit is displayed. The virtual layout doesn't depend on the design rule at this stage.

Please note that a detailed display of the layout is not done and it also doesn't show the range of the layout display with the mouse when you select tools->Flat menu on the graal.

Figure 4.3 Display results of layout

Figure 4.2 Synthesis result of AND circuit

Figure 4.3: Layout of AND circuit

4.2.2 Add Circuit

Let create example called add.sfl. This example use operator add to add 2 input values and return 1 output.

Input command line as follow.

A large amount of message appears and the logical synthesis is completed. Information on the area, delay time, and the use logic cell is shown in the message of the logical synthesis as follows.

Area on file add.vst 24250 lamda (with over cell routing)

Details

xr2_x1 : 7 (64%)

buf_x2 : 1 (4%)

oa2ao222_x2 : 1 (10%)

a2_x2 : 1 (5%)

ao2o22_x2 : 1 (9%)

a3_x2 : 1 (6%)

Total : 12

Critical path (no warranty) 1846 ps from a 1 to f 3

The area of 2450 lamda^2 is expected with virtual arranged. From input a1 to output f3 have 1846ps is calculated.

In the figure 4.4 display the synthesis result

When we execute arrangement wiring command the layout of circuit is created. The virtual layout dose not depend on design rule in this stage.

Please note that a detailed display of the layout is not done and it also doesn't show the range of the layout display with the mouse when you select tools->Flat menu on the graal.

Figure 4.4 Synthesis result of add Circuit

Figure 4.5 Layout of add circuit

4.2.3 Register transfer in add circuit

Create example called adder.sfl that adds 4 bit input values then return output values after it is delayed by number of registers. Increase the number of registers to check the wiring of the clock signal.

A large amount of message appears and the logical synthesis is completed.

Information on the area, delay time, and the use logic cell is shown in the message of the logical synthesis as follows.

The area of 194000 lamda^2 is expected with virtual arranged. From input a0 to part of input register r1_3_ins has 2053ps is calculated.

The circuit is generated by following command.

Figure 4.6 Display map of result synthesis. The addition operation described with SFL is developed by operation description synthesis program vasy, and after the data flow is received and optimized by boom, boog converted it into the net list (structural description).

Figure4.6: Synthesis result of adder

Tool NameOptionExplain

Boom- l num

- d num

- i num Optimized level (0-3) default 0 (low level)

Delay optimization ratio default 0%

Repeat frequency

boog-m numOptimization mode Area : 04:delay

loon-m numOptimization mode Area : 04:delay

Table 4.2 : Optimized option of Alliance logical synthesis tool

4.3 Implement LSI layoutLSI__ LSI The result of executing logical synthesis a connection information of schematic diagram that is called a net list. LSI layout makes mask of information from the net list. Cell-base design layout operates putting cell line on the silicon and connections between cells by wiring.

LSI Delay of wiring is also very important in the system, so the both are related closely. Therefore, in the design large scale LSI it is important to viewing the delay after it wires for arrangement while reviewing the arrangement and logic synthesis, it also requires designer manages the floor plan.

4.3.1 Base Cell

LSI

LSI__ LSI' In the cell-based design the layout created in advance of the basic cells is combined to design for LSI. The LSI manufacturer provides a lot of basic cells, so it is difficult to switch the manufacturer. LSI has basic cell (95 kinds) of a virtual independent manufacturer and manufacture process to convert virtual place to real place according with the design file rule.

Alliance NAND

NOR_Figure 4.7: Example of layout of basis cell of Alliance with 2 inputs NAND circuit and 2 inputs NOR circuit in the figure from right side.

Figure 4.7 Basic cell of Alliance

4.3.2 Exercise wiring arrangement

Use the follow example to exercise wiring arrangement.

In this example executes operator AND logic for each bit and outputs the result. Because there is no relationship on each of the operator it is easy to make the wiring arrangement.

The first let make the net list.

Synthesize the circuit with following command.

Next, place the cell that is included in the net list on the silicon.

Figure 4.7 : Placed basic cells on the layout

(#-ring_ Figure 4.7 display basic cells on the layout. To see aspect of cells and connectors the inside of a cell does not expand. The top and bottom of layout of the modules and an external part with connection point (connector) is defined. The optional ring allows to place connector in the top and bottom of layout with random order.

Lets execute wiring for the layout of place.

Figure 4.9 layout of after wiring

tools_Flat__ AllianceAlliances2rFigure4.9 display layout of after wiring. Connector of the module is connected with basic input output connectors by aluminum wire.

To observe the level of non aluminum selects Flat from tools menu can enclose all layout with a mouse. Figure4.10 displays the layout after flattening.

It is different between the layout of created Alliance and actual mask pattern. With Appliance wiring arrangement only relate to the position of each element from using correct virtual rules. In the layout is created by using virtual rules the design of the actual conduct coordinated the mask pattern will be generated by using s2r tool.

Figure 4.10 Layout of after wiring (after flatting)

Cell nameDescription

pi_spInput exclusive pin

po_spOutput exclusive pin

pow_sp(#)

'Output exclusive pin (small drive capacity)

pio_sp3 state3 state output pin

piow_sp3 state(#)3 state output pin (small drive capacity)

piot_sp3 state3 state input pin

piotw_sp3 state(#)3 state input pin (small dive capacity)

pck_spClock input exclusive pin

pvdde_spIOIO power pin

pvsse_spIOIO ground pin

pvddi_spInternal power pin

pvssi_spInternal clock pin

pvddeck_spIOClock driver IO power pin

pvsseck_spIOClock driver IO ground pin

pvddick_spClock driver internal power pin

pvssick_spClock driver internal ground pin

4.3.3 Input output cell and chip layoutCMOSLSI LSI LSILSI In the normal CMOS circuit the LSI internal signal level is decided via supply voltage but in the input of LSI the large voltage may be applied by electrostatic, overshort, under short or when transportation or when implement,etc In case that to prevent destruction of LSI the circuit connected to the input and output pins will be made by special design. Next because the capacitance of LSI outside is very large, transistor with a large dirve capacity is required. In this input-output circuit there is the different requirement for internal circuit, so a special circuit and the layout is prepared. The basic cell implements the input-output circuit is called input output cell.

Alliance LSI5 LSIIO IO _LSI In the figure 4.3 the main input output cells name and functions are collected. In Alliance the input output cells are placed in the periphery of LSI. And on the input-output cells of the five aluminum wiring this LSI will be formed around the ring. This ring becomes ground wire from the outside IO, IO power wiring, power wiring inside the cells for input and output, input - output cell of the internal ground wire, wiring clock. In the input cells and internal part of circuit power line of more ring is created and they is strengthening. The internal power ring is the ground wire is inside from the outside and internal power supply wiring. To generate placing pins in the corner of LSI chips connect to the inner ring of circuit it requires the exclusive power pin.

LSILSI Alliance VHDL PADring ring 2.2 Ring chip.rin 4.1.1 The net list that includes input-output cells

To connect LSI internal circuit to input-output cells requires generating the net list with input-output cells is included in it. Next, when place input-output pin in the peripheral LSI location of physical pin is also required. In Alliance the first create description of structure VHDL and the second copy parameter file for PADring. Because in the circuit with small internal core of ring the wiring may be fail, the example 2.2 will synthesis for the circuit.

In figure 4.11 chip.rin is generated as parameter file of ring.

Figure 4.11 PAD ring router parameter file

Figure 4.12 LSI layout with input output cells

Now create LSI layout with the following commands.

LSI IO VHDL chip.vstchip.vst chip.cif Caltech Intermediate format(CIF) LSI[4]Alliance Figure 4.13 displays the description of structure VHDL(chip.vst) which describes required the IO PAD in the generated LSI layout. Here, in advance, note that the net list chip.vst is generated in directory. The LSI master information file chip.cif with cif is caltech intermediate format. In this exercise the mask pattern of virtual process 1.0 is attached to alliance but because of changing the design rule file other processes can be applied. Not copy code

4.4 Synthesis of logical hierarchy : Synthesis procedure of RISC processor SN/X.

: RISC SN/X Alliance1 SNXSNX In Alliance one module not only restrict in the one file. For example, when the logical file of SNX processor includes some modules then can not synthesize it. Remove SNX directory and try to create layout.

Create layout with the following procedure.

sfl2vh -split -p VHDL vasy-HVHDL vasy Alliance VHDL .vbe boog ocp nero SNX SN/X 4.14 With split option of vfl2vh you can split module in to separate files. Next, option p changes signal name in VHDL file that is created and it can not conflict with reserved word. Option H of vasy the hierarchical structure VHDL file is instructed. Because in the vasy the VHDL file of Alliance format of data follow with extension .vbe is outputted, so all file with extension .vbe is logical synthesized via boog. If synthesize completely ocp and nero will operates the wiring arrangement. If logical scale of SNX class is created then the wiring arrangement requires a considerable time.

After wiring arrangement SN/X layout is show in figure 4.14

Figure 4.14 the layout of SN/X processor after wiring arrangement.

4.5 From layout simulating SPICE circuit.

_____AllianceSPICE 2.1(andlogic.sfl)' andlogic.ap SPICE With Alliance the netlist can be exported from layout. Let simulate circuit by exporting SPICE netlist. Using example 2.1 (andlogic.sfl) in the exported netlist because of using the circuit with virtual places on it, incase can not output the virtual place file andlogic.ap please refer this chapter.

Depend on command try to create SPICE netlist.

Figure 4.15 Exported SPICE netlist

4.15_ SPICE_ 2 AND spice3 4.16 x0 1PE SPICE[9] andlogic.spice_SPICE3 Figure 4.15 displays exported SPICE netlist. The netlist is exported by connection of 2 input AND gate and inverter then can calculate floating capacity of netlist. Next try to verify the simulation of exported netlist by using spice3. Figure 4.16 displays the verifying simulation.

Includes the exported netlist and create an instance of sub circuit as 0x. Next, as capacity of circuit copy 1PE and specify supply voltage of pins and power for them. Then transistor model parameter and command are also included. About detail requirement for SPICE simulation please refer to literature [9]. Create simulation script file andlogic.spice and using spice3 to implement the simulation.

Figure 4.16 Example spice simulation script

___ Here input run command and execute it. When the simulation is finished, using the following commands to observe the wave of circuit.

4.17 4.18 SFL 19ff.sfl SPICE SPICE SPICE 4.204.5.1 4.20 (4.19)' SPICE i.f.m.clock Figure4.17 displays input-output voltage waveform. Figure 4.18 displays

supply current waveform. Figure 4.19 is file ff.sfl which is logic synthesized then creates SPICE netlist. In the exercise 4.5.1 using the script in figure 4.20 to simulate SPICE of circuit and displays waveform in each i,f,m and f clock.

Figure4.17 : The input-output voltage waveform of circuit simulation

Figure 4.19 : The supply current waveform of circuit simulation

Figure 4.20 : The circuit using register

4.5 Summary

AllianceSFL LSI Alliance VDEC[5] [3]Makefile 4.21 This chapter explains using logical synthesis of Alliance. It instructs that can create the exercise environment from SFL to LSI layout. By changing design rule of Alliance ( VDEC[5] etc) can create actually product. To exercise this chapter using the following Makefile displays on figure 4.21.

Figure 4.21: The exercise Makefile

Chapter 5. Practicing simulation by verilator with C language.

VerilatorC5.1 IntroductionSystemC Verilog Programming language Interface (PLI)' Because it is important to understand software-hardware-coding, so there are a lot of analyst of this topic. Although can use SystemC language to design hardware but in the nature language characteristic parallel not is considered, so it can describe or can not describe hardware by using instruction class. Verilog called Programming language Interface (PLI) with there are a lot of concept but because it opposites with interface of software, so it is difficult to use it.

1994Digital Equipment AlphaVerilogC (Verilator)Duane Galbi 1998GNU Public license 2002Wilson Synder C++Verilator Wilson Synder [10]In 1994 Digital Equipment company created verilator tool can convert verilog to C language to simulate for Alpha Processor. With the support of Duane Galbi in 1998 verilator tool is became open source with GNU public license. In 2002 Wilson Synder customized it to can convert verilog to C++ language. Now, verilator is active supported by Wilson Synder[10].

Verilator C++SystemC2C++Verilator C++

Using verilator tool can convert verilog to C++ language and System C but because we want to practice with only C++ language we use version for C++ language.

5.2 Logical simulation by verilator

Verilator5.1 Verilator Figure 5.1 displays environment simulation using verilator

Figure 5.1 : Environment simulation using verilator

SFLsfl2vlVerilog Verilator C++C dHDL C++I5.2 SFL 16SFL do VerilatorC++do exdo Verilator SFL Using vfl2vl tool to convert sfl source file to verilog file then using verilator to convert verilog file to C++ file and executes C++ file. Beginner can use C++ language as description hardware language. In the Figure 5.2 SFL describes a 16bit full adder counting device. In examples using SFL language usually use do but with C++ language can not use do because do is syntax in C++ language so we use exdo instead of do. In the verilator about operation (add etc) corresponding input which has the number of bits must match.

Figure 5.2 : Test Circuit

HDLC++Verilator V->eval()Figure 5.3 describes HDL by C++ script. By using verilator to generate instance of class include modules name with V at the first position. Using the syntax instance name-> terminal value can refer to terminal value of module (input variable, output variable etc), so it is important to setup information for simulating. To start testing the circuit we call method eval () follow syntax instance name ->eval().

0 eval() C++Verilator VL_PRINTF printf 5.410 C++2 inputs variable is set by random number and cin=0 then call eval() method. By using C++ to calculate in the module that describes adder circuit the output is displayed by VL_PRINT (other name of printf method) method.

Figure 5.4 displays result of simulation of test circuit.

Verilog 5.5 Verilog C++Verilog The corresponding simulation using verilog script is displayed in figure 5.5. Let compare content script of 2 languages we can see that the changing is very small.

VerilatorVerilog Verilator C Verilator CVerilator But note that with verilator can not observe the internal signal of module. Therefore, for begin design pattern use verilog language to observe internal signal and design logical for simulation circuit. When the pattern requires relative software we can link verilator to C language.

Let make example use simulation environment by go to the verilator directory.

Next to create module for simulation input follow command.

Execute module by input command

The result displays in figure 5.4

5.3 Logical Simulation with C language

CVerilator C C Because there are a lot of people who always use C language this topic shows how to using C language to describe hardware base on verilator.

Figure 5.6 : Test script with C language

Figure 5.7 : Simulation environment with C language

5.6 C5.3 main() C (excla()) excla() C++C extern CBC++5.7 cla16_main2.ccDifferent with figure 5.3 where to call hardware execution we use staff method (eval()) in the figure 5.6 with C language we instead of excla() function in the main() function for it. Function excla() is used for both C and C++ when use C language you have to declare extern C for this function. When use only C++ thats declare is unnecessary.

The script C language called cla16_main2.cc. Let create the new implement script.

Next execute the following command.

5.45.3.1 _ The result of implement simulation is displayed in figure 5.4

5.4 Sequence Circuit Simulation

0(eval())' 1 0 125.8 The sequence circuit includes signal clock and signal reset. The concept time is included along with introduction of the signal clock. When the clock signal is leading, register value is updated for single phase synchronous circuit. When calling eval() method in the 1 clock if signal is 0 then terminal value is set to 0 and if signal is 1 terminal value is set to 1 and data is transferred by internal module. Figure 5.8 displays concept of sequence circuit simulation.

Figure 5.8 : Simulation sequence circuit with verilator.

Figure 5.9 : sequence circuit example

5.9 r out 1 5.10 (p_reset)' 1 (m_clock)0(eval())' 1 SFL 1 Let explain example in figure 5.9. The result of add circuit before transfer to terminal out of circuit it is recorded in the writeable register r. In the main loop when clock signal is 0 terminal value is set and execute eval() method then when clock signal is 1 second time eval() method is executed. In the circuit is described by SFL language because when clock signal is leading the register value is set, so the external signal or terminal value is set before clock signal become 1.

Figure 5.10 : Script of sequence circuit simulation

SFLrcla16.sflrcla16_main.cc

From SFL source file rcla.sfl let implement simulation with C language in script file called rcla16_main.cc.

5.11 1 Figure 5.11 displays result we can see output of add circuit is late 1 clock.

Figure 5.11 : Result of implement sequence circuit

5.5 Example Simulation Processor.

RISC CPU SN/XVerilator 5.12 RISC CPU SN/X snx->mclock 0 _ snx_main.cc

Let simulate RISC CPU SN/X by using verilator. Figure 5.12 displays test script of RISC CPU SN/X simulation. The value of snx->mclock is reversed at each loop and it is updated for reference memory when clock signal is 0.This script called snx_main.cc. Let create implement script with new format.

Next execute the following command.

20Verilog Icarus Verilog In this simulation there are 20 line instruction is implemented. Not that we have to create verilog script in the same directory then implement this simulation by using Icarus Verilog.

. Icarus verilog /dev/null Because it is difficult to understand how much difference performance of speed is flowed in the screen, so the time is measured. Let measure when Icarus verilog command is used. Because the screen display is a big overhead, so redirect standard output to /dev/null directory.

5.5.1 Icarus VerilogIcarus verilog Verilator 10 The time of implement icarus is little difference in each implement.

Create the implement format by Icarus verilog and by verilator 10 times and average the performance magnification. This is require for exercise 5.5.1.

Figure 5.12 : Processor test script

Figure 5.13 : Makefile

5.6 Summary VerilatorC Incarus VerilogMakefile 5.13 This chapter explains how to use verilator to logical simulate hardware base on C language. Compare with when use incarus verilog speed is faster. It is also to operate hardware-software-coding. Therefore there are a lot of tools are created for efficient development.

Figure 5.13 shows makefile is used for this exercise.

Chapter VI Processor Design

6.1 Introduction

The exercise of this chapter is everyone can understand microprocessor design via design of SN/X CPU that have 16bit RISC processor. The SN/X is based on architecture designed for practicing in Tokai University that are instruction set and register structure written in easy samples program by C language with minimum composition. Concretely As for the register that have only 4 registers, instruction and data length fixed at 16 bits, through Harvard architecture that is independence of data instruction bus, three address method is adopted. Please see [1] for details of the processor, architecture, and the compiler.

This exercise performs is shown below:

RISC architecture SN/X explanation

Processor hardware structure

SN/X SFL description

Logic simulation

ALTERA CPLD mapping

6.2 RISC architecture SN/X

I think you have ever heard a word as RISC. Unlike using compiler, in CPU complex instruction is stopped, can be built under the idea that the high-performance system in a compact way, this is called the architecture of the compact instruction set and hardware configuration. By improving the compiler technology, from 80s to 90s despite of variety of RISC architecture has been released. Many fixed-length and three-operand instruction (address) system is adopted.

Because SN/X is used to take classes in the high level language and processor instruction concerned, So it is designed with the goal of simplifying the hardware configuration to run simple subset of high-level language as well as possible. As a similar result with RISC architecture, in 80s the MIPS architecture was appeared. Unlike the MIPS, assembler level program has not used LOAD, STORE, and DELAYetc for simple programs.

Figure 6.1 Essential diagram of SN/X Processor.

6.2.1 Basic operation of the processor.

The execution of processor is begun when instructions fetch from memory that contains the instructions. In SN/X instruction and data that are stored separately, but this structure is called as Harvard architecture. Processor can know what instruction address is fetched in instruction memory that remembered PC (program counter) in special register. The value of PC will be set to 0 when power is off or reset. Then SN/X will start execute instruction form 0th address of memory.

Instruction read from the instruction memory stored in the instruction register (OP), the next depending on hardware its contents will be interpreted. Instruction decoded step is called. After confirming the type of instruction based on the result of the instruction decode, instruction will be executed depending on type of instruction.

After the instruction execution, the program counter is incremented by 1, instruction that lined up in memory is fetching and executing repeatedly.

In SN/X, the operation is implemented with all 16-bit integer represented in two's complement

Figure 6.2 Operation of SN/X Instruction flow.

Instruction format

FormatStructure

R FormatOPR2R3R1

I FormatOPR1R2I

With the operation that use instruction as in table 6.1. In this table OP is represented as operand with 16bit number value. That is not only a register in instruction, the instruction that use group instruction immediately represented as number called instruction format I. Instruction format is defined with 5 types as table 6.2 below.

ActionInstructionOPOperandMeaning

AddADD0Rd, Rsa, RsbRdRsa + Rsb

AndAND1Rd, Rsa, RsbRdRsa & Rsb

CompareSLT3Rd, Rsa, RsbRd(Rsa < Rsb)?1:0

NegateNOT4Rd, Rsa, RsbRd not Rs

Right ShiftSR6Rd, Rsa, RsbRd0b0 ||Rs151

HaltHLT7Processor halt

OperandRd = R1, Rsa = R2, Rsb = R3, Rs = R2

Table 6.1 Implementation of R Format Instructions.

ActionInstructionOPOperandMeaning

LoadLD8Rd, I(Rb)RdDMEM[ea]

StoreST9Rs, I(Rb)RdRsa & Rsb

Load AddressLDAARd, I(Rb)Rdea

Branch zeroBZERc, I(Rb)Rd(Rc==0)?ea:PC

Branch Access LinkBALFRd, I(Rb)PCea,RdPC+1

OperandRd = R1, Rs = R1, Rc = R1, Rb = R2

Effective addressEaI(Rb)Ea(8#I7||I) + (Rb ==$0)?0:Rb

Table 6.1 Implementation of I Format Instruction.

6.3 SN/X practice package

This package includes assembly, compiler for practicing SN/X. The structure of directory in package is shown in figure 6.3 below. This package is constituted compiler source code group, SN/X assemble, SN/X logic file and simulation environment.

cd CPU

Please Type command above to go to the directory containing CPU package.

Figure 6.3 Organization of SN/X package

Compiler use Yacc and lex compiler to describe grammar language programming, because of using C language to generate code, so these simple samples are written in C language. A specification of the language compiler is summarized in the next.

Variable: When the global variables (a-z) fetched from 1th address of memory, the argument of function (arg) is only allowed. Variable can give the index from 0 to 26 (a-z), for example a[0] is a, a[26] is z.

Function/method: The function can be defined only with name as foo and type of Integer or, local variables is not used.

Operand: Some of operands are using as +, -, , >=,