introduction to asynchronous circuit design: specification and synthesis
DESCRIPTION
Introduction to asynchronous circuit design: specification and synthesis. Part II: Synthesis of control circuits from STGs. Outline. Overview of the synthesis flow Specification State graph and next-state functions State encoding Implementability conditions Speed-independent circuit - PowerPoint PPT PresentationTRANSCRIPT
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Introduction toasynchronous circuit design:
specification and synthesis
Part II:Synthesis of control circuits
from STGs
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Outline
• Overview of the synthesis flow• Specification• State graph and next-state functions• State encoding• Implementability conditions• Speed-independent circuit
– Complex gates– C-element architecture
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Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
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x
y
z
x+
x-
y+
y-
z+
z-
Signal Transition Graph (STG)
xy
z
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x
y
z
x+
x-
y+
y-
z+
z-
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x+
x-
y+
y-
z+
z-
xyz000
x+
100y+z+
z+y+
101 110
111
x-
x-
001
011y+
z-
010
y-
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xyz000
x+
100y+z+
z+y+
101 110
111
x-
x-
001
011y+
z-
010
y-
Next-state functions
x z x y ( )
y z x
z x y z
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Next-state functions
x z x y ( )
y z x
z x y z
x
zy
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Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
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VME bus
DeviceLDS
LDTACK
D
DSr
DSw
DTACK
VME BusController
DataTransceiver
Bus DSr
LDS
LDTACK
D
DTACK
Read Cycle
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STG for the READ cycle
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
LDS
LDTACK
D
DSr
DTACK
VME BusController
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Choice: Read and Write cycles
DSr+
LDS+
LDTACK+
D+
DTACK+
DSr-
D-
LDS-
LDTACK- DTACK-
DSw+
D+
LDS+
LDTACK+
D-
DTACK+
DSw-
LDS-
LDTACK-DTACK-
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Choice: Read and Write cycles
DTACK-
DSr+
LDS+
LDTACK+
D+
DTACK+
DSr-
D-
LDS-
LDTACK-
DSw+
D+
LDS+
LDTACK+
D-
DTACK+
DSw-
LDS-
LDTACK-DTACK-
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Choice: Read and Write cycles
DTACK-
DSr+
LDS+
LDTACK+
D+
DTACK+
DSr-
D-
LDS-
LDTACK-
DSw+
D+
LDS+
LDTACK+
D-
DTACK+
DSw-
LDS-
LDTACK-DTACK-
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Choice: Read and Write cycles
DTACK-
DSr+
LDS+
LDTACK+
D+
DTACK+
DSr-
D-
LDS-
LDTACK-
DSw+
D+
LDS+
LDTACK+
D-
DTACK+
DSw-
LDS-
LDTACK-DTACK-
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Circuit synthesis
• Goal:– Derive a hazard-free circuit
under a given delay model andmode of operation
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Speed independence
• Delay model– Unbounded gate / environment delays– Certain wire delays shorter than certain paths in the
circuit
• Conditions for implementability:– Consistency– Complete State Coding– Persistency
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Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
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STG for the READ cycle
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
LDS
LDTACK
D
DSr
DTACK
VME BusController
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Binary encoding of signals
DSr+
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDS-LDS-LDS-
LDTACK- LDTACK- LDTACK-
D-
DSr-DTACK+
D+
LDTACK+
LDS+
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Binary encoding of signals
DSr+
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDS-LDS-LDS-
LDTACK- LDTACK- LDTACK-
D-
DSr-DTACK+
D+
LDTACK+
LDS+
10000
10010
10110 01110
01100
0011010110
(DSr , DTACK , LDTACK , LDS , D)
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QR (LDS+)QR (LDS+)
QR (LDS-)QR (LDS-)
Excitation / Quiescent Regions
ER (LDS+)ER (LDS+)
ER (LDS-)ER (LDS-)
LDS-LDS-
LDS+
LDS-
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Next-state function
0 1
LDS-LDS-
LDS+
LDS-
1 0
0 0
1 1
1011010110
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Karnaugh map for LDS
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
LDS = 0 LDS = 1
0 1-0
0 0 0 0 0 0/1?
1
111
-
-
-
---
- - - -
-
- ---
- - -
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Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
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Concurrency reduction
LDS-LDS-
LDS+
LDS-
1011010110
DSr+
DSr+
DSr+
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Concurrency reduction
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
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State encoding conflicts
LDS-
LDTACK-
LDTACK+
LDS+
10110
10110
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Signal Insertion
LDS-
LDTACK-
D-
DSr-
LDTACK+
LDS+
CSC-
CSC+
101101
101100
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Specification(STG)
State Graph
SG withCSC
Next-state functions
Decomposed functions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
DesignDesignflowflow
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Complex-gate implementation
)(csccsc
csc
csc
LDTACKDSr
LDTACKD
DDTACK
DLDS
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Implementability conditions
• Consistency– Rising and falling transitions of each signal
alternate in any trace
• Complete state coding (CSC)– Next-state functions correctly defined
• Persistency– No event can be disabled by another event
(unless they are both inputs)
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Implementability conditions
• Consistency + CSC + persistency
• There exists a speed-independent circuit that implements the behavior of the STG
(under the assumption that ay Boolean function can be implemented with one complex gate)
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Persistency
100 000 001a- c+
b+ b+
ac
b
a
c
bis this a pulse ?
Speed independence glitch-free output behavior under any delay
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a+
b+
c+
d+
a-
b-
d-
a+
c-a-
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
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0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
abcd 00 01 11 10
00
01
11
10 1
1 1 11
10
0 000
ER(d+)
ER(d-)
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abcd 00 01 11 10
00
01
11
10 1
1 1 11
10
0 000
caadd
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
Complex gate
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Implementation with C elements
CR
S z
• • • S+ z+ S- R+ z- R- • • •
• S (set) and R (reset) must be mutually exclusive• S must cover ER(z+) and must not intersect ER(z-) QR(z-)• R must cover ER(z-) and must not intersect ER(z+) QR(z+)
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abcd 00 01 11 10
00
01
11
10 1
1 1 11
10
0 000
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
CS
Rdc
ca
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0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
CS
Rdc
ca
but ...
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0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
CS
Rdc
ca
Assume that R=ac has an unbounded delayStarting from state 0000 (R=1 and S=0):
a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ;
R+ disabled (potential glitch)
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abcd 00 01 11 10
00
01
11
10 1
1 1 11
10
0 000
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
CS
Rdc
cba
Monotonic covers
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C-based implementations
CS
Rdc
cba Cd
ab
c
a
b
cd
weak
a
cd
generalized C elements (gC)
weak
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Speed-independent implementations
• Implementability conditions– Consistency– Complete state coding– Persistency
• Circuit architectures– Complex (hazard-free) gates– C elements with monotonic covers– ...
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Synthesis exercise
y-
z- w-
y+ x+
z+
x-
w+
1011
0111
0011
1001
1000
1010
0001
0000 0101
0010 0100
0110
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
Derive circuits for signals x and z (complex gates and monotonic covers)
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Synthesis exercise
1011
0111
0011
1001
1000
1010
0001
0000 0101
0010 0100
0110
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
wxyz 00 01 11 10
00
01
11
10
----
Signal x
1
0
1
1
1
1
1
0 0
0
0
0
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Synthesis exercise
1011
0111
0011
1001
1000
1010
0001
0000 0101
0010 0100
0110
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
wxyz 00 01 11 10
00
01
11
10
----
Signal z
1
0 0
0
0
11 1
0
0 0
0