Introduction to FPGAs & Its

Applications

Presented by: Mohammad Ebrahimi

IPM – Institute for Research in Fundamental Sciences

Outline

What is an FPGA

FPGA structure

What’s inside – Core components

FPGA design flow overview

FPGA applications

A brief look at our project

Conclusion

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What is an FPGA

FPGAs (is an acronym for field-programmable

gate array) are integrated circuits that enable

designers to program customized digital logic in

the field

An FPGA is a semiconductor device on which its

function can be defined and modified even after

manufacturing

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ASIC as a competitor

4

ASIC stands for Application Specific Integrated

Circuit

A chip which serves the purpose for which it has

been designed and cannot be reprogrammed or

modified to perform another function

Designers have to engage with hardware details at

the lowest levels (layout and transistors)

FPGA vs ASIC

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FPGA Architecture

Xilinx FPGA

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FPGA Architecture

Configurable logic block (CLB)

GRM

slices

Xilinx FPGA

7

FPGA Architecture

Configurable logic block (CLB)

GRM

slices

Xilinx FPGA

8

FPGA Architecture

Configurable logic block (CLB)

GRM

slices

Xilinx FPGA

9

FPGA Architecture

Configurable logic block (CLB)

GRM

slices

Xilinx FPGA

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FPGA Architecture

Configurable logic block (CLB)

GRM

slices

A B C D

Lookup Table (LUT)

‘0’

0

1

1

1

1

1

1

1

0

1

0

0

1

0

1

0

Xilinx FPGA

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FPGA Architecture

Configurable logic block (CLB)

GRM

slices

A B C D

Lookup Table (LUT)

‘0’

0

1

1

1

1

1

1

1

0

1

0

0

1

0

1

0

Boolean Function

F(A,B,C,D)

Xilinx FPGA

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FPGA Architecture

Xilinx FPGA

BRAM

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Multipliers or DSP blocks

High speed serial IOs (gigabit transceivers)

Clocking resources

I/O (Input/Output)

PCIe block

SERDES

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What’s inside – Core components

Implementation flow (Synthesis)

15

Register

a

b

output

clk

reset

clear

D Q

process(clk, reset)

begin

if reset = ‚1‘ then

output <= ‚0‘;

elsif rising_edge(clk) then

output <= a XOR b;

end if;

end process;

HDL

(VHDL /

Verilog)

Synthesize

Netlist

Map

Place

Route

Bitstrea

m

FPGA design flow (Mapping)

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HDL

(VHDL /

Verilog)

Synthesize

Netlist

Map

Place

Route

Bitstrea

m

Register

a

b

output

clk

reset

clear

D Q

FPGA design flow (Place&Route)

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HDL

(VHDL /

Verilog)

Synthesize

Netlist

Map

Place

Route

Bitstrea

m

Data analytics

Telecommunication

Artificial Intelligence

Video processing

Cyber security

Genomics

Aerospace & defense

High energy physics

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FPGA Applications

For example, in CMS upgrade project, each FPGA

performs a real-time process on 96 active input

channels in parallel

CPU based platforms cannot meet performance

and power requirements

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FPGA High energy physics

Single Event Upset (SEU) problem

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Configuration memory bits

CLB slice

LUT

Single Event Upset (SEU) problem

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Configuration memory bits

CLB slice

LUT

Single Event Upset (SEU) problem

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Configuration memory bits

CLB slice00

01

01

11

0

00

101

11

I1 I2 I3 I4

LUT

LUT

Single Event Upset (SEU) problem

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Configuration memory bits

CLB slice00

01

01

11

0

00

101

11

I1 I2 I3 I4

LUT

routing

LUT

Single Event Upset (SEU) problem

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Solution: Scrubbing Configuration Data

SRAM-based FPGA

OSC

INIT

DONE

CCLK

OE/RESET

CLK

XQR18V04

DATA[7:0] DATA[7:0]

CE

WR

GND

OE/RESET

CLK

XQR18V04

DATA[7:0]

CE

I/O

GND

CS

BOOT

SCRUB

• No application interruption

PROM

00000001010

10101010100

10101010010

10101010101

01010100101

11111111101

11100000000

11101010101

10101010101

00101000010

00000001010

10101010100

10101010010

10101010101

01010100101

11111111101

11100000000

11101010101

10101010101

00101000010

I/O

I/O

I/O

SCRUB

Controller

I/O

Configuration bits

Original bitstream

10101000101

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SRAM-based FPGA

OSC

INIT

DONE

CCLK

OE/RESET

CLK

XQR18V04

DATA[7:0] DATA[7:0]

CE

WR

GND

OE/RESET

CLK

XQR18V04

DATA[7:0]

CE

I/O

GND

CS

BOOT

SCRUB

• No application interruption

PROM

00000001010

10101010100

10101010010

10101010101

01010100101

11111111101

11100000000

11101010101

10101010101

00101000010

00000001010

10101010100

10101010010

10101000101

01010100101

11111111101

11100000000

11101010101

10101010101

00101000010

I/O

I/O

I/O

SCRUB

Controller

I/O

Configuration bits

Original bitstream

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Solution: Scrubbing Configuration Data

ScrubColumn

x

Configuration

Upset

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Solution: Scrubbing Configuration Data

ScrubColumn

x

Configuration

Upset

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Solution: Scrubbing Configuration Data

ScrubColumn

x

Configuration

Upset

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Solution: Scrubbing Configuration Data

ScrubColumn

x

Configuration

Upset

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Solution: Scrubbing Configuration Data

ScrubColumn

Configuration

Upset

Repaired

Scrubbing can be performed:

from outside the FPGA by another FPGA controller

from inside the FPGA: Internal Configuration Access Port (ICAP)

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Solution: Scrubbing Configuration Data

Conclusion

A brief look at the FPGA structure

Discussion about Implementation flow of FPGA

based designs

Introduction to wide usage of FPGAs in modern

applications

A brief look at our solution to make commercial

FPGAs reliable for using in safety-critical

applications

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