introduction to msp430 family

INTRODUCTION TO MSP430 FAMILY

1 PREPARED BY: JEEVA.B ASSISTANT PROFESSOR / ECE, N.I.T. RAICHUR.



Description:

The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 s.

The MSP430F20xx series is an ultra-low-power mixed signal microcontroller with a built-in 16-bit timer and ten I/O

pins. In addition, the MSP430F20x1 has a versatile analog comparator. The MSP430F20x2 and MSP430F20x3 have

built-in communication capability using synchronous protocols (SPI or I2C) and a 10-bit A/D converter

(MSP430F20x2) or a 16-bit sigma-delta A/D converter (MSP430F20x3).

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then

process the data for display or for transmission to a host system. Stand alone RF sensor front end is another area of

application.

Salient Features of MSP430:

Low Supply Voltage Range 1.8 V to 3.6 V

Ultra-Low Power Consumption

o Active Mode: 220 A at 1 MHz, 2.2 V

o Standby Mode: 0.5 A

o Off Mode (RAM Retention): 0.1 A

Five Power-Saving Modes

Ultra-Fast Wake-Up From Standby Mode in Less Than 1 s

16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time

Basic Clock Module Configurations:

o Internal Frequencies up to 16 MHz With Four Calibrated Frequencies to 1%

o Internal Very Low-Power Low-Frequency Oscillator

o 32-kHz Crystal

o External Digital Clock Source

16-Bit Timer_A With Two Capture/Compare Registers

On-Chip Comparator for Analog Signal Compare Function or Slope A/D (MSP430F20x1)

10-Bit 200-ksps A/D Converter With Internal Reference, Sample-and-Hold, and Autoscan (MSP430F20x2)

16-Bit Sigma-Delta A/D Converter With Differential PGA Inputs and Internal Reference (MSP430F20x3)

Universal Serial Interface (USI) Supporting SPI and I2C (MSP430F20x2 and MSP430F20x3)

Brownout Detector

Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by

Security Fuse

On-Chip Emulation Logic With Spy-Bi-Wire Interface

Family Members:

o MSP430F2001: 1KB + 256B Flash Memory, 128B RAM






Available in 14-Pin Plastic Small-Outline Thin Package (TSSOP), 14-Pin Plastic Dual Inline Package (PDIP),

and 16-Pin QFN

For Complete Module Descriptions, See the MSP430x2xx Family User's Guide (SLAU144)



Block diagram of MSP430 family:

Figure above shows a block diagram of the F2013. These are its main features:

On the left is the CPU and its supporting hardware, including the clock generator. The

emulation, JTAG interface and Spy-Bi-Wire are used to communicate with a desktop computer

when downloading a program and for debugging.

The main blocks are linked by the memory address bus (MAB) and memory data bus(MDB).

These devices have flash memory, 1KB in the F2003 or 2 KB in the F2013, and128 bytes of

RAM.

Six blocks are shown for peripheral functions (there are many more in larger devices). All

MSP430s include input/output ports, Timer A, and a watchdog timer, although the details differ.

The universal serial interface (USI) and sigmadelta analog-to-digital converter (SD16_A) are

particular features of this device.



The brownout protection comes into action if the supply voltage drops to a dangerous level.

Most devices include this but not some of the MSP430x1xxfamily.

There are ground and power supply connections. Ground is labeled VSS and is taken to define

0 V. The supply connection is VCC. For many years, the standard for logic was VCC=+5 V but

most devices now work from lower voltages and a range of 1.83.6 V is specified for the F2013.

The performance of the device depends on VCC. For example, it is unable to program the flash

memory if VCC



Central Processing Unit (MSP430 CPU) :

The RISC type architecture of the CPU is based on a short instruction set (27 instructions), interconnected

by a 3-stage instruction pipeline for instruction decoding.

The CPU has a 16-bit ALU, four dedicated registers and twelve working registers, which makes the

MSP430 a high performance microcontroller suitable for low power applications.

The addition of twelve working general purpose registers saves CPU cycles by allowing the storage of

frequently used values and variables instead of using RAM.

The orthogonal instruction set allows the use of any addressing mode for any instruction, which makes

programming clear and consistent, with few exceptions, increasing the compiler efficiency for high-level

languages such as C.



1 Arithmetic Logic Unit (ALU)

The MSP430 CPU includes an arithmetic logic unit (ALU) that handles addition, subtraction, comparison

and logical (AND, OR, XOR) operations. ALU operations can affect the overflow, zero, negative, and

carry flags in the status register.

2 MSP430 CPU registers

The CPU incorporates sixteen 16-bit registers:

four registers (R0, R1, R2 and R3) have dedicated functions;

there are 12 working registers (R4 to R15) for general use.

R0: Program Counter (PC)

The 16-bit Program Counter (PC/R0) points to the next instruction to be read from memory and executed

by the CPU. The Program counter is implemented by the number of bytes used by the instruction (2, 4, or

6 bytes, always even). It is important to remember that the PC is aligned at even addresses, because the

instructions are 16 bits, even though the individual memory addresses contain 8-bit values.

R1: Stack Pointer (SP)

The Stack Pointer (SP/R1) is located in R1.

1st: stack can be used by user to store data for later use (instructions: store by PUSH, retrieve by POP);

2nd

: stack can be used by user or by compiler for subroutine parameters (PUSH, POP in calling routine;

addressed via offset calculation on stack pointer (SP) in called subroutine);

3rd

: used by subroutine calls to store the program counter value for return at subroutine's end (RET);

4th: used by interrupt - system stores the actual PC value first, then the actual status register content (on

top of stack) on return from interrupt (RETI) the system get the same status as just before the interrupt

happened (as long as none has changed the value on TOS) and the same program counter value from

stack.

R2: Status Register (SR)

The Status Register (SR/R2) stores the state and control bits. The system flags are changed automatically

by the CPU depending on the result of an operation in a register. The reserved bits of the SR are used to

support the constants generator.



R2/R3: Constant Generator Registers (CG1/CG2)

Depending of the source-register addressing modes (As) value, six commonly used constants can be

generated without a code word or code memory access to retrieve them.

This is a very powerful feature, which allows the implementation of emulated instructions, for example,

instead of implementing a core instruction for an increment, the constant generator is used.

R4 - R15: GeneralPurpose Registers

These general-purpose registers are used to store data values, address pointers, or index values and can be

accessed with byte or word instructions.



Addressing Modes:

The MSP430 architecture supports a relatively rich set of addressing modes. Seven of addressing modes

can be used to specify a source operand in any location in memory, and the first four of these can be used

to specify the source/destination operand. Figure below illustrates the syntax and give a short description

of the addressing modes. The addressing modes are encoded using As and Ad address specifiers in the

instruction word, and the first column shows how they are encoded.

Instruction set :

The MSP430 instruction set consists of 27 core instructions. Additionally, it supports 24 emulated

instructions. The core instructions have unique op-codes decoded by the CPU, while the emulated ones

need assemblers and compilers to generate their mnemonics.

There are three core-instruction formats:

Double operand;

Single operand;

Program flow control - Jump.

Byte, word and address instructions are accessed using the .B,.W or , A extensions. If the extension is

omitted, the instruction is interpreted as a word instruction.

introduction to msp430 family

Documents

b ram o msp430f2011

b ram o msp430f2002

b ram o msp430f2012

b ram o msp430f2003

b ram o msp430f2013

b flash memory

b ram available

o msp430f2001