introduction to the virtuoso rf solution for co-design of rf chips and...

Introduction to the Virtuoso RF Solution for Co-Design of RF Chips and Modules

NameDateTitle

2 © 2018 Cadence Design Systems, Inc. All rights reserved.

Outline

Introduction

Overview - Virtuoso® RF Solution

Summary


System Design Enablement (SDE): Thinking Outside the Chip…

Partnerships with Ecosystem Leaders

Mobile Consumer Medical Automotive Cloud

Datacenter

Aerospace

& Defense

CHIPDesign and implementation

IP/SoC verification

Software drivers

SYSTEM

INTEGRATION

System analysis

HW-SW verification

Software applications

Software development

PACKAGE and

BOARD

Advanced package design

and analysis

PCB design and analysis

IP


How is RF Design Evolving?

• RF design complexity is rapidly outpacing traditional, disjointed

design flows

• Market is rapidly expanding: 5G (24-40GHz), automotive (77-81 GHz)

• Module content is increasing: 5-6 technologies (CMOS, SOI, GaAs,

GaN, SMD, laminate, package). With BAW, SAW, and FBAR filters,

up to 20 ICs in an RF module

• Reduced packaging size does not allow for traditional RF type design

flow

• 10 years ago

– RF designs smaller in size and complexity

– Majority of design effort in electrical design

– Because of the physical design simplicity, minimal

verification needed a small portion of design time

• Today

– Overall RF design effort larger

– Verification has dramatically increased as part of the flow

and in some flows is a larger effort than the RF design

itself

10 years ago


Aerospace & DefenseIntegration of III-V devices

with focus on reliability.

Goal: Reduce the size/weight

of the PCB by integrating

bare, un-package dies into

a single design

Disaggregated SoCAlternative to Moore’s Law and

dimensional scaling of a single device.

Leverage design re-use paradigm that

drove SoC with blocks built from varying

nodes, integrating them on a single device.

Smart PhonesProvide self-contained analog/RF

systems/subsystems in a single package.

Goal: Simplify the PCB-level requirements

by integrating multiple bare die in a

in a reduced form-factor required to fit

into handheld commercial devices.

Multi-Chip Module

(MCM)

System in a Package (SiP)

RF Module Heterogeneous Integration

PCB Style Design Flows IC Style Design Flows

1970 2005 Future

2.5D & 3D ICThree-dimensional stacking for memory

and CMOS image sensors. Processor

with 3D memory stacks, integrated on a

silicon interposer

Now

How is Advanced Packaging Evolving?


Outline

Introduction


Summary


Expanding Virtuoso Analog/RF IC Platform to Support Multi-Chip (PDK) Package/Module Designs


Virtuoso RF Solution Extends Virtuoso System Design Platform

• “Cadence and National Instruments announce collaboration to simplify next-generation semiconductor and RF development”

• Complete Virtuoso® RF Solution targeting next-gen wireless applications (5G)

• Module/package-level layout now supported within Virtuoso platform

– “Edit-in-Concert” functionality supports concurrent editing of die and module/package

• Sigrity™ technology for on-chip and off-chip device-level modeling

– Extends Sigrity integration to Virtuoso Layout Suite

• Integrated AXIEM solver from NI– Planar solver for on-chip and off-chip device-

level and antenna modeling– Transistor-level correlation between Spectre®

simulation and AWR Microwave Office, targeting III-V devices

9 © 2018 Cadence Design Systems, Inc. All rights reserved. Virtuoso Platform Virtuoso Platform

GaNGaAsCMOS

Hierarchical Top-Level Schematic

Representing Complete System-Level Design

Allegro Package-Level

Footprints

Virtuoso Symbol Virtuoso Symbol

Cadence® SiP Layout

Non-Native IC Layout

Interconnect

ParasiticsHPJ

RSTKEY

AUD

VID

VSS

RX1TX1

VCC

RGBS

Device

Models

Package

Lib

Allegro

PCB

Virtuoso Symbol

“Chips” Cell View

Virtuoso Layout Suite

OASiP

Cadence Sigrity technology

NI AXIEM

Virtuoso System Design Platform/Virtuoso RF Solution Design Flow


Why RFIC Designers Should Consider Changing Their Existing Methodology?

• Why extend Virtuoso® Layout Suite for package/module layout?

– The RFIC/module flow dictated, to a large extent, by IC designers

– Existing approach of adding additional metal layers in IC PDK to represent the packaging layers is no longer required. Process/flow is now formalized

– Virtuoso platform is tool of choice for many analog and RFIC designers. Virtuoso RF Solution provides familiar Virtuoso capabilities, e.g., gen from source, layout versus schematic, check against source, connectivity extraction, design rule checking, etc. for module/package layout

– Leveraging same EM modeling engines and methodologies for on-chip and off-chip structures

– Concurrent editing of ICs and package/module simplifies process of creating optimized systems and subsystems


Outline

Introduction


Summary


ICADVM

18.1

Virtuoso® solution for RFIC and RF module co-design

Enables module-level design in Virtuoso Layout Suite

Provides seamless integration of Sigrity™ and

AXIEM™ 3D EM solvers to Virtuoso Layout Suite

Direct interoperability with Cadence SiP Layout

© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of

Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

http://www.cadence.com/go/trademarks

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