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ECE 322
Digital Design with VHDL
Introduction to VHDL #3
Lecture 7,8,9,10
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VHDL Modeling Styles
Components and
interconnects
Structural
VHDL Modeling
Styles
Dataflow
Concurrent
statements
Behavioral
(sequential)
• Registers
• State machines
• Decoders
Sequential statements
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VHDL Modeling Styles-Dataflow Modeling
Dataflow modeling- describes how data moves through the system and the various processing steps.
Dataflow uses series of concurrent statements
Dataflow is the most useful style to describe combinational logic
Dataflow code also called “concurrent” code
Concurrent statements are evaluated at the same time; thus, the order of these statements doesn’t matter.
This is not true for sequential/behavioral statements!
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VHDL Modeling Styles-Dataflow Modeling
Example: XOR3
U1 <= A XOR B;
Result <= U1 XOR C;
Result <= U1 XOR C;
U1 <= A XOR B;
These two orders are the same
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VHDL Modeling Styles-Dataflow Modeling
Example: XOR3
LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity xor3_gate is
port(
A,B,C : in std_logic;
Result : out std_logic);
end xor3_gate;
Architecture dataflow of xor3_gate is
signal U1 : std_logic;
begin
U1 <= A xor B;
Results <= U1 xor C;
end dataflow;
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VHDL Modeling Styles-Structural Modeling
Structural design is the simplest to understand. This style is
the closest to schematic capture and utilizes simple building
blocks to compose logic functions.
Components are interconnected in a hierarchical manner.
Structural descriptions may connect simple gates or
complex, abstract components.
Structural style is useful when expressing a design that is
naturally composed of sub-blocks.
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VHDL Modeling Styles-Behavioral Modeling
Behavioral modeling describes the function or expected
behavioral of the design in an algorithmic manner
This style is the closest to a natural language description of
the circuit functionality
Usually described using process block statements which
encapsulate collections of actions executed in sequence
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VHDL Modeling Styles-Behavioral Modeling
Process block – Syntax
The first line of the process statement includes a label, the
keyword process, and an optional list of signals, known as
the sensitivity list.
Process_label : process (sensitivity list)
-- declarations
Begin
-- sequential statements
end process;
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VHDL Modeling Styles-Behavioral Modeling
A process with a sensitivity list is evaluated during simulation
whenever an event occurs on any of the signals in the
sensitivity list (and only then).
If a process has no sensitivity list then it is evaluated when
an event occurs on any signal.
Process_label : process (sensitivity list)
-- declarations
Begin
-- sequential statements
end process;
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VHDL Modeling Styles-Behavioral Modeling
Sensitivity lists are only used for speeding up simulations.
They are ignored by synthesis programs.
Why?
Hardware synthesis needs to know about all
signals, not just the active ones. Simulation,
on the other hand, only needs to know about
active signals.
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VHDL Modeling Styles-Behavioral Modeling
In a typical circuit application, a process will include in its
sensitivity list –all inputs that have asynchronous behavior.
These asynchronous inputs may include:
clock signal(s)
reset signals
inputs to blocks of combinational logic
Synchronous inputs should not be listed in the sensitivity list!
count or register load enable signals
external control input signals
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VHDL Modeling Styles-Behavioral Modeling
Example of a sensitivity list: 3-input AND gate
In purely combinational circuits, all
inputs are considered to be
asynchronous and should therefore
appear in the sensitivity list.
Note: Outputs do not show up in
sensitivity lists.
AND3_1 : process (A,B,C)
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VHDL Modeling Styles-Behavioral Modeling
The main part of the process block involves a set of sequential
statements, delimited by begin and end
The order of the sequential statements is important!
Statements inside a process block are evaluated in
sequence from first to last.
Process_label : process (sensitivity list)
-- declarations
Begin
-- sequential statements
end process;
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VHDL Modeling Styles-Behavioral Modeling
Types of sequential statements that can be used in process
blocks:
simple signal assignment statements
if/then/else
case
for loop
while loop
Note: the last 4 structures can be used only inside process blocks
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VHDL Modeling Styles-Behavioral Modeling
You cannot have
Component instantiations
Selected Signal assignments
Conditional Signal assignments
in process blocks!
NOTE!!!
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The elsif and else are optional.
The conditions specified in an if-then-else construct must
evaluate to a Boolean signal type.
If/Then/Else statements
if first_condition then
--statements
elsif second_condition then
--statements
else
--statements
end if;
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Example: 3_input OR gate
If/Then/Else statements
OR3_1 : process(A,B,C)
begin
F <= ‘0’; if A = ‘1’ then F <= ‘1’; elsif B = ‘1’ then F <= ‘1’; elsif C = ‘1’ then F <= ‘1’; end if;
end process;
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Notice that there are multiple assignments to the signal F.
This is allowed!
If/Then/Else statements
OR3_1 : process(A,B,C)
begin
F <= ‘0’; if A = ‘1’ then F <= ‘1’; elsif B = ‘1’ then F <= ‘1’; elsif C = ‘1’ then F <= ‘1’; end if;
end process;
multiple signal assignments
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Multiple signal assignments are permitted within a process
block (and only within a process block)
The last assignment to be evaluated in the sequential
evaluation of the statements in the process block is the one
that takes effect.
If/Then/Else statements
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OR3_1 : process(A,B,C)
begin
F <= ‘0’; if A = ‘1’ then F <= ‘1’; elsif B = ‘1’ then F <= ‘1’; elsif C = ‘1’ then F <= ‘1’; end if;
end process;
The first statement in the process block of the example is
there to prevent the occurrence of implied memory.
If/Then/Else statements
if not present, the circuit would
hold the value of F when A=B=C=0
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It is better to provide default values for combinational outputs
rather than using an ending else clause as it is easier to read
and less prone to error.
If/Then/Else statements
OR3_1 : process(A,B,C)
begin
if A = ‘1’ then F <= ‘1’; elsif B = ‘1’ then F <= ‘1’; elsif C = ‘1’ then F <= ‘1’; else F <= ‘0’; end if;
end process;
Not a good approach!
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You can have multiple process blocks, so -
Divide your circuit into a number of functional blocks (like
components) and use a separate process block to describe
each one.
blk1 blk2 blk3
A
B
C X
Y
Z Q
VHDL Modeling Styles-Behavioral Modeling
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VHDL Modeling Styles-Behavioral Modeling
…
blk1 : process(A,B,C) -- 2 input OR and AND gates
begin
X <= A or B;
Y <= C and B;
end process;
…
blk2 : process(X,Y,A) -- 3 input OR gate
begin
Z <= X or Y or A;
end process;
…
blk3 : process(Z,B) -- implement a latch
begin
if Z = ‘1’ then Q <= B; end if; end process;
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VHDL Modeling Styles-Behavioral Modeling
Architecture EX1 of DSD is
Signal A,B,X,Y,Z : std_logic;
Begin
process(X,Y,A)
begin
Z <= X or Y or A;
Y <= X and A;
end process;
process(Z,B)
begin
if Z = ‘1’ then Y <= B; end if; end process;
The following VHDL code is incorrect. WHY?
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VHDL Modeling Styles-Behavioral Modeling
The code on the previous slide is in error because there is
more than 1 assignment to the signal Y outside of a process
block!
process(X,Y,A)
begin
Z <= X or Y or A;
Y <= X and A;
end process;
…
blk3 : process(Z,B)
begin
if Z = ‘1’ then Y <= B; end if; end process;
multiple signal assignments
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VHDL Modeling Styles-Behavioral Modeling
You can have multiple assignments to a signal within a
process block, since only one assignment actually takes
effect.
This is not true outside of a process block!
In effect, the multiple assignments in a process count as a
single concurrent assignment statement.
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Case Statements
Case statements are a type of control statement that can be
used as alternatives to if-then-else constructs.
The two test expressions are allowed to be true at the same time.
Case statements must also include all possible conditions of the
control expression. (The others expression can be used to guarantee
that all conditions are covered.)
case control_expression is
when test_expression1 =>
-- statements
when test_expression2 =>
-- statements
when others
-- statements
end case;
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Case Statements
The case statement is much like the selected signal
assignment statement.
Their syntax is different however, so be careful to use the
appropriate one.
Inside process block - case statements
Outside process block - selected assignment
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Case Statements
entity MUX4_1 is
port (
i0,i1,i2,i3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
bitout : out std_logic);
end MUX4_1;
architecture Behavioral of MUX4_1 is
begin
process(i0,i1,i2,i3,sel)
begin
case sel is
when "00" => bitout <= i0;
when "01" => bitout <= i1;
when "10" => bitout <= i2;
when others => bitout <= i3;
end case;
end process;
end Behavioral;
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Adder
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Single-Bit Adders
Half-adder
Adds two binary (i.e. 1-bit) inputs A and B
Produces a sum and carryout
Problem: Cannot use it alone to build larger adders
Full-adder
Adds three binary (i.e. 1-bit) inputs A, B, and carryin
Like half-adder, produces a sum and carryout
Allows building M-bit adders (M > 1)
Simple technique
Connect Cout of one adder to Cin of the next
These are called ripple-carry adders
Shown in next section
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Half-Adder
Sum
s
0
1
1
0
Carry
c
0
0
0
1
0
0 +
0
1 +
1 0 0 0
1
0 +
1 0
1
1 +
0 1
x
y +
s c
Sum Carry
(a) The four possible cases
x y
0
0
1
1
0
1
0
1
(b) Truth table
x
y s
c
HAx
y
s
c
(c) Circuit (d) Graphical symbol
Sum
s
0
1
1
0
Carry
c
0
0
0
1
0
0 +
0
1 +
1 0 0 0
1
0 +
1 0
1
1 +
0 1
x
y +
s c
Sum Carry
(a) The four possible cases
x y
0
0
1
1
0
1
0
1
(b) Truth table
x
y s
c
HAx
y
s
c
(c) Circuit (d) Graphical symbol
Sum
s
0
1
1
0
Carry
c
0
0
0
1
0
0 +
0
1 +
1 0 0 0
1
0 +
1 0
1
1 +
0 1
x
y +
s c
Sum Carry
(a) The four possible cases
x y
0
0
1
1
0
1
0
1
(b) Truth table
x
y s
c
HAx
y
s
c
(c) Circuit (d) Graphical symbol
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VHDL Code for Half-Adder
library ieee ;
use ieee.std_logic_1164.all;
entity HA is
port(x, y : in std_logic;
s, c : out std_logic);
end HA;
architecture dataflow of HA is
begin
s <= x xor y;
c <= x and y;
end dataflow;
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Full-Adder
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VHDL Code for Full-Adder
library ieee ;
use ieee.std_logic_1164.all;
entity FA is
port(ci, xi, yi : in std_logic;
si, ci+1 : out std_logic);
end FA;
architecture LogicFunc of FA is
begin
Si <= xi xor yi xor ci;
ci+1 <= (xi and yi) or (ci and xi) or (ci and yi);
end LogicFunc;
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Decomposed Implementation of Full-Adder
HA
HA s1
c1
s
c2 c i
x i y i
c i 1 +
s i
c i
x i
y i
c i 1 +
s i
(a) Block diagram
(b) Detailed diagram
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VHDL Code for Full-Adder Using Half-Adder
library ieee ;
use ieee.std_logic_1164.all;
entity FA is
port(ci, xi, yi : in std_logic;
si, ciplus1 : out std_logic);
end FA;
architecture structure_FA of FA is
signal s1,c1,c2 : std_logic;
component HA
port(x, y : in std_logic;
s, c : out std_logic);
end component;
begin
HA1:HA port map(xi, yi, s1, c1);
HA2:HA port map(ci, s1, si, c2);
ciplus1 <= c2 or c1;
end structure_FA;
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1 0 1 0
1 0 0 1 +
1 Carry-in
0 1 0 0 1 Carry-out
1 1
Carry ripples from one column to the next
Multi-Bit Ripple-Carry Adder
Called a ripple-carry adder because carry ripples from
one full-adder to the next.
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Cin c1 c2 … c3 cn-1 Cout
s0
y0 x0 Carry-out
Carry ripples from one stage to the next
Carry-in
LSB position MSB position
y1 x1 y2 x2 yn-1 xn-1
s1 s2 sn-1
FAn-1 FA2 FA1 FA0
An n-bit RCA consists of n Full Adders
The carry-out from bit i is connected to the carry-in of bit (i+1)
Multi-Bit Ripple-Carry Adder
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Consists of 4 Full Adders
4-Bit Ripple-Carry Adder
Cin
c1 c2 c3
s0
y0 x0 y1 x1 y2 x2
s1 s2
FA2 FA1 FA0 FA3 Cout
s3
y3 x3
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VHDL Code for 4-Bit Ripple-Carry Adder
library ieee ;
use ieee.std_logic_1164.all;
entity adder4 is
port(Cin : in std_logic;
x3, x2, x1, x0 : in std_logic;
y3, y2, y1, y0 : in std_logic;
s3, s2, s1, s0 : out std_logic
Cout : out std_logic);
end adder4;
architecture structure_adder4 of adder4 is
signal c1,c2,c3 : std_logic;
component FA
port(Cin, x, y : in std_logic;
s, Cout : out std_logic);
end component;
begin
FA1:FA port map(Cin, x0, y0, s0, c1);
FA2:FA port map(c1 , x1, y1, s1, c2);
FA3:FA port map(c2 , x2, y2, s2, c3);
FA4:FA port map(c3 , x3, y3, s3, Cout);
end structure_adder4;
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Alternative Approach for Component Declaration
Another way to declare component in VHDL is to place it in
VHDL package.
A package allows VHDL constructs to be defined in one
source code file and then used in other source code files.
Package declaration has its own LIBRARY and USE
clauses.
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Alternative Approach for Component Declaration
library ieee;
use ieee.std_logic_1164.all;
package fulladd_package is
component FA
port(Cin, x, y : in std_logic;
s, Cout : out std_logic);
end component;
end fulladd_package;
Example: Declaration of Full-Adder package
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VHDL Code for 4-Bit Adder Using Full-Adder package
library ieee ;
use ieee.std_logic_1164.all;
use work.fulladd_package.all;
entity adder4 is
port(Cin : in std_logic;
x3, x2, x1, x0 : in std_logic;
y3, y2, y1, y0 : in std_logic;
s3, s2, s1, s0 : out std_logic
Cout : out std_logic);
end adder4;
architecture structure_adder4 of adder4 is
signal c1,c2,c3 : std_logic;
begin
FA1:FA port map(Cin, x0, y0, s0, c1);
FA2:FA port map(c1 , x1, y1, s1, c2);
FA3:FA port map(c2 , x2, y2, s2, c3);
FA4:FA port map(c3 , x3, y3, s3, Cout);
end structure_adder4;