Upload File

introductory programming guide for wideband pll+vcos...2 hittite microwave confidential september 5,...

  • Home
  • Documents
  • Introductory Programming Guide for Wideband PLL+VCOs...2 Hittite Microwave Confidential September 5, 2012 Table of Contents 1. Introduction to Wideband PLL+VCO Programming 2. Overview
24
September 5, 2012 Hittite Microwave Confidential 1 Introductory Programming Guide for Wideband PLL+VCOs A Practical Introduction to Using the HMC829LP6GE HMC830LP6GE, HMC832LP6GE, HMC833LP6GE, and HMC834LP6GE Wideband PLL+VCO Devices Greg Bachmanek Applications Engineer Hittite Microwave Canada

Upload: others

Post on 28-Jan-2021

30 views

Category:

Documents


0 download

Report

TRANSCRIPT

  • September 5, 2012Hittite Microwave Confidential1

    Introductory Programming Guide for Wideband PLL+VCOs

    A Practical Introduction to Using the HMC829LP6GE HMC830LP6GE, HMC832LP6GE, HMC833LP6GE, and

    HMC834LP6GE Wideband PLL+VCO Devices

    Greg BachmanekApplications Engineer

    Hittite Microwave Canada

  • September 5, 2012Hittite Microwave Confidential2

    Table of Contents

    1. Introduction to Wideband PLL+VCO Programming

    2. Overview of Fractional-N PLL+VCO Circuit3. Register 02h – Reference Divider4. Register 07h – Lock Detect5. Register 09h – Charge Pump6. Register 0Bh – Phase Detector Control7. Register 05h – VCO Subsystem Control

    a) VCO Subsystem Register 01hb) VCO Subsystem Register 02hc) VCO Subsystem Register 03hd) VCO Subsystem Register 04h and 05h

    8. Register 0Ah – VCO AutoCal Configuration9. Integer/Fractional Mode Frequency Tuning10. Register File Examples for HMC830LP6GE

    a) Fundamental (f0) Frequency Outputb) Output Divided Frequency Output

  • September 5, 2012Hittite Microwave Confidential3

    Introduction to Wideband PLL+VCO Programming

    The PLLs with Integrated VCO – RF Applications Product & Operating Guide should be consulted for more detailed device operation register programming information and procedures

    This document is intended as to be a brief practical introduction to understanding register programming

    This document highlights the handful of register commands you need to get a PLL+VCO device up and running for typical applications Other registers can typically left with default

    power-up settings and are used only for special-case device operation

  • September 5, 2012Hittite Microwave Confidential4

    Overview of Fractional-N PLL+VCO Circuit

    Register 02h Register 09h

    Register 03h

    Register 04h Register 05h

    Register 0Bh Register 0AhRegister 06h

    Register 07h

  • September 5, 2012Hittite Microwave Confidential5

    Register 02h – Reference Divider

    /RfPDfref

    ReferenceDivider

    θR

    The Reference Divider Register sets the division factor for converting the input reference signalfref into the phase detector frequency fPD

    Example:

    fref = 200MHz R = 4 Therefore fPD = fref / R = 50MHz

    Register File:

    REG 2 4Register Number

    Register Value in hexadecimal for R = /4 setting

  • September 5, 2012Hittite Microwave Confidential6

    Register 07h – Lock Detect

    The Lock Detect Register controls the ability of the PLL+VCO circuit to detect lock

    Note that a circuit may be phased-locked as measured by instrumentation but not indicating lock due to the configuration of this register

    Example:

    Register File:

    REG 7 14DRegister Number

    Register Value in hexadecimal – typical default case

    PhaseFrequency Detector

    fPD

    θR CP

    ChargePump

    θO

    PFD

  • September 5, 2012Hittite Microwave Confidential7

    Register 09h – Charge Pump

    The Charge Pump Register controls the conversion of PFD digital voltage pulses into an analog control signal

    CP Up Gain, DN Gain, and Offset can be set When θR > θ O then PFD + CP produces an UP

    CURRENT PULSE to speed up VCO When θ R < θ O then PFD + CP produces a DN

    CURRENT PULSE to slow down VCO

    Example:

    Integer Mode operates with Zero CP Phase Offset Fractional Mode requires CP Phase Offset or else phase noise

    and spurious performance is degraded (See Op Guide or Datasheet)

    Register File:

    REG 9 547FFFRegister Number

    Register Value for CP = 2.54mA, CP DN Offset = 420uA

    PhaseFrequency Detector

    fPD

    θR CP

    ChargePump

    θO

    PFD

  • September 5, 2012Hittite Microwave Confidential8

    Register 0Bh – Phase Detector Control

    The Phase Detector Control Register enables special control functions of the PFD

    Enables PD UP and/or DN output Enables Cycle-Slip Prevention Forces CP UP and/or DN

    Example:

    Cycle-Slip Prevention can be used to reduce lock acquisition time Forcing CP UP and/or DN can be useful for diagnostic purposes

    (See Op Guide or Datasheet)

    Register File:

    REG B 7C0E1Register Number

    Register Value for PD UP and DN enabled, CSP On,Force CP disabled

    PhaseFrequency Detector

    fPD

    θR CP

    ChargePump

    θO

    PFD

  • September 5, 2012Hittite Microwave Confidential9

    Register 05h – VCO Subsystem Control

    The VCO Subsystem controls various RF output and output divider (M) functions

    The VCO subsystem registers are addressed by writing values through register 05h

    The subsystem registers cannot be read

    Register File:REG 5 F88 Enable VCO subsystem, PLL Buffer, RF Buffer, RF Divider REG 5 E090 Set RF Divide Ratio, RF Buffer Gain, Divider Output GainREG 5 2A98 Set Single Ended Mode, Manual RF Output ModeREG 5 60A0 Set subsystem register 04h to factory suggested defaultREG 5 1628 Set subsystem register 05h to factory suggested defaultREG 5 0 Close out VCO subsystem register writes

    VCO

    /M

    OutputDivider

    fVCO

    fVCOM

    (applicable to HMC829/830/833/834LP6GE devices)

    Example:

    Five VCO subsystem registers are encoded as shown in example(See Op Guide or Datasheet for further details)

  • September 5, 2012Hittite Microwave Confidential10

    VCO Subsystem Register 01h = 0F88h

    0B88h = 0000 1111 1000 1000000 = Wideband Register ID

    0001 = VCO Subsystem Register 01h000010111 sets the following Register 01h bits:

    VCO_Reg01h[0] = Master Enable VCO Subsystem = 1 VCO_Reg01h[1] = Manual Mode PLL Buffer Enable = 1 VCO_Reg01h[2] = Manual Mode RF Buffer Enable = 1 VCO_Reg01h[3] = Manual Mode Divide by 1 Enable = 1 VCO_Reg01h[4] = Manual Mode RF Divider Enable = 1 VCO_Reg01h[8:5] = Spare Don’t Cares = 0000

  • September 5, 2012Hittite Microwave Confidential11

    VCO Subsystem Register 01h = 0F88h

  • September 5, 2012Hittite Microwave Confidential12

    VCO Subsystem Register 02h = E090h

    E090h = 1110 0000 1001 0000000 = Wideband Register ID

    0010 = VCO Subsystem Register 02h111000001 sets the following Register 02h bits:

    VCO_Reg02h[5:0] = RF Divide Ratio = 000001 = 1d = Divide by 1 = m VCO_Reg02h[7:6] = RF Output Buffer Gain Control = 11 = Max Gain VCO_Reg02h[8] = Divider Output Stage Gain Control = 1

  • September 5, 2012Hittite Microwave Confidential13

    VCO Subsystem Register 02h = E090h

  • September 5, 2012Hittite Microwave Confidential14

    VCO Subsystem Register 03h = 2A98h

    2A98h = 0010 1010 1001 1000000 = Wideband Register ID

    0011 = VCO Subsystem Register 03h001010101 sets the following Register 03h bits:

    VCO_Reg03h[0] = RF Buffer SE Enable = 1 = Single Ended Output from RF_N port VCO_Reg03h[1] = Reserved = 0 VCO_Reg03h[2] = Manual RFO Mode = 1 = Manual RFO Mode setting VCO_Reg03h[4:3] = RF Buffer Bias = 10 VCO_Reg01h[8:5] = Spare Don’t Cares = 0010

  • September 5, 2012Hittite Microwave Confidential15

    VCO Subsystem Register 03h = 2A98h

  • September 5, 2012Hittite Microwave Confidential16

    VCO Subsystem Registers 04h and 05h

    As stated in our RF PLL Operating Guide registers 04h and 05h must be set to values given in a table as shown below:

  • September 5, 2012Hittite Microwave Confidential17

    Register 0Ah – VCO AutoCal Configuration

    The VCO auto-calibration parameters can be adjusted with this register

    VCO auto-calibration can also be turned-off and then the VCO can be manually calibrated with values stored in a look-up table for fast frequency tuning (subject of another AppNote)

    VCO

    /M

    OutputDivider

    fVCO

    fVCOM

    Example:

    The AutoCal is enabled with bit 11 The VSPI Trigger can be disabled to stop Register 05h writes

    (See Op Guide or Datasheet for further details)

    Register File:

    REG A 2046Register Number

    Register Value for AutoCal enabled, VSPI trigger enabled

  • September 5, 2012

    Hittite Microwave Confidential18

    Integer/Fractional Mode Frequency Tuning

    There are four main modes of operation:(1) Integer Mode(2) Fractional A Mode(3) Fractional B Mode(4) Exact Frequency Mode (subject of another AppNote)

    Integer Mode:

    RF Divider/N

    ΔΣDelta Sigma Modulator

    θO

    fPD N x fPD

    Fractional Mode A: Fractional Mode B:

    fVCO

    September 5, 2012

  • Hittite Microwave Confidential19

    Integer/Fractional Mode Frequency Tuning

    Frequency Tuning Formulae:

    RF Divider/N

    ΔΣDelta Sigma Modulator

    θO

    fPD N x fPD

    fVCO

    September 5, 2012

  • Hittite Microwave Confidential20

    Integer/Fractional Mode Frequency Tuning

    September 5, 2012

  • REVISION HMC830 Register FileREG 0 20 // RESET command.REG 2 1 // Reference Divider Register-Default value = /1 REG 5 60A0 // Set VCO subsystem register 04h to factory suggested defaultREG 5 1628 // Set VCO subsystem register 05h to factory suggested defaultREG 5 F88 // Set VCO subsystem register 01h to enable VCO subsystem, PLL Buffer, RF Buffer, RF Divider REG 5 E090 // Set VCO subsystem register 02h to set RF Divide Ratio = /1, RF Buffer Gain = Max, Divider Output GainREG 5 2A98 // Set VCO subsystem register 03h to set Single Ended Mode, Manual RF Output ModeREG 5 0 // Close out VCO subsystem register writes//REG 6 200B4E // Delta-Sigma Modulator Configuration Register. Program this value for Fractional Mode A = optimum in-band phase noiseREG 7 14D // 14Dh is the default value for LD programming. For different configurations this may need to change.REG 9 547FFF // CP Register-Program as needed. 547FFFh = 2.54mA CP current with 420uA down CP Leakage current.REG A 2046 // VCO AUTO-CAL and Configuration RegisterREG B 7C0E1 // PFD Control Register - Here set to PD UP and DN enabled, CSP On, Force CP disabled//REG 3 2C // Integer VCO Divider Register REG 4 18937 // Fractional VCO Divider Register. When this register is written, a VCO AUTO-CAL is initiated.//// These last 3 lines are directives to the evaluation software indicating reference source frequency and divider configuration.// These are not required in actual application software.XTAL 50VCO_TO_SYNTH_DIV 1VCO_TO_OUT_DIV 1

    Hittite Microwave Confidential21

    Register File Example for HMC830LP6GE Minimum Register Writes for 2200.30MHz Output

    M = /1

    September 5, 2012

  • REVISION HMC830 Register FileREG 0 20 // RESET command.REG 2 1 // Reference Divider Register-Default value = /1REG 5 60A0 // Set VCO subsystem register 04h to factory suggested defaultREG 5 1628 // Set VCO subsystem register 05h to factory suggested defaultREG 5 F88 // Set VCO subsystem register 01h to enable VCO subsystem, PLL Buffer, RF Buffer, RF Divider REG 5 E110 // Set VCO subsystem register 02h to set RF Divide Ratio = /2, RF Buffer Gain = Max, Divider Output GainREG 5 2A98 // Set VCO subsystem register 03h to set Single Ended Mode, Manual RF Output ModeREG 5 0 // Close out VCO subsystem register writes//REG 6 200B4E // Delta-Sigma Modulator Configuration Register. Program this value for Fractional Mode A = optimum in-band phase noiseREG 7 14D // 14Dh is the default value for LD programming. For different configurations this may need to change.REG 9 547FFF // CP Register-Program as needed. 547FFFh = 2.54mA CP current with 420uA down CP Leakage current.REG A 2046 // VCO AUTO-CAL and Configuration RegisterREG B 7C0E1 // PFD Control Register - Here set to PD UP and DN enabled, CSP On, Force CP disabled//REG 3 2C // Integer VCO Divider Register REG 4 18937 // Fractional VCO Divider Register. When this register is written, a VCO AUTO-CAL is initiated.//// These last 3 lines are directives to the evaluation software indicating reference source frequency and divider configuration.// These are not required in actual application software.XTAL 50VCO_TO_SYNTH_DIV 1VCO_TO_OUT_DIV 1

    Hittite Microwave Confidential22

    Register File Example for HMC830LP6GE Minimum Register Writes for 1100.15MHz Output

    M = /2

    September 5, 2012

  • Frequency Generation ProductsOttawa Design Centre (ODC)

    Applications Engineering Contacts:

    September 5, 2012Hittite Microwave Confidential23

    Greg [email protected]. 1 613 216-2476 ext. 255

    Hittite Microwave Canada380 Hunt Club RoadSuite 100Ottawa, OntarioCanadaK1V 1C1

    Don [email protected]. 1 613 216-2476 ext. 234

    Hittite Microwave Canada380 Hunt Club RoadSuite 100Ottawa, OntarioCanadaK1V 1C1

  • September 5, 201224 Hittite Confidential

    Thank You


High Linearity Wideband RF-to-Digital Transceiverww1.prweb.com/prfiles/2014/09/10/12160069/RF-7102.pdf · PLL Synthesizer User Region Registers ... High Linearity Wideband RF-to-Digital

ICML-Tutorial, Banff, Canada, 2004 Overview 1.Introduction to PLL 2.Foundations of PLL –Logic Programming, Bayesian Networks, Hidden Markov Models, Stochastic

Design of a Wideband Fractional-N Frequency Synthesizer ...noise, whereas a ΣΔ synthesizer relies on the PLL dynamics to attenuate quantization noise. Active noise cancellation is

LECTURE 090 – PLL DESIGN EQUATIONS AND PLL MEASUREMENTS

PLL Presentation

Wideband RF/microwave PLL fractional/integer …This is information on a product in full production. August 2019 DS11314 Rev 6 1/63 STuW81300 Wideband RF/microwave PLL fractional/integer

ADF4106 PLL

PLL FM Exciter - Virtual Innovative Technology Co., Ltd. FM Exciter Model: PLL-11031K Model: PLL -11032K Model: PLL -11033K Model: PLL -11034K Model: PLL -11035K Model: PLL -11036K

Wideband Quadrature Modulator with Integrated Fractional-N … · 2019-06-05 · Wideband Quadrature Modulator with Integrated Fractional-N PLL and VCOs Data Sheet ADRF6720-27 Rev

PLL report

1.0 - 2.0 GHz Wideband PLL CMOS Frequency …iv Abstract 1.0 - 2.0 GHz Wideband PLL CMOS Frequency Synthesizer by Chao W. Huang CMOS mixed-signaldesign has become very popular in today’s

BoT-nLE521 - fccid.io · Bluetooth Smart (Bluetooth low energy) ... Radio ra RF Input Level 10 ... PLL,PROG,RES PLL programming resolution 2 kHz f PLL,CH,SP

PLL Design

1606 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 7 ... Low Phase Noise, Wideband... · : A LOW PHASE NOISE, WIDEBAND AND COMPACT CMOS PLL FOR USE IN A HETERODYNE 802.15.3c

DATA SHEET SKY73134-11: Wideband PLL … SHEET • SKY73134-11 FREQUENCY SYNTHESIZER Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected]

A 9.2--12.7GHz Wideband Fractional-N Subsampling PLL in ... · A 9.2–12.7GHz Wideband Fractional-N Subsampling PLL in 28nm CMOS with 280fs RMS jitter Kuba Raczkowski , Nereo Markulic;y,

Wideband RF/microwave PLL fractional/integer frequency ... · 9 VIN_LDO_VCO Supply voltage of VCO circuitry regulator - 10 VR Connection of reference voltage filtering capacitor-11

PLL performance.pdf

AN 661: Implementing Fractional PLL Reconfiguration with ... · Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores 2019.10.14 AN-661 Subscribe

Oszcillatorok Pll

LMX2594 EVM Instructions 15-GHz Wideband Low … · LMX2594 EVM Instructions – 15-GHz Wideband Low Noise PLL With Integrated VCO User's Guide Literature Number: SNAU210 March 2017

DATA SHEET SKY73134-11: Wideband PLL Frequency Synthesizer · 2012-01-26 · external VCO or external Phase Locked Loop (PLL), or the device can use the divider chain only. The SKY73134-11

Evaluating the ADF4356 Microwave Wideband …€¦ · product page for the EV-ADF4356SD1Z control software. For the software installation procedure, see the PLL Software Installation

Sintetizdor PLL

Open Source SPM Controller & PLL Model Mk3-PLL · PDF fileOpen Source SPM Controller & PLL Model Mk3-PLL ... This MK3-PLL model is fully compatible with the SPM control software

Donmez a. - Wideband PLL System as a Clock Multiplier (2009)

Wideband RF PLL fractional/integer frequency synthesizer ... · January 2016 DocID025943 Rev 7 1/58 STW81200 Wideband RF PLL fractional/integer frequency synthesizer with integrated

Hittite’s New Wideband PLL+VCO - The Ultimate Solution for Low … · 2017-02-15 · is ideal for wideband multi-carrier, multi-standard cellular base stations as it can be used

MAX2871 23.5MH to 6MH ractional InteerN SnthesierVCO · 2017-04-28 · The MAX2871 is an ultra-wideband phase-locked loop (PLL) with integrated voltage control oscillators (VCOs)

Wideband RF/microwave PLL fractional/integer frequency ... · Wideband RF/microwave PLL fractional/integer frequency synthesizer with ... 7.7 Charge pump ... VCO feedthrough at RF2

APLIKASI PLL

Super PLL Appnotemirror.unpad.ac.id/orari/library/library-sw-hw/community-broadcasting/fm-pll...Programming Example: FM Broadcast Receiver Local Oscillator ... Voltage Controlled Oscillator

Wideband RF PLL fractional/integer frequency synthesizer ... · PDF fileJanuary 2016 DocID025943 Rev 7 1/58 STW81200 Wideband RF PLL fractional/integer frequency synthesizer with integrated

Wideband RF/microwave PLL fractional/integer … · This is information on a product in full production. December 2016 DocID028443 Rev 5 1/60 STuW81300 Wideband RF/microwave PLL fractional/integer

A Miniaturised Wideband Frequency Synthesisereprints.qut.edu.au/31851/1/David_Enchelmaier_Thesis.pdfFigure 4.2: Cross-sectional view of the VCO/PLL module, showing layering of the