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Common Power Format: Everything you wanted to know and more!

April 2007

April 20, 20072

Power is causing process migration discontinuity

180 130 90 65Process Technology

(nm)

Leakage Power

ActivePower

199019701960 2000

Vacuum2

468

101214

1980 2010M

odul

e H

eat F

lux(

wat

ts/c

m2)

Bipolar

Year of AnnouncementSource: Bernard Meyerson, IBM

CMOS

?

We are here today

A design-based solution is essential

April 20, 20073

State-of-art Low Power Flow in 2005

VerificationFormal

Analysis

Acceleration & Emulation

Simulation

Verif

icat

ion

Cov

erag

e

Test

benc

h A

utom

atio

n

Design Creation

Synthesis

ConstraintGeneration

Design for Test

SVP

Equivalence Checking

Constraint Validation

SpecificationFunction, timing, power

RTL Coding

IterateIterate

Physical ImplementationChip Integration

Prototyping

Physical Synthesis

Routing

DFT A

nalysis

Sign-off

ATPG

Constraint Validation

Equivalencechecking

LVS/DR

C/Ext

GDSII

Constraints Netlist

How do you verify power functionality

without changing RTL??

MSVSRPGPSO

DVFS

Command file•Domains•Level shifters•Isolation•SRPG

Command file•Domains•Level shifters•Isolation•SRPG

Command file•Domains•Level shifters•Isolation•SRPG

Command file•Domains

Command file•Domains•Modes for ATPG

Command file•Domains•Level shifters•Isolation•SRPG

Command file•Domains•Level shifters•Isolation•SRPG

Which one of these is “golden”?

Does the power shutoff really going to

work?

April 20, 20074

What was the problem?

Logic is “Connected”

Can be Automated

Libraries

IP

LogicInformation

(Verilog)

Synthesis

TestSiliconVirtual

Prototype

SimulationParser Parser

P+RParser

Pars

er

Parser

VerificationParser

Power is Not “Connected”

Libraries

IP

Verification

Synthesis

Test

P+R

ScriptsFile translationErrors

Very Difficult to Automate

PowerInformation(no consistency)

Simulation

SiliconVirtual

Prototype

April 20, 20075

What Did Designers Need in 2005?

• A central deposit of all design and implementation related information for advanced low power techniques

• A complete low power verification flow from RTL to GDSII

• A complete implementation flow to implement exactly what has been verified

• A low power flow solution not point tool support• A complete IP methodology for advanced low power

designs• And many more …

April 20, 20076

Taking the Leadership Role

Encounter Low Power Implementation Flow

PowerForwardInitiative

Synthesis EquivalenceChecking

Design for TestSVP

Formal Analysis

Simulation

AccelerationEmulation

Verification Process Automation

Constraints management

April 20, 20077

Rallying Industry Support

CPF

Design

Verific

ation

Implementation

Libs

Semi

System

MfgEquip

EDA

IP

A new method of capturing design and constraint

information

Enables automation and what-if exploration

Facilitates holistic methodology across design, verification, and implementation

April 20, 20078

?

New Start-of-art Low Power Flow: CPF Enabled

Design Creationb

Synthesis

ConstraintGeneration

Design for Test

SVP

Equivalence Checking

Constraint Validation

SpecificationFunction, timing, power

RTL Coding

RTL + CPFCoding

Iterate

Quick architectural exploration

Re-use pre-verified IPInstantiate single

RTL with different power profiles

Hand off to drive physical implementation

Physical ImplementationChip Integration

Prototyping

Physical Synthesis

Routing

DFT A

nalysis

Sign-off

ATPG

Constraint Validation

Equivalencechecking

LVS/DR

C/Ext

GDSII

Constraints CPF Netlist

Golden specification eliminates

assumptions and miscommunications

Automatic partitioning of power domains

Automatic scheduling of test modes

Single power specification used from specification to GDSII

Verif

icat

ion

Cov

erag

e

Test

benc

h A

utom

atio

n

Verification

Structural &Funct. Checks

FormalAnalysis

Simulation

Acceleration& Emulation

Functionally verify advanced power implementation

techniques Iterate

April 20, 20079

Power is Not “Connected”

Very Difficult to AutomateIs Automated

Power is Connected

PowerInformation

(CPF)

Power Forward InitiativeCommon Power Format (CPF)

Logic is “Connected”

Libraries

IP

Synthesis

Test

P+R

Is Automated

Libraries

IP

VerificationParser

Parser Parser

Parser

Pars

er

Parser

Libraries

IP

LogicInformation

(Verilog)

Synthesis

TestSiliconVirtual

Prototype

SimulationParser Parser

P+RParser

Pars

er

Parser

VerificationParser

Simulation

SiliconVirtual

Prototype

April 20, 200710

100100ManMan

YearsYears

Common Power Format Progress

2005

CPFCPFV 0V 0

Q22006

CPFCPFV 0.5V 0.5

~ 100 Inputs~ 100 Inputs

Q32006

CPFCPFV 0.8V 0.8

> 400 Inputs> 400 Inputs

Q42006

CPFCPFV 1.0V 1.0

Membership: 10 Membership: 22

April 20, 200711

Common Power FileASCII file to capture

• Design intent and constraints– Power domain

• Logical: instances as domain members• Physical: power/ground nets and connectivity• Analysis view: timing library sets for power domains

– Power Logic• Level Shifter Logic• Isolation Logic• State-Retention logic• Switch Logic & Control Signals

– Power mode• Mode definitions• Mode transition expressions

• Technology information– Level Shifter Cells, Isolation Cells, State-Retention Cells, Switch Cells,

Always On Cells

April 20, 200712

Command Categories Based on Applicationsset_designend_designcreate_power_domaincreate_nominal_conditioncreate_power_modecreate_state_retention_rulecreate_isolation_ruledefine_library_setdefine_state_retention_cellcreate_power_switch_rulecreate_level_shifter_ruleupdate_nominal_conditionupdate_power_modecreate_analysis_viewcreate_global_connectioncreate_ground_netscreate_power_netscreate_operating_cornerupdate_power_domain

Specify power intentsGood for: verification and simulation

design explorationearly power estimation

More implementation detailsGood for: synthesis

formal verificationDFT, ATPG, gate level power estimation

Complete physical implementation detailsGood for: silicon virtual prototyping

power planningphysical synthesisformal and structural verificationsign-off power analysis

April 20, 200713

CPF Commands: Design Intents

• create_power_domain• create_state_retention_rule• create_isolation_rule• create_level_shifter_rule• create_power_mode• create_mode_transition• create_power_switch_rule

• identify_always_on_driver• identify_power_logic

April 20, 200714

CPF Commands: Design Constraints

• create_nominal_condition• create_operating_corner• create_analysis_view• create_power_mode

April 20, 200715

update_nominal_condition-name <nominal_condition>-library_set <name>

update_power_mode-name <mode_name>[ -activity_file file -activity_file_weight weight ][ -sdc_files sdc_file_list ]

create_analysis_view-name <string>-mode <mode_name>-domain_corners

{ list_of_operating_corners_by_domain }

create_power_mode-name <string>-domain_conditions

{ list_of_nominal_condition_by_domains }

create_operating_corner-name <string>-voltage <float>[-process <float>][-temperature <float>]-library_set <name>

define_library_set-name <library_set>-timing <library_list>

create_nominal_condition-name <string>-voltage <float>

create_power_domain-name <string>{-default [-instances instance_list] [-boundary_ports pin_list]| -instances instance_list[-boundary_ports pin_lust][-boundary_ports pin_list }[-shoutoff_condition expression]

DVFS

Corner Info.MMMC

April 20, 200716

Power Mode

• create_nominal_condition –name high -voltage 1.2 • create_nominal_condition –name low -voltage 1.0 • create_power_mode -name M1 \

-domain_conditions { PD1@high PD2@high PD3@low }• create_power_mode -name M2 \

-domain_conditions { PD1@high PD2@low }• create_power_mode -name M3 \

-domain_conditions { PD1@low }

PD1 PD2 PD3

M1 1.2v 1.2v 1.0vM2 1.2v 1.0v 0.0vM3 1.0v 0.0v 0.0v

April 20, 200717

CPF Commands: General Commands

• set_cpf_version• set_array_naming_style• set_register_naming_style• set_hierarchy_separator• set_power_unit• set_time_unit• set_power_target• set_switching_activity

April 20, 200718

Not just the format but real solutions to address customer challenges

Customer Engineering Teams

Incisive Design Team / Enterprise Manager X X X

Encounter True-Time X

Encounter Timing Solution X

Cadence Products Now Supporting Common Power Format

Logic Design Teams

Advanced Verification

Teams

Physical Implementation

TeamsIncisive Design Team / Enterprise Simulator X X X

Encounter RTL Compiler X X

Encounter Conformal Low Power X X X

Encounter Test Architect X X

First Encounter X X

SoC Encounter X

Encounter VoltageStorm X

April 20, 200719

Key Benefits of CPF

• Supports design, verification, and implementation– Single view for all power related information (design intent,

constraint, and technology library)• Enables architectural exploration for power

– Separate Core functionalities from power constraints/intent– Golden RTL with multiple CPF files to tradeoff different

implementations• Eases IP reuse and portability

– Simple migration of non-power aware RTL design to power aware

– Supports multiple instantiation of a module with varying power architecture

• HDL language neutral– Single format can be used in mixed languages designs

April 20, 200720

Contributions of CPF to the Industry

• CPF lead the EDA industry to address low power challenges in a holistic approach

• Eliminates the debates on whether a new power format should be developed or extension of current standards is enough– This was a big debate in DAC 2006 but not any more

• Eliminates the need by customers to work on their own power formats– Of almost every customers PFI engaged early on had its own

power format.

• Dec 4, 2006 – Cadence contributed CPF v1.0 to

Si2• January 12, 2007

– LPC members unanimously voted and approved CPF v1.0 as Si2 Specification for low power standard

• January 17, 2007– Cadence contributed CPF v1.0

parser source code to Si2• March 5, 2007

– CPF 1.0 available to everyone at no cost as a Si2 standard

Si2 CPF Standardization Progress

April 20, 200722

Call to Action

• Come and see CPF based flows working on real customer designs!

• Cadence booth # R52