inverter design - animesh

8/3/2019 Inverter Design - Animesh

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Basics of Inverter:Analysis and Design

Animesh Datta

Research ConsultantAdvanced VLSI Design Lab

Email: [email protected] page:

http://www.vlsi.iitkgp.ernet.in/~animesh
mailto:[email protected]://www.vlsi.iitkgp.ernet.in/~animeshhttp://www.vlsi.iitkgp.ernet.in/~animeshhttp://www.vlsi.iitkgp.ernet.in/~animeshmailto:[email protected]


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5/28/2002CMOS Inverter: Analysis and Design2

Introduction

What is an inverter Background knowledge

Classification of inverters

Inverting amplifier circuits

Inverter as a basic digital logic block

DC analysis of basic CMOS inverter

Dynamic analysis of CMOS inverter

Digital CMOS inverter design Power consumption

Introduction to layout of inverter

Conclusion


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Basic MOS design relations

For an nMOS transistor with channel width W

and channel length L (bulk is connected tosubstrate)ID

D

G

S

VDS

VGS- -

+

+

Small signal model of MOS devices

Condition for the device to be in saturation

VDS VGSVT (1)

ID =k'W/2L(VGSVT) = 2 (VGSVT) (2)

Trans-conductance gm=ID ..(3)

gm = 10gmbs = 100gds(approximate)..(4)

VDS|sat = 2ID/..(5)


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Inverter Classifications

Amplifier characterization

Large signal voltagetransfer characteristics.

Small signal frequencyindependent performance

gain

Input and output resistance

The CMOS inverter:

DC operation

Dynamic operation

Propagation delay

Power consumption Layout

Digital:

Inverter ( NOT gate)

Symbol

Y Y'

(Amplifies and inverts the input signal)

Analog :

Inverting Amplifier


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Inverting amplifier

Importance of W/L in Analog CMOS circuit design

Vout

Vin

gnd

nMOS

Active Load

(pMOS) inverter

pMOS

M1

M2

Vdd

Active pMOS load inverter

Large-signal voltage swing limits

Vout(Max) = Vdd - |VTp|, VTp=Vthreshold of the pMOSignoring presence of any Isubthreshold in the MOS device

What about Vout(Min) = ?

Voltage Transfer Characteristics (VTC) of the circuit:

Small signal analysisFrom the small signal model derive the expressions

Gain= Vout/Vin= - gm1/gm2 = -K'NW1.L2/KP.W2.L1

Rout= Vout/Iout|Vin=0 1/gm2 also depends upon W2/L2


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Inverting Amplifier (contd.)

Small signal analysis

VinVout

Vdd

gnd

pMOS

Push-pull

Inverter

nMOS

CL

M1

M2

Push-pull inverter

Large signal analysis

-VTC and Inversion voltage (to beexplored in detail).

- Compare with the earlier VTC.

Gain=Vout/Vin= - (gm1+ gm2)/(gds1 +gds2)Rout = Vout/Iout|Vin=0 1/(gds1 +gds2)


7/195/28/2002CMOS Inverter: Analysis and Design7

Other forms of Inverter Circuit

Vin

gnd

Vout

Vdd

RL

nMOS

Resistive load

Vin

gnd

Vout

nMOS

nMOS

Active load

(nMOS)

Vin

Vout

Vdd

gnd

nMOS

pMOS

Current source

load Inverter

VGG2


8/195/28/2002CMOS Inverter: Analysis and Design

8

CMOS Inverter as a basic digital logicblock (NOT Gate)

Provides large output swing at theexpenses of very low power.

Vin Vout

Vdd

gnd

Pull-up

Mn

Mp

Pull-down

IDnI

Dp

Why CMOS?

A nMOS-pMOS group with a common gate is

called a complementary pair. This is the basis ofthe CMOS logic circuits.

DC operation (note the bulk connections)

Vin= 0 v => Vout= VDD

Vin= VDD => Vout= 0 v

Positive logic Convention:

Small voltages ( close to 0) => Logic 0

Large voltages (close to VDD) =>Logic 1



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CMOS Inverter Analysis

Regions of operation (balanced inverter):

Vin n-MOS p-MOS Vout

gnd

Mn

Mp

IDnI

Dp

VinVout

Vdd

0 cut-off linear Vdd

VTNVdd/2 linear saturation ~0

Vdd linear cut-off 0



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CMOS Inverter analysis (contd.)

Noise margin: circuits immunity

against false switching in the presenceof external and parasitic affects

VTC:presents a set of critical voltages

Vout

Vin

VOH=VDD

Unity gain line

Vout =Vin

dVout/dVin=-1

VI

dVout/dVin=-1

VOL=0

VIL VIHVI

Critical VTC voltages

VOH, VOL: largest and smallest possible Vout

Output logic swing VL= VOH - VOL= VDD

VIH and VIL can be defined as

VIN > VIH 1

VIN < VIL0

VNMH=VOH-VIH

VNML=VIL-VOL



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CMOS Inverter analysis (contd.)Inverter Threshold (midpoint, inversion) Voltage(VI) :

point of intersection of VTC and unity gain line.

Very important design parameter thatdetermine the entire VTC of the circuit.

Derive the expression for VI:(VDD - |VTp| + n pVTn

VI =-----------------------------------

1 + n

p

If = n p is the device ratio,

then for 1 < 1 < 3

Vout

Variation of Inverter threshold

voltage (VI) with

Vin

VI1

VI2

VI33

1

2=1



12

Dynamic analysis: switching characteristics

VDD

Mpoff

Vin= VDD

Vout

gnd

Charging and

Discharging Circuit

Cout

Mn

0

Propagation delay(tP)Main origin: load capacitance(CL)

tC V

k V V

C

k V

tC V

k V V

C

k V

t t tC

V k k

pLHL dd

p dd TP

L

p dd

pHLL dd

n dd TN

L

n dd

p pLH pLH

L

dd n p

2

2

1

2 2

1 1

To reduce the delay:

Reduce CL

Increase kn and kp. That is, increase W/L


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switching characteristics(contd.)

0 2 4 6 8 10 12-0.5

0

0.5

1

1.5

2

2.5

3

Time (ns)

Inverter transient response

0 2 4 6 8 10 12

-0.6

-0.4

-0.20

0.2

0.4

0.6

Time (ns)

Vout,

Vin

(V) Vout

Vin

ID(nmos)

ID(pmos)

ID

(mA)

CL=250fF

CL=250fF


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Inverter design1: DC Design

To design the value of VI for a particular VTC

Compute the design parameter from the expression of VI.

Calculate the value of VI for inverter having same aspectratio (W/L)n = (W/L)p

Design Problem:Design a inverter with symmetrical VTC, VI =0.5VDD

Assume suitable values for VTn, VTp, , kn, kp .


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Inverter design2: Transient Design The transient response should be symmetrical with tLH=tHL.

but once (W/L)n and (W/L)p are decided the time constants arealso determined.

DC design sets the general shape of the switching waveforms

Cout= Cint + CL,

Cint : internal MOSFET capacitance and is dependent on

device aspect ratio.CL: external load capacitance due to large no of fan-out.

Large aspect ratio (W/L) is to be chosen for design to achievefast charging and discharging of Cout.

High performance designTo achieve smaller time delays in digital signal path


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Power consumptions

Dynamic power consumption : Only occurs while charging and discharging of capacitors

Short circuit path between power rails during switching

Consume largest part of the supply in the high speed digital

circuits

Leakage(static Power consumption): Due to leakage currents through diodes and transistors in the cut-off state

Uses a small part (10 %) of the total power.

Power delay product (PDP)Avg. energy per switch= Pav. tP in Joules

Pav=1/TVDD I()d over a time period.


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Low Power Inverter design

VDD

Vin

Vout

Dynamic power

E = Energy / transition =

P = Power = 2

1

2

2

2

C V

f E f C V

L dd

L dd

To reduce dynamic power dissipation

Reduce: CL (usually not controllable)

Reduce: f (demand for faster ckt doesnt permit this!!)Reduce: Vdd The most effective action but delay

Decide on the trade-off between delay and power loss


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Inverter Layout

n-well

n-well contact (n+)

Poly-silicon

p+ diffusions

substrate contact (p+)

n+ diffusions

Poly-silicon contacts

diffusion contacts


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Conclusion and looking ahead

Tips for analog designer:

Use paper-pencil to design from the dc conditions and then

check its performance simulating in SPICE.

Inverter is a simple but versatile circuit.

Extensively used as buffer in the output stage to

reduce the loading effect of the previous stage(Low RO).

Used as a basic block in many analog circuits like

oscillators, Amplifiers.

Never use CAD tools for circuit design, but only for

verifications

inverter design - animesh

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