investigation for readout electronics of wac in lhaaso shubin liu university of science &...
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Investigation for Readout Electronics of WAC in LHAASO
Shubin LiuUniversity of Science & Technology of China
April 22nd, 2009
2009/04/22 USTC, Shubin Liu 2
LHAASO Project for γs and CRs
WCD: 4x2.25x104m2
μ : 100x400m2
e : 2400x1m2
CT: 28
BD: 1000x1m2
AS+μ:
ARGO: 104m2
Large High Altitude Air Shower Observatory
2009/04/22 USTC, Shubin Liu 3
Water Cherenkov Detector
• Sensitive to cosmic gamma rays around TeV– Maintaining the all-sky, high-duty-factor capabilities of
an EAS array
• 4 ponds each with the area of 2.25x104m2
– Each will be filled with purified water– 900 PMTs will be deployed under the water of Each p
ond• For a total of 3600 PMTs and corresponding readout electron
ics• Hamamatus R5912 employed in Daya Bay experiment is the
candidate type
2009/04/22 USTC, Shubin Liu 4
The Requirement of Readout Electronics
• Digitalizing the accurate time of arrival of the selected showers– Both the timing and pulse height of each PMT is impo
rtant• 1ns time resolution for leading edge time measurement• A wide dynamic range of 1~4000 PEs for pulse height measu
rement– A trigger decision must be made to select showers– Clock and calibration systems are essential
• Distributing the large number of signals over the long distance (~100m) is an issue– Pre-Amplifier or Front-end process circuit is needed
2009/04/22 USTC, Shubin Liu 5
Sketch of Electronics
Digital Board(VME)
M #
Digital Board(VME)
1#
Trigger Board(VME)
Clock, Trigger
Fast hit info
Fast hit info
1:P Fan-out
Clock, Trigger
Clock, Trigger
GPS Receiver
PMT1
PMT n
PMT 900
PMT读出电子学系统结构
FEB1#
FEBN #
~5m long cable ~100m long cable
2009/04/22 USTC, Shubin Liu 6
Two Candidate Scheme
• Traditional scheme– Similarly with Daya Bay Experiment’s electronics, with
the additional Pre-amplifier– The mature scheme– Much power consumption and expense because of th
e ADCs• TOT scheme
– Adopted by Milagrito/Milagro and the planned Hawk Experiment
– The TDC marks each time that a pulse crosses a voltage threshold with a edge
– Lower power consumption and expense for the absence of ADCs
2009/04/22 USTC, Shubin Liu 7
Traditional Readout Scheme
• Patch panels (FEBs) above the water accommodating the Pre-Amplifiers, which are fed by the PMT signals via the 5m long cables, and drive the ~100m long cables to the digital boards
• Two amplifiers and corresponding shaping and ADC circuits for the wide dynamic range (1~4000PE)
• Waveform digitalization by high speed (40MHz) ADCs to find the peak of the waveform after shaping
• Fast discriminator provides the arriving time of the pulse, recorded by TDC, and fed to the trigger logic
ADC
PMT
Pre- Amp
gH
gL ADC
Da
ta Bu
ffer
DAQ
Vth
Trigg.
Interfa
ce
CableShaping
Shaping
TDCL1 L1
Clock
2009/04/22 USTC, Shubin Liu 8
Charge Measurement in Daya Bay Experiment
PMT1
CR-(RC)^4Shaping
2 Ranges
ADC12 bit/40MHigh speed
Ampifier
Peak Value ~ PMT output charge
FPGA
I ntegrati ng
Cable of only ~50m
The wide dynamic range (1~4000PE), and high charge measurement resolution (0.1PE), are achieve in this scheme
• The PMT signal with a pulse width of about 10-20ns is sent to a high speed amplifier
• The amplified signal is then fed to the CR-(RC)4 shaping circuits with different gain parameters
– The simulation shows error of lower than 4% can be achieved with the ADC sampling speed of 40MHz
• Two 12-bit ADCs are employed to sampling these two signals at a speed of 40MHz
– Results in a number of ~7200 ADCs to the number of ~3600 PMT channels– ~700mW/chip and ~¥ 300/chip
shaping time constant: 25ns
Waveform width: 325ns
The peak width of 1% resolution is 109.29-95.97=13.32nsThe peak width of 4% resolution is 116.43-89.74=26.69nsThe peak width of 5% resolution is 118.11-88.21=29.9ns
shaping time constant: 25ns
Waveform width: 325ns
The peak width of 1% resolution is 109.29-95.97=13.32nsThe peak width of 4% resolution is 116.43-89.74=26.69nsThe peak width of 5% resolution is 118.11-88.21=29.9ns
2009/04/22 USTC, Shubin Liu 9
Charge measurement in Detail
2009/04/22 USTC, Shubin Liu 10
Time Measurement in Daya Bay Experiment
• A fast discriminator generates the timing pulse– The threshold is defined by a DAC set via VME interface– The leading edge of the output represents the arrival time of the signal
• The trigger signal deriving from trigger system is used as the stop signal• The TDC is built on a high-performance FPGA
– Two ultra high speed gray-code counters change at different phases of 1/2 a clock cycle
– Time precision of 1.5625ns and STD Error about 0.7ns can be achieved
Threshold
Disc.
~20ns width
Amp.
PMT1
0.25 p.e.
TDC
high performance FPGA
hit
L1 trigger
start
stop
delay line (640 MHz)
2009/04/22 USTC, Shubin Liu 11
TOT Scheme
AmpAmp
Disc.
Disc.
High Gain
Low Gain
High Threshold
Low Threshold
To External ADC (Cal ibration)
25ns delay
Digi tal Board (VME)Front End Board
Mul ti -Channels
TDC
VME Interface
Buff er
L1
To Trig. Logic
• The cable from PMT comes out of the pond and goes into the Front End Boards (FEB)
• The signal from each PMT is split and sent to high gain and low gain charge amplifiers, followed by a pair of discriminators with different PE thresholds
• The leading edge gives the pulse’s arrival time information, and the time which the amplified PMT signal spends over the low/high threshold represents the charge of the signal
• The FEB accommodate several neighboring PMTs’ process circuits• The digital signals carry the time information of the pulses to the digital boar
d via a long ribbon cable
2009/04/22 USTC, Shubin Liu 12
Concept of TOT
Signal Pulse
Threshold
Discriminator Signal
Signal Pulse
Threshold
Discriminator SignalTime Over Threshold
• The pulse height of a signal from PMT is proportional to the stored charge caused by photoelectrons
• A PMT pulse delivers a charge which charges a capacitor• The capacitor then discharges as that in a simple RC circuit• The leading edge gives the time information and the length of the
pulse gives the logarithm of the charge
)ln( PEsab Nttt
2009/04/22 USTC, Shubin Liu 13
The Conceptual Simulation for TOT
Cf
Rf
GND
+
-Vi nVout
Compari son
u1
x2
x1
f (x1. . . xn)
OpAmp
Ri n
Vth
Vti me
Vcc
Vee+
-
220
2 2( )
t
sig
VV t t e
e
2009/04/22 USTC, Shubin Liu 14
The Conceptual Simulation for TOT
• The time over threshold is proportional to the logarithm of the PE number
• Small signal with little amount PEs results in the large error– Amplification and low threshold discriminator for small signal are
essential– While amplification for large signal will lead to saturation
2009/04/22 USTC, Shubin Liu 15
Two Separate Thresholds Discriminator Concept
• A small pulse from the PMT can pass only the low threshold, and thus it only produces two crossing edge times
• A large signal can fire both the low threshold and the high threshold to generate 4 edge counts in the TDC– The delays in the circuit
ensure a fixed time interval (~25ns) between the low and high threshold outputs
)ln( PEscd Nttt
2009/04/22 USTC, Shubin Liu 16
The Advantages of Dual Threshold TOT• Achieve the wide dynamic range o
f charge measurement– The signals which are large enoug
h intend to saturate the high gain amplifier
• Alleviate the influence of Pre-pulsing
– A large PMT pulse with sufficiently large amount PEs increases the incidence of pre-pulsing which affects the low TOT value as well as the low start time
– High-start slewing is not influenced by pre-pulsing, so using the high-start slewing whenever it is possible is always the first choice
• Differentiate between overlapping pulses
– A long pulse will never be mistaken for a large signal if the high threshold does not fire
2009/04/22 USTC, Shubin Liu 17
TOT Circuit in Detail
2009/04/22 USTC, Shubin Liu 18
The Conceptual Simulation for Dual Threshold TOT
PMT R5912 signal pattern provided by Daya Bay Experiment's American Cooperator
The high gain channel is followed by a disc. wiht low threshold at 1/4 PE
The low gain channel is followed by a disc. wiht high threshold at 5 PEs
2009/04/22 USTC, Shubin Liu 19
The Conceptual Simulation for Dual Threshold TOT
2009/04/22 USTC, Shubin Liu 20
The Conceptual Simulation for Dual Threshold TOT
PMT R5912 signal pattern acquired in Daya Bay Experiment
The high gain channel is followed by a disc. wiht low threshold at 1/4 PE
The low gain channel is followed by a disc. wiht high threshold at 5 PEs
2009/04/22 USTC, Shubin Liu 21
The Conceptual Simulation for Dual Threshold TOT
2009/04/22 USTC, Shubin Liu 22
TDC Built on FPGA
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Q
QSET
CLR
D
Enc
oder
Del
ayD
elay
Del
ayD
elay
TDC low bits
Counter TDC high bits
FIF
O
Write
Channel n input
Clock
TDC Data
Channel ID
Read
The single channel time stamp measurement
Enable
Clear
Channel n Full
Dis
c
LVDS
FPGA(TDC)
Ext. SYN
50 MHzTCXO
Dat
a
I nterface
Add
r
Ctr
l
Data Memory192 MB
DCM
网络接口
CO
NFIG
DA
TA
/Add
r
• Based on the coarse-fine architecture consisted of the coarse counter and the time-coding delay line interpolator
• TDC built on FPGA achieves the precision of ~50ps (LSB) and STD error better than 25ps
Prototype
2009/04/22 USTC, Shubin Liu 23
TDC Built on FPGA
Cable Delay Test Setup
2009/04/22 USTC, Shubin Liu 24
The Advantages of TOT
1. A large amount of money is saved Two times of channels of ADCs are not needed The cheaper ribbon cable takes place of the coaxial cable
2. With the absence of ADC data, the event size is cut significantly, and in turn the ability to handle a higher trigger rate in the data acquisition is enhanced
3. The ADC conversion time is relatively slow and that may cause dead time during data taking
4. There is no need to worry about synchronizing the ADC
5. TDC data and the TOT has much better dynamic range than that in the ADC
6. Alleviate the influence of Pre-pulsing
2009/04/22 USTC, Shubin Liu 25
Calibration Apparatus
• Based on the laser - fiber-optic – diffusing ball concept– Adopted by Milagro/Milagrito– Calibration for slewing corrections and time offsets
2009/04/22 USTC, Shubin Liu 26
Trigger Logic
• Multiplicity trigger: If the number of PMT signals crossing the threshold in 200ns is higher than the setting number (20), the trigger is generated, and the information from the event is processed– For each PMT signal that crosses the threshold, the
corresponding electronics channel generates a logic pulse with 200 ns wide and a fixed amplitude
– The analog sum of all these fixed width pulses is sent to a discriminator
– If the analog sum is higher than the threshold setting, the trigger signal is generated
2009/04/22 USTC, Shubin Liu 27
Clock Distribution
GPS Recei verWi th
Rubi di um Osci l l ator
El ectro-opti calConverter
Opti cal -El ectroConverter
Fan-out
VME CratesAdj acent to
WCA 1
Opti cal Fi ber
LVDS or LVPECL
GPS t i me1PPS10KHz
40MHz Cl ock
GPS ti me/ 1PPS/ 10KHz
El ectro-opti calConverter
Opti cal -El ectroConverter
Fan-out
VME CratesAdj acent to
WCA 2
Opti cal Fi ber
LVDS or LVPECL
GPS t i me1PPS10KHz
40MHz Cl ock
El ectro-opti calConverter
Opti cal -El ectroConverter
Fan-out
VME CratesAdj acent to
WCA 3
Opti cal Fi ber
LVDS or LVPECL
GPS t i me1PPS10KHz
40MHz Cl ock
El ectro-opti calConverter
Opti cal -El ectroConverter
Fan-out
VME CratesAdj acent to
WCA 3
Opti cal Fi ber
LVDS or LVPECL
GPS t i me1PPS10KHz
40MHz Cl ock
Analogous with Daya Bay Experiment’s clock system
2009/04/22 USTC, Shubin Liu 28
Schedule
• Both traditional and TOT scheme are in progress– After the concept simulation, the schematic de
sign and PSPICE simulation has been started
• The first version of traditional scheme preamplifier is planned to be test in Daya Bay experiment circumstance
2009/04/22 USTC, Shubin Liu 29