IPC-7351BGeneric Requirements for Surface Mount Design and Land Pattern StandardDeveloped by the Surface Mount Land Patterns Subcommittee (1-13) of the Printed Board Design Committee (1-10) of IPCUsers of this publication are encouraged to participate in thedevelopment of future revisions. Contact: IPC 3000 Lakeside Drive, Suite 309S Bannockburn, Illinois60015-1249 Tel 847615.7100 Fax 847615.7105Supersedes:IPC-7351A - February 2007IPC-7351 - February 2005IPC-SM-782A withAmendments 1 & 2 -December 1999ivIPC-7351B June 2010Table of Contents1SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11.1Purpose. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2Documentation Hierarchy . . . . . . . . . . . . . . . . . . . . . . . 11.2.1Component and Land Pattern Family Structure. . . . . . 21.3Performance Classication . . . . . . . . . . . . . . . . . . . . . . 21.3.1Producibility Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4Land Pattern Determination. . . . . . . . . . . . . . . . . . . . . 21.5Terms and Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . 31.6Revision Level Changes . . . . . . . . . . . . . . . . . . . . . . . . 62APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . . . .72.1IPC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2Electronic Industries Association. . . . . . . . . . . . . . . . . 72.3Joint Industry Standards (IPC). . . . . . . . . . . . . . . . . . . 72.4International Electrotechnical Commission. . . . . . . . . 72.5Joint Electron Device Engineering Council(JEDEC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73DESIGN REQUIREMENTS. . . . . . . . . . . . . . . . . . . . . .73.1Dimensioning Systems. . . . . . . . . . . . . . . . . . . . . . . . . 73.1.1Component Tolerancing. . . . . . . . . . . . . . . . . . . . . . . . 83.1.2Land Tolerancing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.1.3Fabrication Allowances . . . . . . . . . . . . . . . . . . . . . . . . 123.1.4Assembly Tolerancing. . . . . . . . . . . . . . . . . . . . . . . . . 123.1.5Dimension and Tolerance Analysis . . . . . . . . . . . . . . . 123.2Design Producibility . . . . . . . . . . . . . . . . . . . . . . . . . . 293.2.1SMT Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293.2.2Standard Component Selection . . . . . . . . . . . . . . . . . . 293.2.3Circuit Substrate Development . . . . . . . . . . . . . . . . . . 293.2.4Assembly Considerations. . . . . . . . . . . . . . . . . . . . . . 293.2.5Provision for Automated Test. . . . . . . . . . . . . . . . . . . 293.2.6Documentation for SMT . . . . . . . . . . . . . . . . . . . . . . . 293.3Environmental Constraints. . . . . . . . . . . . . . . . . . . . . 303.3.1Moisture Sensitive Components . . . . . . . . . . . . . . . . . 303.3.2End-Use Environment Considerations. . . . . . . . . . . . 303.4Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.4.1Component Spacing. . . . . . . . . . . . . . . . . . . . . . . . . . 313.4.2Single-and Double-Sided Printed BoardAssembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.4.3Component Stand-off Height for Cleaning . . . . . . . . . 323.4.4Fiducial Marks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.4.5Conductors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.4.6Via Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.4.7Standard Printed Board Fabrication Allowances. . . . . 373.4.8Panelization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393.5Outer Layer Surface Finishes. . . . . . . . . . . . . . . . . . . 413.5.1Solder Mask Finishes. . . . . . . . . . . . . . . . . . . . . . . . . 413.5.2Solder Mask Clearances. . . . . . . . . . . . . . . . . . . . . . . 413.5.3Land Pattern Surface Finishes. . . . . . . . . . . . . . . . . . . 414COMPONENT QUALITY VALIDATION . . . . . . . . . . . .424.1Validation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . 425TESTABILITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .435.1Printed Board and Assembly Test . . . . . . . . . . . . . . . . 435.1.1Bare Printed Board Test. . . . . . . . . . . . . . . . . . . . . . . . 435.1.2Assembled Printed Board Test. . . . . . . . . . . . . . . . . . 435.2Nodal Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435.2.1Test Philosophy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445.2.2Test Strategy for Bare Printed Boards. . . . . . . . . . . . . 445.3Full Nodal Access for Assembled Printed Board. . . . 445.3.1In-Circuit Test Accommodation. . . . . . . . . . . . . . . . . 445.3.2Multi-Probe Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . 455.4Limited Nodal Access . . . . . . . . . . . . . . . . . . . . . . . . . 455.5No Nodal Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455.6Clam-Shell Fixtures Impact. . . . . . . . . . . . . . . . . . . . . 455.7Printed Board Test Characteristics. . . . . . . . . . . . . . . 455.7.1Test Land Pattern Spacing. . . . . . . . . . . . . . . . . . . . . . 455.7.2Test Land Size and Shape . . . . . . . . . . . . . . . . . . . . . . 455.7.3Design for Test Parameters . . . . . . . . . . . . . . . . . . . . . 466PRINTED BOARD STRUCTURE TYPES. . . . . . . . . .466.1General Considerations . . . . . . . . . . . . . . . . . . . . . . . . 486.1.1Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496.1.2Thermal Expansion Mismatch. . . . . . . . . . . . . . . . . . . 496.2Organic-Base Material. . . . . . . . . . . . . . . . . . . . . . . . 496.3Nonorganic Base Materials . . . . . . . . . . . . . . . . . . . . . 496.4Alternative Printed Board Structures. . . . . . . . . . . . . 496.4.1Supporting-Plane Printed Board Structures. . . . . . . . 496.4.2High-Density Printed Board Technology. . . . . . . . . . 496.4.3Constraining Core Structures. . . . . . . . . . . . . . . . . . . 496.4.4Porcelainized Metal (Metal Core) Structures. . . . . . . 497ASSEMBLY CONSIDERATIONS FOR SURFACE MOUNT TECHNOLOGY (SMT) . . . . . . . . . . . . . . . . . .497.1SMT Assembly Process Sequence. . . . . . . . . . . . . . . 497.2Substrate Preparation. . . . . . . . . . . . . . . . . . . . . . . . . 507.2.1Adhesive Application. . . . . . . . . . . . . . . . . . . . . . . . . 507.2.2Conductive Adhesive. . . . . . . . . . . . . . . . . . . . . . . . . . 507.2.3Solder Paste Application . . . . . . . . . . . . . . . . . . . . . . . 507.2.4Solder Preforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517.3Component Placement. . . . . . . . . . . . . . . . . . . . . . . . . 517.3.1Component Data Transfer . . . . . . . . . . . . . . . . . . . . . . 517.4Soldering Processes. . . . . . . . . . . . . . . . . . . . . . . . . . . 517.4.1Wave Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51June 2010 IPC-7351Bv7.4.2Vapor Phase (VP) Soldering . . . . . . . . . . . . . . . . . . . . 527.4.3IR Reow Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . 527.4.4Hot Air/Gas Convection. . . . . . . . . . . . . . . . . . . . . . . 527.4.5Laser Reow Soldering. . . . . . . . . . . . . . . . . . . . . . . . 537.4.6Conduction Reow Soldering . . . . . . . . . . . . . . . . . . . 537.5Cleaning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537.6Repair/Rework. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537.6.1Heatsink. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537.6.2Dependence on Printed Board Material. . . . . . . . . . . 537.6.3Dependence on Copper Land and ConductorLayout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538IPC-7352 DISCRETE COMPONENTS . . . . . . . . . . . .548.1Chip Resistors (RESC) . . . . . . . . . . . . . . . . . . . . . . . . 548.1.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 548.1.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558.1.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 558.1.4Resistance to Soldering Process. . . . . . . . . . . . . . . . . 558.2Chip Capacitors (CAPC) . . . . . . . . . . . . . . . . . . . . . . . 558.2.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 558.2.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558.2.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 558.2.4Resistance to Soldering Process Temperatures . . . . . . 568.3Inductors (INDC, INDM, INDP). . . . . . . . . . . . . . . . 568.3.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 568.3.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568.3.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 568.3.4Resistance to Soldering Process Temperatures . . . . . . 568.4Molded Body (CAPMP, CAPM, DIOM, FUSM, INDM, INDP, LEDM, RESM) . . . . . . . . . . . . . . . . . . 578.4.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 578.4.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.4.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 578.4.4Resistance to Soldering Process Temperatures . . . . . . 578.5Metal Electrode Face (DIOMELF, RESMELF) . . . . . 578.5.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 578.5.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578.5.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 578.5.4Resistance to Soldering Process Temperatures . . . . . . 578.6SOT23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588.6.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 588.6.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588.6.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 588.6.4Resistance to Soldering Process Temperatures . . . . . . 588.7SOT89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588.7.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 588.7.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588.7.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 588.7.4Resistance to Soldering Process Temperatures . . . . . . 588.8SOD123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588.8.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 588.8.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588.8.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 588.8.4Resistance to Soldering Process Temperatures . . . . . . 598.9SOT143 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598.9.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 598.9.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598.9.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 598.9.4Resistance to Soldering Process Temperatures . . . . . . 598.10SOT223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598.10.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 598.10.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598.10.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 598.10.4Resistance to Soldering Process Temperatures . . . . . . 598.11DPAK (TO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608.11.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 608.11.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608.11.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 608.11.4Resistance to Soldering Process Temperatures . . . . . . 608.12Electrolytic Aluminum Capacitor (CAPAE) . . . . . . . . 608.12.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 608.12.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608.12.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 608.12.4Resistance to Soldering Process Temperatures . . . . . . 608.13Small Outline Diode, Flat Lead (SODFL)/Small Outline Transistor, Flat Lead (SOTFL) . . . . . . . . . . . . 618.13.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 618.13.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618.13.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 618.13.4Resistance to Soldering Process Temperatures . . . . . . 619IPC-7353 GULLWING LEADED COMPONENTS,TWO SIDES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .619.1SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629.1.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 629.1.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629.1.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 629.1.4Resistance to Soldering Process Temperatures . . . . . . 629.2SOP8/SOP64 (SOP). . . . . . . . . . . . . . . . . . . . . . . . . . 639.2.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 639.2.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639.2.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 639.2.4Resistance to Soldering Process Temperatures . . . . . . 649.3SOP127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649.3.1Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649.3.2Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 64viIPC-7351B June 20109.3.3Resistance to Soldering Process Temperatures . . . . . . 649.4CFP127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649.4.1Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649.4.2Carrier Packages Format . . . . . . . . . . . . . . . . . . . . . . . 649.4.3Resistance to Soldering Process Temperatures . . . . . . 6410IPC-7354 J-LEADED COMPONENTS, TWO SIDES .6510.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 6510.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6510.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 6510.4Process Considerations . . . . . . . . . . . . . . . . . . . . . . . . 6611IPC-7355 GULL-WING LEADED COMPONENTS,FOUR SIDES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6611.1BQFP or PQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6811.1.1Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 6811.2QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6811.2.1Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 6811.3CQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6811.3.1Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 6912IPC-7356 J LEADED COMPONENTS, FOURSIDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6912.1PLCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7112.1.1Premolded Plastic Chip Carriers . . . . . . . . . . . . . . . . . 7112.1.2Postmolded Plastic Chip Carriers . . . . . . . . . . . . . . . . 7112.2PLCCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7112.2.1Premolded Plastic Chip Carriers . . . . . . . . . . . . . . . . . 7112.2.2Postmolded Plastic Chip Carriers . . . . . . . . . . . . . . . . 7113IPC-7357 POST (DIP) LEADS, TWO SIDES . . . . . . 7213.1Termination Materials . . . . . . . . . . . . . . . . . . . . . . . . . 7213.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7213.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 7213.4Resistance to Soldering Process Temperatures . . . . . . 7214IPC-7358 AREA ARRAY COMPONENTS (BGA,FBGA, CGA, LGA, Chip Array) . . . . . . . . . . . . . . . . .7314.1Area Array Congurations. . . . . . . . . . . . . . . . . . . . . 7314.1.1BGA Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7414.1.2Fine Pitch BGA Package (FBGA). . . . . . . . . . . . . . . . 7514.1.3Ceramic/Plastic Column Grid Arrays (CGA) . . . . . . . 7614.1.4Plastic Land Grid Arrays (LGA) . . . . . . . . . . . . . . . . . 7614.2General Conguration Issues. . . . . . . . . . . . . . . . . . . 7614.2.1Device Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7614.2.2Contact Matrix Options. . . . . . . . . . . . . . . . . . . . . . . . 7614.2.3Selective Depopulation . . . . . . . . . . . . . . . . . . . . . . . . 7714.2.4Attachment Site Planning . . . . . . . . . . . . . . . . . . . . . . 7714.2.5Dening Contact Assignment . . . . . . . . . . . . . . . . . . . 7814.3Handling and Shipping . . . . . . . . . . . . . . . . . . . . . . . . 7814.4Land Pattern Analysis . . . . . . . . . . . . . . . . . . . . . . . . . 7814.4.1Land Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 7914.4.3Land Pattern Calculator. . . . . . . . . . . . . . . . . . . . . . . . 8014.5Chip Array Component Lead Packages. . . . . . . . . . . . 8014.5.1Concave Chip Array Packages (RESCAV,CAPCAV, INDCAV, OSCSC, OSCCCC) . . . . . . . . . . 8014.5.2Convex Chip Array Packages(RESCAXE, RESCAXS). . . . . . . . . . . . . . . . . . . . . . 8014.5.3Flat Chip Array Packages (RESCAF, CAPCAF, INDCAF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8115IPC-7359 NO-LEAD COMPONENTS (QFN,PQFN, SON, PSON, DFN, LCC). . . . . . . . . . . . . . . . .8115.1LCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8115.1.1Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8215.1.2Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 8215.1.3Process Considerations . . . . . . . . . . . . . . . . . . . . . . . . 8215.2Quad Flat No-Lead (QFN). . . . . . . . . . . . . . . . . . . . . 8315.2.1Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8415.2.2Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 8415.2.3Process Considerations . . . . . . . . . . . . . . . . . . . . . . . . 8415.2.4Solder Mask Considerations . . . . . . . . . . . . . . . . . . . . 8415.3Small Outline No-Lead (SON) . . . . . . . . . . . . . . . . . . 8515.3.1Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8515.3.2Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 8515.3.3Process Considerations . . . . . . . . . . . . . . . . . . . . . . . . 8515.3.4Solder Mask Considerations . . . . . . . . . . . . . . . . . . . . 8515.4Small Outline and Quad Flat No-Lead withPullback Leads (PQFN, PSON). . . . . . . . . . . . . . . . . 8515.5Dual Flat No-Lead (DFN) . . . . . . . . . . . . . . . . . . . . . . 8515.5.1Basic Construction. . . . . . . . . . . . . . . . . . . . . . . . . . . 8515.5.2Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8515.5.3Carrier Package Format. . . . . . . . . . . . . . . . . . . . . . . . 8515.5.4Resistance to Soldering Process Temperatures . . . . . . 8616ZERO COMPONENT ORIENTATIONS. . . . . . . . . . . .86APPENDIX A(INFORMATIVE) TEST PATTERNS PROCESS EVALUATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 93A.1Test Vehicle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93A.2Test Patterns -In-Process Validator . . . . . . . . . . . . . . . 93A.3Stress Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94APPENDIX BIPC-7351 LAND PATTERNCALCULATOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95B.1Software Installation . . . . . . . . . . . . . . . . . . . . . . . . . . 95B.2Software Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95B.3Software Updates. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95FIGURESFigure 3-1Prole Tolerancing Method. . . . . . . . . . . . . . . . . . 8Figure 3-2Example of 3216 (1206) Capacitor Dimensioningfor Optimum Solder Fillet Condition . . . . . . . . . . . 9June 2010 IPC-7351BviiFigure 3-3Prole Dimensioning of Gull-Wing LeadedSOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 3-4Pitch for Multiple Leaded Components . . . . . . . . 14Figure 3-6Examples of Land Shape Modiers . . . . . . . . . . . 25Figure 3-7Examples of Chamfered Corner Modiers. . . . . . 27Figure 3-8Component Orientation for Wave-Solder Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Figure 3-9Alignment of Similar Components. . . . . . . . . . . . 32Figure 3-11Local Fiducials . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 3-10Global/Panel Fiducials . . . . . . . . . . . . . . . . . . . . . 33Figure 3-13Fiducial Size and Clearance Requirements. . . . . 34Figure 3-12Fiducial Locations on a Printed Board. . . . . . . . . 34Figure 3-14Use of Vias in High Component DensityPrinted Boards. . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 3-15Land Pattern to Via Relationship . . . . . . . . . . . . . 35Figure 3-16Examples of Via Positioning Concepts. . . . . . . . 36Figure 3-17Vias under Components . . . . . . . . . . . . . . . . . . . . 36Figure 3-18Filled and Capped Via Structure. . . . . . . . . . . . . . 37Figure 3-19Via-in-Pad Process Description. . . . . . . . . . . . . . 37Figure 3-20Conductor Description . . . . . . . . . . . . . . . . . . . . . 38Figure 3-22Typical Copper Glass Laminate Panel . . . . . . . . . 39Figure 3-21 Examples of Modied Landscapes . . . . . . . . . . . 39Figure 3-23Conductor Clearance for V-Groove Scoring. . . . 40Figure 3-24Breakaway (Routed Pattern) with RoutedSlots. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Figure 3-25Gang Solder Mask Window . . . . . . . . . . . . . . . . . 41Figure 3-26Pocket Solder Mask Window. . . . . . . . . . . . . . . . 41Figure 4-1Component Operating Temperature Limits. . . . . 42Figure 5-1Test Via Grid Concepts. . . . . . . . . . . . . . . . . . . . . 44Figure 5-2General Relationship between Test ContactSize and Test Probe Misses. . . . . . . . . . . . . . . . . 45Figure 5-3Test Probe Feature Distance fromComponent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Figure 7-1Typical Process Flow for One-Sided SMT. . . . . . 50Figure 7-2Assembly Process Flow for Two-SidedSurface Mount with THT . . . . . . . . . . . . . . . . . . . 50Figure 8-1Packaging of Discrete Components . . . . . . . . . . . 54Figure 8-2Chip Resistor Construction. . . . . . . . . . . . . . . . . . 55Figure 8-3Chip Capacitor Construction. . . . . . . . . . . . . . . . 56Figure 8-6MELF Component Construction. . . . . . . . . . . . . 57Figure 8-7Break-Away Diagram of MELF Components. . . 57Figure 8-5Molded Body Construction. . . . . . . . . . . . . . . . . 57Figure 8-8SOT23 Construction SOT23Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Figure 8-9SOT 89 Construction. . . . . . . . . . . . . . . . . . . . . . 58Figure 8-10SOD123 Construction. . . . . . . . . . . . . . . . . . . . . 59Figure 8-11SOT143 Construction. . . . . . . . . . . . . . . . . . . . . . 59Figure 8-12SOT223 Construction. . . . . . . . . . . . . . . . . . . . . . 60Figure 8-13DPAK (TO) Construction. . . . . . . . . . . . . . . . . . . 60Figure 8-14Aluminum Electrolytic Capacitor(CAPAE) Construction. . . . . . . . . . . . . . . . . . . . . 60Figure 8-15SODFL/SOTFL Construction. . . . . . . . . . . . . . . . 61Figure 9-1SOIC Construction . . . . . . . . . . . . . . . . . . . . . . . . 63Figure 9-2SOP8/SOP63 Construction. . . . . . . . . . . . . . . . . . 63Figure 9-3SOP127 Construction. . . . . . . . . . . . . . . . . . . . . . 64Figure 9-4CFP127 Construction . . . . . . . . . . . . . . . . . . . . . . 64Figure10-1SOJ Construction . . . . . . . . . . . . . . . . . . . . . . . . . 65Figure 11-2QFP Construction . . . . . . . . . . . . . . . . . . . . . . . . . 68Figure 11-1BQFP Construction. . . . . . . . . . . . . . . . . . . . . . . . 68Figure 11-3CQFP Construction. . . . . . . . . . . . . . . . . . . . . . . . 68Figure 12-1PLCC Construction. . . . . . . . . . . . . . . . . . . . . . . 71Figure 12-2PLCCR Construction . . . . . . . . . . . . . . . . . . . . . . 71Figure 13-1DIP Construction. . . . . . . . . . . . . . . . . . . . . . . . . 72Figure 14-1Ball Grid Array (BGA) IC PackageExample. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Figure 14-2Example of Plastic BGA PackageCongurations. . . . . . . . . . . . . . . . . . . . . . . . . . . 74Figure 14-3Ceramic/Plastic Column Grid Array (CGA)Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 14-4Plastic Land Grid Array (LGA) Package Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 14-5Variation of BGA Contact Pitch in CommonPackage Outlines. . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 14-6One Package Size, Two Full Matrices . . . . . . . . . 77Figure 14-8Staggered Matrix. . . . . . . . . . . . . . . . . . . . . . . . . 77Figure 14-7Perimeter and Thermally EnhancedMatrices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Figure 14-9Selective Depopulation. . . . . . . . . . . . . . . . . . . . . 77Figure 14-10Device Orientation and Contact A1Position. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Figure 14-11Side Concave Chip Component . . . . . . . . . . . . . . 81Figure 14-13Convex Chip Component E Version . . . . . . . . . 81Figure 14-12Corner Concave Chip Component . . . . . . . . . . . . 81Figure 14-14Convex Chip Component S Version . . . . . . . . . 81Figure 14-15Flat Chip Component . . . . . . . . . . . . . . . . . . . . . . 81Figure 15-1LCC Component. . . . . . . . . . . . . . . . . . . . . . . . . . 82Figure 15-2Quad Flat No-Lead (QFN) Construction . . . . . . . 83Figure 15-3Quad Flat No-Lead (QFN) Construction(Cross-Sectional View). . . . . . . . . . . . . . . . . . . . . 83Figure 15-4QFN Devices with Multiple Paste MaskApertures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Figure 15-5Small Outline No-Lead (SON)Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Figure 15-6Pullback Quad Flat No Lead (PQFN) andSmall Outline No Lead (PSON) Construction . . . 85Figure 15-7DFN Construction. . . . . . . . . . . . . . . . . . . . . . . . 86Figure 16-1Zero Component Rotations for CommonPackage Outlines. . . . . . . . . . . . . . . . . . . . . . . . . 87Figure A-1General Description of Process ValidationContact Pattern and Interconnect . . . . . . . . . . . . . 93viiiIPC-7351B June 2010Figure A-2Photoimage of IPC Test Board for PrimarySide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94TABLESTable 3-1Tolerance Analysis Elements for ChipDevices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Table 3-2Flat Ribbon L and Gull-Wing Leads(greater than 0.625 mm pitch) (unit: mm). . . . . . 16Table 3-3Flat Ribbon L and Gull-Wing Leads(less than or equal to 0.625 mm pitch)(unit: mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 3-4J Leads (unit: mm) . . . . . . . . . . . . . . . . . . . . . . . . 16Table 3-5Rectangular or Square-End Components (Capacitors and Resistors) Equal to or Largerthan 1608 (0603) (unit: mm). . . . . . . . . . . . . . . . 17Table 3-6Rectangular or Square-End Components (Capacitors and Resistors) Smaller than 1608 (0603) (unit: mm) . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 3-7Cylindrical End Cap Terminations (MELF)(unit: mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 3-8Leadless Chip Carrier with Castellated Terminations (unit: mm). . . . . . . . . . . . . . . . . . . . 17Table 3-9Concave Chip Array Component Lead Package (unit: mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 3-10Convex Chip Array Component Lead Package (unit: mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 3-11Flat Chip Array Component Lead Package(unit: mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Table 3-12Butt Joints (unit: mm). . . . . . . . . . . . . . . . . . . . . . 18Table 3-13Inward Flat Ribbon L-Leads (Molded Inductors, Diodes & Polarized Capacitors) (unit: mm). . . . . 19Table 3-14Flat Lug Leads (unit: mm) . . . . . . . . . . . . . . . . . . 19Table 3-15Quad Flat No-Lead (unit: mm). . . . . . . . . . . . . . . 19Table 3-16Small Outline No-Lead (unit: mm). . . . . . . . . . . 19Table 3-17Ball Grid Array Components (unit: mm) . . . . . . . 20Table 3-18Small Outline and Quad Flat No-Lead with Pullback Leads (unit: mm) . . . . . . . . . . . . . . . . . . 20Table 3-19Corner Concave Component Oscillator Lead Package (unit: mm). . . . . . . . . . . . . . . . . . . . . . . . 20Table 3-20Aluminium Electrolytic Capacitor and 2-pin Crystal (unit: mm). . . . . . . . . . . . . . . . . . . . . . . . 20Table 3-21Column and Land Grid Array (unit: mm). . . . . . . 21Table 3-22Small Outline Components, Flat Lead(unit: mm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Table 3-23IPC-7351 Land Pattern Naming Convention . . . . 24Table 3-24Product Categories and Worst-Case Use Environments for Surface Mounted Electronics (For Reference Only) . . . . . . . . . . . . . . . . . . . . . . 30Table 3-25Nominal Finished Conductor Width Tolerances, 0.046 mm [0.0018 in] Copper, mm [in] . . . . . . . . 38Table 3-26Feature Location Accuracy (units: mm [in]). . . . 38Table 3-27Key Attributes for Various Board SurfaceFinishes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Table 6-1Printed Board Structure Comparison . . . . . . . . . . 46Table 6-2Printed Board Structure SelectionConsiderations. . . . . . . . . . . . . . . . . . . . . . . . . . . 48Table 6-3Printed Board Structure Material Properties. . . . 48Table 8-1Solderability Tests for Discrete Components . . . . 54Table 8-2Solderability, Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . 55Table 8-3Package Peak Reow Temperatures. . . . . . . . . . . 55Table 9-1Solderability Tests for Gullwing Leaded Components, Two Sides . . . . . . . . . . . . . . . . . . . . 62Table 9-2Solderability, Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . 62Table 9-3Package Peak Reow Temperatures. . . . . . . . . . . 63Table 10-1Solderability Tests for J-Leaded Components,Two Sides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65Table 10-2Solderability, Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . 66Table 10-3Package Peak Reow Temperatures. . . . . . . . . . . 66Table 11-1Solderability Tests for Gullwing Components,Four Sides. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Table 11-2Solderability, Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . 67Table 11-3Package Peak Reow Temperatures. . . . . . . . . . . 67Table 12-1Solderability Tests for J-Leaded Components,Four Sides. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 12-2Solderability, Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . 70Table 12-3Package Peak Reow Temperatures. . . . . . . . . . . 70Table 13-1Solderability Tests for Post (DIP) Leads,Two Sides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Table 13-2Solderability, Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . 73Table 13-3Package Peak Reow Temperatures. . . . . . . . . . . 73Table 14-1Solderability Tests for Discrete Components . . . . 74Table 14-2Package Peak Reow Temperatures. . . . . . . . . . . 75Table 14-3JEDEC Standard JEP95Allowable BallDiameter Variations for FBGA (mm) . . . . . . . . . 75Table 14-4Ball Diameter Sizes (mm). . . . . . . . . . . . . . . . . . 78Table 14-5Land Approximation (mm) for CollapsibleSolder Balls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Table 14-6Land Approximation (mm) for Non-Collapsible Solder Balls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Table 14-7BGA Variation Attributes (mm) . . . . . . . . . . . . . . 80Table 14-8Land-to-Ball Calculations for Current andFuture BGA Packages (mm). . . . . . . . . . . . . . . . . 80Table 15-1Solderability Tests for No Lead Components. . . . 82Table 15-2Solderability, Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . 83Table 15-3Package Peak Reow Temperatures. . . . . . . . . . . 83June 2010 IPC-7351B1Generic Requirements for SurfaceMount Design and Land Pattern Standard1SCOPE This document provides generic requirements on land pattern geometries used for the surface attachment of electronic components, as well as surface mount design recommendations for achieving the best possible solder joints to the devices assembled. 1.1PurposeThe intent of the information presented herein is to provide the appropriate size, shape and tolerance of surface mount land patterns to insure suffcient area for the appropriate solder fllet to meet the requirements of IPC J-STD-001, and also to allow for inspection, testing, and rework of those solder joints. Designers can use the information contained herein to establish standardlandpatterngeometriesnotonlyformanualdesignsbutalsoforcomputer-aideddesignsystems.Whetherpartsare mounted on one or both sides of the printed board, subjected to wave, reow, or other type of soldering, the land pattern and part dimensions should be optimized to insure proper solder joint and inspection criteria. Land patterns become a part of the printed board circuitry and they are subject to the producibility levels and tolerances associated withfabricationandassemblyprocesses.Theproducibilityaspectsalsopertaintotheuseofsoldermaskandtheregistration required between the solder mask and the conductor patterns.In addition to the land pattern geometries required for proper solder joint formation, other mounting conditions must be considered, such as solder mask clearance, solder paste stencil aperture sizes, clearance between adjacent components, clearance between the bottom of the component and the printed board surface (if relevant), keep-out areas (if relevant), and suitable rules for adhesive applications. These additional features become part of the overall land pattern standard for each component type. Note 1: The dimensions used for component descriptions have been extracted from standards listed in Section 2. Designers should refer to the manufacturers data sheet for specic component package dimensions.Caution:Usersshouldbeawarethatindividualcomponentdatasheetsmaynotmeetstandardizedcomponentoutlines(.e.g., JEDEC standard component outlines).Note 2: Elements of the mounting conditions, particularly the courtyard, given in this standard are related to the reow soldering process. Adjustmentsforwaveorothersolderingprocesses,ifapplicable,havetobecarriedoutbytheuser. Thismayalsobe relevant when solder alloys other than eutectic tin lead solders are used. Note 3: This standard assumes that even under worst case tolerance conditions the opportunity for an acceptable solder llet will be maintained. Note 4: Heat dissipation aspects have not been taken into account in this standard. Greater mass may require slower process speed to allow heat transfer. Note 5: For surface mount components, the solder joints provide not only the electrical connection, but the mechanical support as well. Heavier components (greater weight per land) require larger lands; thus, adding additional land pattern surface will increase surface area of molten solder to enhance capabilities of extra weight. In some cases the lands shown in this standard may not apply for a particular application and may need to be increased in a land pattern library; in these cases, considering additional measures may be necessary. 1.2Documentation HierarchyThis standard identifes the generic physical design principles involved in the creation of land patternsforsurfacemountcomponents,andissupplementedbyasharewareIPC-7351LandPatternCalculatorthatprovides, through the use of a graphical user interface, the individual component dimensions and corresponding land pattern recommendations baseduponfamiliesofcomponents.TheIPC-7351LandPatternCalculatorisprovidedonCD-ROMaspartofthisstandard. Updates to land pattern dimensions, including patterns for new component families, can be found on the IPC website (www.ipc.org) under the Knowledge menu, within PCB Tools and Calculators. See Appendix B for more information on the IPC-7351 Land Pattern Calculator.