irena - from preamp to the usb - sektion physik der cau kiel · irena - from preamp to the usb...

CSA Shaper ADC FPGA Verilog DIRENA

IRENA - from preamp to the USB

Stephan I. Bottcher

Institut fur Experimentelle und Angewandte PhysikChristian Albrechts Universitat zu Kiel

Sommersemester 2013

Stephan I. Bottcher IEAP, CAU Kiel

IRENA - from preamp to the USB Sommersemester 2013


Charge Sensitive Amplifiers

Charge Sensitive Amplifiers

I Principle

I Detector coupling

I Input jFET

I Miller Effect

I Full schematic

I HET layout




Principle

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TITLECharge Sensitive Amplifier: Principle

$Revision$

CF

INOUT

RF

I Gain: 1/Cf

I Typical Cf = 1 pF . . . 10 pF

I Time constant: τ = RfCf

I Typical τ = 100µs

i(t) = Q δ(t) q(t) = −Q/Cf Θ(t) exp(−t/τ)

Delta pulse response: h(t) = − 1Cf

Θ(t) exp(−t/τ)

Transfer function: H(s) = L(h) = − 1Cf

τ1+sτ




Detector Coupling

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TITLECharge Sensitive Amplifier: Coupling

$Revision$

CF

OUT

RF

BIAS

Det

CC

RB

CF

OUT

RF

BIAS

Det

Directly coupled

Indirectly coupled

Indirectly coupled detector:I Works with higher leakage currents

Directly coupled detector:

I No bias resistor, less noise,

I Output DC level can be used to readthe detector leakage current.

I Requires low leakage current.

I Reduced dynamic range.

Most silicon detectors have p-type junctions.Segmented detectors must be read out fromthe junction side. That requires positive biasvoltage for directly coupled detectros and neg-ative bias voltage for indirectly coupled detec-tors. Hamamatsu photodiodes can be used ei-ther way. In space we use indirect couplingto cope with degrading detectors. stein usesdirect coupling.




Input Junction Field Effect Transistor

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TITLECharge Sensitive Amplifier: FET

$Revision$

CF

OUT

RF

BIAS

Det

CC

RB

Jfet

RD

VF

ET

+− VD

I Low noise jFET, BF 862:en = 0.8 nV/

√Hz, Cd = 10 pF.

I Constant drain currentId = (VFET − Vd)/Rd.

I Constant gate voltage, output DC-level.

The serial noise of this amplifier is proportionalto the sum of the detector, gate, and feedbackcapacitances

qineq = en (Cdet + Cg + Cf).

The detector yields one electron charge for3.6 eV deposited energy. Using a BF 862 witha shaping time of 1µs:

Eeq = 0.8 nV/√

HZ·√

1 MHz

·3.6 eV/(1.6·10−19 As)

= 18 eV/pF.




Miller Effect

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$Revision$

CF

OUT

RF

BIAS

Det

CC

RB

Jfet

RD

VF

ET

Q1

VS

S

IC+− VB1

Miller effect: The effective Gate-Drain Capacitance is

Cgd,eff = y RdCgd = 20 mS·470 Ω·1.9 pF = 18 pF.

A common base stage provides a low drain impedance to mitigate themiller effect.




HET-EPT CSA Schematic

C1 10nF

c1206

C2 $CF

c0603

R2 $RF

c0805

q1ou

tq2_out

fet_

gate

C31

100n

F

c080

5

vfet

2 D

1 S3G

Q1

SOT23BF862

R3

470Ωc060

3

C12

100n

F

c080

5C

13

100n

F

c080

5

vss_u1

vcc_u1

R1

10M

Ω

c080

5

C51

10nF

c120

6

R51

10M

Ω

c080

5

vbias_filtered3 +

4 -1

5 VCC

2 VSS

AD8005 U1

SOT23_5CFA

R13

75Ω

c060

3R

12

75Ω

c060

3

R31

470Ωc0

603

C3

100n

F

c080

5

vfet_q1

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TITLE

Common base stage with current source type Charge Sensitive Amplifier

$Date: 2012-07-23 14:36:46 +0200 (Mo, 23 Jul 2012) $

CSA-Beau-2.sch $Revision: 1174 $

$Author: stephan $

$Id: CSA-Beau-F.sch 1174 2012-07-23 12:36:46Z stephan $

u1_i

out

in

VccVfet

Vss

Vbias

R9

1kΩ

c060

3

C710

0nF

c080

5

R8

33kΩ

c060

3R

712

0kΩ

c060

3

R6

68kΩ c0603

q2bias

R4

1.5k

Ω

c0603vss_f1

q3bias

C8

100n

F

c080

5

C62

100n

F

c080

5

R62

75Ω

c060

3

32

1

Q2UB2N4957UBJ

GND:4

3

2

1Q3

UB2N2857UBJX

GND:4

q3e

C52

10nF

c1206

GND




Layout Top




Layout Bottom




Further reading

I http://www.nikhef.nl/~jds/vlsi/noise/Amplifiers.PDF

I http://www.nxp.com/documents/data_sheet/BF862.pdf

I http://en.wikipedia.org/wiki/Laplace_transform



http://www.nikhef.nl/~jds/vlsi/noise/Amplifiers.PDF

http://www.nxp.com/documents/data_sheet/BF862.pdf

http://en.wikipedia.org/wiki/Laplace_transform


Shaper amplifier

Shaper amplifier

I Principle

I Pole-Zero cancelation

I Full schematic

I Inverse Laplace Transform

I Shaper output waveform




Principle

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TITLEShaper: Principle

$Revision$

C2

INOUT

R2

C1

R1

I Gain: a = R2/R1 = C1/C2

I Time constant: τ = R1C1 = R2C2

I Typical: τ = 1µs . . . 2.2µs

Differentiation: Z1(jω) = R1 + 1jωC1

= R11+jωτjωτ

Integration: Z2(jω) =R2

jωC2

R2+ 1jωC2

= R21+jωτ

Transfer function: H(s) = Z2(s)Z1(s) = asτ

(1+sτ)2

a = R2/R1 = C1/C2




Pole-Zero Cancelation

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TITLEShaper: Pole−Zero Cancelation

$Revision$

C2

INOUT

R2

C1

R1

R0

Compensate the preamplifier discharge time constant.

I τP = C1R0 = 100µs

I τS = C1R1 = C2R2 = 2.2µs

I a = R2/R1 = C1/C2

Exercise:Find the transfer function of the shaper with pole-zero cancelation.




HET-EPT Shaper Schematic

4 IN0

15DOUT

1nCS

16SCLK

12

DGND

2

VA

3

AGND

13

VD

14DIN

5 IN16 IN27 IN38 IN49 IN510 IN611 IN7ADC128S102CSOIC16

U2

A+3.3V D+3.3V

C9

C8

A+3.3V D+3.3V

IN0

IN1IN2IN3IN4IN5IN6IN7

DIN

VD

GND

VA

DOUT

nCS

SCLK

C3$C3

R3

$R3

u1inv

u1out

u1vssu1vcc

3+

4-

1

5 VCC

2 VSSAD8005

U1SOT23_5

CFA

C1$C1

L575

Ω

c060

3

L475

Ω

R7

51Ω

R2

220Ω

u1fb

inz

C7

6n8

C5

C4

VC

C

VE

E

u2in

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TITLE

$Id: heteptshadc.sch 1283 2012-10-08 15:12:26Z stephan $

$Date: 2012-10-08 17:12:26 +0200 (Mo, 08 Okt 2012) $

heteptshadc.sch $Revision: 1283 $

$Author: stephan $

C0$C0

R0

$R0

pz

parameter=C1:10nFparameter=R1:220Ω (on preamp board)

parameter=C3:220pFparameter=R3:10kΩ

parameter=R0:10kΩparameter=C0:220nF

Spaping time τ=2.2µsPole-Zero comp τr=100µsGain 16




Transfer function

INPUT OUTPUT

C2

Rf

Cf

R2

Cr

RrC0

R1 C1

R0

τ = R1C1 = R2C2, τP = RrCr = R0C1, τZ = C0R0, τF = Rf Cf

HP = 1Cr

τP1+sτP

, HS = asττZτP

1+sτP(1+sτ)2(1+sτZ)

, HF = 11+sτF

H(s) = HP(s)HS(s)HF(s) = 1Cr

τZ1+sτZ

asτ(1+sτ)2

11+sτF

i(t) = Q δ(t)q(t) = Q L−1(H)




Shaper output waveform

maxima

display2d:false$

H: s/(1+s*T)**2/(1+s*TR)/(1+s*TP);

h: ilt(H,s,t);

-TR*%e^-(t/TR)/(TR^3+(-TP-2*T)*TR^2+(2*T*TP+T^2)*TR-T^2*TP)

-%e^-(t/T)*(T*TP*TR-T^3)/(T*((TP^2-2*T*TP+T^2)*TR^2

+(-2*T*TP^2+4*T^2*TP-2*T^3)*TR+T^2*TP^2

-2*T^3*TP+T^4))

+TP*%e^-(t/TP)/((TP^2-2*T*TP+T^2)*TR-TP^3+2*T*TP^2-T^2*TP)

-t*%e^-(t/T)/(T*((TP-T)*TR-T*TP+T^2))

h1(t) = − exp(−t/τZ)τZ

(τZ − τF)(τZ − τ)2

h2(t) = − exp(−t/τ)τFτZ − τ 2

(τF − τ)2(τZ − τ)2

h3(t) = exp(−t/τF)τF

(τF − τ)2(τZ − τF)

h4(t) = −t exp(−t/τ)1

ττFτZ − τ 2(τZ + τF) + τ 3

h(t) =aττZCf

(h1(t) + h2(t) + h3(t) + h4(t))




Shaper output waveform

(S-Z

)/ba

nana

(A)

[AD

C/m

V]

t [´µs]

2012-04-03-adc128pz-Bi207-16

"2012-04-03-adc128pz-Bi207-16S.2dhist"Fit

0

0.2

0.4

0.6

0.8

1

5 10 15 20 25 30 1

10

100

1000

10000




Further reading

I http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/

arm/i128/shaper2u2.pdf

I http://www.analog.com/en/high-speed-op-amps/

current-feedback-amplifiers/ad8005/products/product.html

I http://en.wikipedia.org/wiki/Laplace_transform

I http://maxima.sourceforge.net



http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/arm/i128/shaper2u2.pdf

http://www.ieap.uni-kiel.de/et/people/stephan/solo/eda/arm/i128/shaper2u2.pdf

http://www.analog.com/en/high-speed-op-amps/current-feedback-amplifiers/ad8005/products/product.html

http://www.analog.com/en/high-speed-op-amps/current-feedback-amplifiers/ad8005/products/product.html

http://en.wikipedia.org/wiki/Laplace_transform

http://maxima.sourceforge.net


Analog to Digital Converter

Analog to Digital Converter

I Important parametersI Types

I Flash ADCsI Successive approximation ADCsI Pipelined ADCs

I DACI ADC that we used here

I AD7276, 12-bit, 3 MSPS, irenaI ADC128S102, 12-bit, 1 MSPS, flightI AD9251, AD9649, 14-bit, 80 MSPS, erenaI AD7690, 18-bit, 400 kSPS, pirena




ADC parameters

I Resolution, number of output bits.

I Sample rate.

I Input range and format.

I Input multiplexer, track and hold.

I Output format, serial/parallel.

I Supply voltage, power consumption.

I Aperture jitter, aperture delay.

I Integral nonlinearity.

I Differential nonlinearity.




Differential nonlinearity

0.001

0.01

0.1

1

10

100

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

cps

SEPT E channel

fm/ecalib/m2_m2_pu_ramp

PDFE 0123




AD7276

C3220pF...560pF

R3

4k...10k

u1inv

u1out

C5

100n

c060

3

C4

100n

u1vss

u1vcc

3+

4−

1

5 VCC

2 VSS

AD8005U1

CFA

C1

1.4nF...10nF

in

R5

75

c060

3R

475

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TITLE

MSL RAD FEE Fast SHaper (FSH)$Revision: 890 $

$Author: stephan $

$Id: irena_ShaperADC.sch 890 2012−01−28 10:38:44Z stephan $

$Date: 2012−01−28 11:38:44 +0100 (Sa, 28 Jan 2012) $

irena_ShaperADC.sch

R3*C3 = 2.2us

R1*C1 = 2.2us, R1 located at csa output

in

Vcc

Vss

GND

8 Vin 2SDATA3nCS

6SCLK

7

GND

1

Vdd

AD7276MSOP8

U2

AD7276BRM

SDATA

C8

100n

Vdd

vadc

sdataSCLK

nCS

sclk

ncs

R7

51

C7

6n8

u2in

R2

220

u1fb

R1

zero

inz

R6

none

L: Gain 1 Shaper: R1*=1k5, C1=1n5 R3=4k7 C3=470pH: Gain 16 Shaper: R1*=220, C1=10n, R3=10k, C3=220p

R4, R5: replace by ferrit bead




ADC128S102

4 IN0

15DOUT

1nCS

16SCLK

12

DGND

2

VA

3

AGND

13

VD

14DIN

5 IN16 IN27 IN38 IN49 IN510 IN611 IN7ADC128S102CSOIC16

U2

A+3.3V D+3.3V

C9

C8

A+3.3V D+3.3V

IN0

IN1IN2IN3IN4IN5IN6IN7

DIN

VD

GND

VA

DOUT

nCS

SCLK

C3$C3

R3

$R3

u1inv

u1out

u1vssu1vcc

3+

4-

1

5 VCC

2 VSSAD8005

U1SOT23_5

CFA

C1$C1

L575

Ω

c060

3

L475

Ω

R7

51Ω

R2

220Ω

u1fb

inz

C7

6n8

C5

C4

VC

C

VE

E

u2in

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TITLE

$Id: heteptshadc.sch 1283 2012-10-08 15:12:26Z stephan $

$Date: 2012-10-08 17:12:26 +0200 (Mo, 08 Okt 2012) $

heteptshadc.sch $Revision: 1283 $

$Author: stephan $

C0$C0

R0

$R0

pz

parameter=C1:10nFparameter=R1:220Ω (on preamp board)

parameter=C3:220pFparameter=R3:10kΩ

parameter=R0:10kΩparameter=C0:220nF

Spaping time τ=2.2µsPole-Zero comp τr=100µsGain 16




AD9251, AD9649

FILE: REVISION:

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TITLE

8 +

1 − 4

3

VD

D

6 VS

S

2 CM

5 AD8138

U1MSOP8

GND

R550

R950

C1022p

U1out+

Vin+AVin−A

Vdd

Vss

Vss

Vdd

C19

C21

BVSS

BVDD

C20

C22

R3500U1in+

U1in−

U1out−

R6500

R1500

R4500

R2220

C4100n

C6100n

VIN−A

VIN+A

8 +

1 − 4

3

VD

D

6 VS

S

2 CM

5 AD8138

U2MSOP8

R1250

R1450

C1122p

U2out+

Vin−B

Vdd

Vss

R10500

U2in+

U2in−

U2out−

R7500

R11500

R8220

C7100n

C9100n

VIN+B

VIN−B

Vin+B

500R13

VCMC23

AVDD

+3.3V

AVDD:1

DR

VD

D

AVDD:1

+3.3V

C1 C2 C3 C5

C14 C15 C16 C17

+3.3V

+3.3V

+3.3V

PD

WN

OE

BC

SB

SC

LKS

DIO

OR

AD

13AD

12AD

11AD

10AD

9A

D8A

D7A

D6A

D5A

D4A

D3A

D2A

D1A

D0A

DC

OA

SY

NC

CLK−CLK+ 100

R16

RR3

BCN1633

OR

AD

13A

D12

AD

11A

D10

AD

9A

D8A

D7A

D6A

D5A

DCOA

D0A

RR2

BCN1633

RR1

BCN1633

RR4

BCN1633

RR5

BCN1633

C12

VREF

12

C13

10u p1206

D4AD3AD2AD1A

R15

10k

RBIAS

in out

GN

Dsd X1

LDO+8.sch

12

C18

10u p1206

L1

C8

12

C24

10u p1206

1C

LK+

2C

LK−

3S

YN

C4

NC

5N

C6

D0B

7D

1B8

D2B

9D

3B10

DR

VD

D11

D4B

12D

5B13

D6B

14D

7B15

D8B

16D

9B

17D10B18D11B19DRVDD20D12B21D13B22ORB23DCOB24DCOA25NC26NC27D0A28DRVDD29D1A30D2A31D3A32D4A33D

5A34D

6A35D

7A36D

8A37D

RV

DD

38D9A

39D10A

40D11A

41D12A

42D13A

43OR

A44S

DIO

45SC

LK46C

SB

47OE

B48P

DW

N

49AVDD50AVDD51VIN+A52VIN−A53AVDD54AVDD55VREF56SENSE57VCM58RBIAS59AVDD60AVDD61VIN−B62VIN+B63AVDD64AVDD

U3

AD9251

Dual 14−bit ADC

LFCSP_VQ

GND:0

C25

C26

clk+

clk−




AD7690

FILE: REVISION:

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TITLE $Id: pirena-adc.sch 1182 2012-07-26 06:57:55Z stephan $

PIRENA ADCdriver and 18-bit, 400kSPS ADC

$Revision: 1182 $

Stephan I. Böttcher

pirena-adc.sch

8 +

1 - 4

3

VD

D

6 VS

S

2 CM

5 AD8138

U1MSOP8

R7560

R8560

U1out+

Vin+

Vin-

Vdd

Vss

Vss

Vdd

C10

C11

VSS

VDD

R5

22k

U1in+

U1in-

U1out-

R31kΩ

R41kΩ

IN-

IN+

VCM

Vref

C3

R15k6

in out

GN

DX1

LDO+1.sch

GND

3 IN+ 7SDO

8SCK

5

GND

2

Vdd

4 IN-

1 REF

6CNV

9SDI

10

Vio

MSOP10

U2

AD7690

R11

10

U2v

dd

C8

12

C13

10u p1206

R9

1kΩ

R10

1kΩ

C433p

U1fb+

C533p

U1fb-

C6220p

C1100p

R6

22k

C2100p

R25k6

C7220p

SCKSDO

CNV

C9

VD

DIO

12

C12

10u p1206

VDDA

R1,R2 additional 5k6 at the source

2012-07-25: R9, R10 changed from 10kΩ to 1kΩ.The VOCM input current was shifting VCM by about 140mV when 10kΩ resistors are used.

2012-07-25: R3, R4 changed from 4.7kΩ to 1kΩ.The board populated in Potsdam came with 1kΩ.




Further reading

I http://www.analog.com/static/imported-files/data_

sheets/AD7276_7277_7278.pdf

I http://cache.national.com/ds/DC/ADC128S102.pdf


sheets/AD9251.pdf


sheets/AD9649.pdf

I http://www.analog.com/static/imported-files/Data_

Sheets/AD7690.pdf



http://www.analog.com/static/imported-files/data_sheets/AD7276_7277_7278.pdf

http://www.analog.com/static/imported-files/data_sheets/AD7276_7277_7278.pdf

http://cache.national.com/ds/DC/ADC128S102.pdf

http://www.analog.com/static/imported-files/data_sheets/AD9251.pdf




http://www.analog.com/static/imported-files/Data_Sheets/AD7690.pdf

http://www.analog.com/static/imported-files/Data_Sheets/AD7690.pdf


Field Programmable Gate Arrays

I Notations

I Boolean algebra

I Signaling: TTL, CMOS, LVDS, PECL

I Logic gate yechnology: TTL, CMOS

I flip-flops

I Counter: ripple, synchronous

I Karnaugh-Veitch (KV) diagrams

I FPGA logic cell




Logic Notations

Math false true ¬a a ∧ b a ∨ b a 6= b

0 1 a a · b a + b

Python False True not and or

C 0 1 ! && ||C bitwise 0 -1 ˜ & | ˆ

ANSI L H

DIN L HTable A Q

0 11 0

A B Q0 0 00 1 01 0 01 1 1

A B Q0 0 00 1 11 0 11 1 1

A B Q0 0 00 1 11 0 11 1 0




Boolean Algebra

Commutativity a·b = b·a a+b = b+aAssociativity a·(b·c) = (a·b)·c a+(b+c) = (a+b)+cDistributivity a·(b+c) = (a·b)+(a·c) a+(b·c) = (a+b)·(a+c)Identity a·1 = a a+0 = aAnnihilation a·0 = 0 a+1 = 1Idempotence a·a = a a+a = aAbsorption a·(a+b) = a a+(a·b) = a

Complementation a·a = 0 a+a = 1

Double negation a = a

De Morgan a·b = a+b a+b = a·bDuality 1 = 0 0 = 1




TTL




Logic Design with Verilog Hardware Description Language

I Module definition

I Module instances

I Module Parameters

I Signals, wire, assign

I reg, always, nonblocking assignment

I Simulation, Testbenches

I initial

I Verilog Change Dump (vcd, lxt)




Module Definition

A Verilog module defines a logic circuit or subcircuit. The moduledefinition syntax is basically

I the keyword module

I a module name

I port declarations

I the module body

I the keyword endmodule

The ports are the inputs and outputs of the module. Moduleswithout ports are toplevel modules for simulation. The ports of thetoplevel module for the target design are the actual input andoutputs of the chip/FPGA.




Module Definition

module mux4

(

input clk,

input sel,

input [3:0] a,

input [3:0] b,

output reg [3:0] qs,

output [3:0] qa

);

assign qa = sel ? a : b;

always @(posedge clk)

qs <= qa;

endmodule




Module Instances

Modules can be instantiated inside higher level modules. Therecan be multiple instances. Each instance needs a name which mustbe unique among the items defined in the enclosing module body.The ports of a module instance can be connected to signalsdefined earlier in the enclosing module body, including ports of theenclosing module. Inputs can be connected to any signal, outputsmust be connected to wires, not registers. A port need not beconnected. If a port is connected to an undefined name, or a namethat is defined later in the module body, a wire of that name isautomatically defined, which can lead to confusing error messages,don’t do that.There are multiple syntactic ways to declare and connect ports.The syntax presented here is more verbose but easier to read thanthe alternative.




Module Instances

module mux8

(

input clk,

input sel,

input [7:0] a,

input [7:0] b,

output [7:0] q

);

mux4 muxlo( .clk(clk),

.sel(sel), .a(a[3:0]), .b(b[3:0]),

.qs(q[3:0]) );

mux4 muxhi( .clk(clk),

.sel(sel), .a(a[7:4]), .b(b[7:4]),

.qs(q[7:4]) );

endmoduleStephan I. Bottcher IEAP, CAU Kiel



Module Parameters

Module can have parameters that are evaluated during theelaboration of the Verilog code by the compiler. The parametersare constants for each instance of the module, but differentinstances can have different values for the parameters.Again, there are different syntax available both to declareparameters for a module and to set the value of a parameter for amodule instance. The syntax presented here is the only one that issupported by all Verilog compilers we use.




Module Parameters

module mux #(parameter N=4)

(

input clk,

input sel,

input [N-1:0] a,

input [N-1:0] b,

output reg [N-1:0] q

);


q <= sel ? a : b;

endmodule




Module Parameters

module mux8

(

input clk,

input sel,

input [7:0] a,

input [7:0] b,

output [7:0] q

);

mux #(.N(8)) m( .clk(clk),

.sel(sel), .a(a), .b(b),

.q(q) );

endmodule




Signals, wires, assign

A signal can be a single bit, or multiple bits that form a number ora bus of logic signals. Signals are either wires or registers. Moduleports are signals, output ports can be registers.A wire is a signal that can be connected to output ports of amodule instance or assigned to a logic expression of other signals.Each bit in a signal carries a logic state that can have four differentvalues: 0 (false), 1 (true), x (unknown), or z (high impedance).A wire can be connected to multiple drivers. If different values(not z) are driven on a wire the resulting value is x (unknown). Ifall drivers are z (high impedance) an expression that depends onthe signal may become x (undefined).An assignment to a wire may be written as part of the wiredeclaration or with a separate assign statement. The state of thewire changes whenever the value of the assigned expressionchanges.




Signals, wires, assign

module switch #(parameter N=4)

(input en, input [N-1:0] a, output [N-1:0] q);

assign q = en ? a : N1’b z;

endmodule

module mux #(parameter N=4)

( input clk, input sel,

input [N-1:0] a, input [N-1:0] b,

output reg [N-1:0] q );

wire [N-1:0] qq;

switch #(.N(N)) sa(.en(sel), .a(a), .q(qq) );

switch #(.N(N)) sb(.en(~sel), .a(b), .q(qq) );


q <= qq;




reg, always, nonblocking assignment

A register is a signal that changes its state whenever a new value isassigned to it in an always or initial block. These blocks aresequences of commands.An initial block is executed once at the beginning of asimulation. This cannot be used to describe a circuit. It may beused to define the power-on state of a register with some tools.An always block is executed in an infinite loop. A block can (andshould) include statements that wait for certain events. The onlysynthesizable thing to wait for is for some signal to change.always blocks can describe combinatorial logic or sequencial logic,i.e., flip-flops. A combinatorial block will wait for some signals tochange and then do a blocking assignment to a register, evaluatedfrom those signals.A sequencial block will wait for a clock edge, and then performnon-blocking assignements to registers.





Blocking assignments (=) are executed immediately, and allexpressions that drive wires and depend of the assigned registerwill change state at that moment in the simulation. This can beused to describe combinatorial logic, where the output dependsonly on the state of the inputs.Non-blocking assignments (<=) are queued at the end of the list ofthings to execute at the current simulation time. The same listincludes all blocks that were waiting for some event that justhappened. When a clock edge occurs, all always blocks that wherewaiting for that clock edge are queued up for execution. Duringexecution, these always blocks queue up assignments to registers.These assignments will be executed after all always blocks wereexecuted, so all always blocks see the old values of all thoseregisters before they change. This is exactly how a synchronouscircuit is supposed to work. The registers represent the flip-flops.





module switch #(parameter N=4)

( input en,

input [N-1:0] a,

output [N-1:0] q

);

reg [N-1:0] qq;

always @(en or a)

if (en)

qq = a;

else

qq = ’bz;

assign q = qq;

endmodule





module counter #(parameter N=8, TC=100)

( input clk,

input reset,

input enable,

output [N-1:0] q

);

reg [N-1:0] c;


if (reset)

c <= 0;

else if (enable & c < TC)

c <= c + 1;

assign q = c;




Simulation, Testbenches

‘timescale 1ns/1ps

module mux_test;

reg clk, sel;

reg [7:0] a, b;

wire [7:0] q;

mux8 dut(.clk(clk), .sel(sel), .a(a), .b(b), .q(q));


$display("%5d: sel=%d a=%h b=%h q=%b", $time, sel, a, b, q);

initial begin

$dumpfile("mux8.lxt");

$dumpvars(0);

clk =0; a=8’h 12; b=8’h 34;

#10 clk=1; #10 clk=0; sel=1;

#10 clk=1; #10 clk=0; sel=0;

#10 clk=1; #10 clk=0; sel=1;

#10 clk=1; #10 clk=0; sel=’bz;

#10 clk=1; #10 clk=0;

#10 clk=1; #10 clk=0;

end




Simulation, Testbenches

$ iverilog mux8_test.v mux4.v mux4_8.v -o mux.vvp

$ ./mux.vvp -lxt2

LXT2 info: dumpfile mux8.lxt opened for output.

10: sel=x a=12 b=34 q=xxxxxxxx

30: sel=1 a=12 b=34 q=00x10xx0

50: sel=0 a=12 b=34 q=00010010

70: sel=1 a=12 b=34 q=00110100

90: sel=z a=12 b=34 q=00010010

110: sel=z a=12 b=34 q=00x10xx0

$ iverilog mux8_test.v mux.v muxp_8.v -o mux.vvp

$ iverilog mux8_test.v muxsw.v muxp_8.v -o mux.vvp

$ ./mux.vvp -lxt2

LXT2 info: dumpfile mux8.lxt opened for output.

10: sel=x a=12 b=34 q=xxxxxxxx

30: sel=1 a=12 b=34 q=xxxxxxxx

50: sel=0 a=12 b=34 q=00010010

70: sel=1 a=12 b=34 q=00110100

90: sel=z a=12 b=34 q=00010010

110: sel=z a=12 b=34 q=xxxxxxxx

$ gtkwave mux8.lxtStephan I. Bottcher IEAP, CAU Kiel



Resources

AD 7276ADC, 12-bit, 3 MSPS, serial output, small package.

I 48 MHz ADC clock – 96 MHz main clock.

EP2C8T144FPGA, small, easy package, 144 pin.

I 18 embedded multipliers – 18 channels.I 36 embedded RAM blocks – 1 block per

channel, plus FIFOs.




Algorithm

I Store the new sample S0.

I Compute

A =15∑i=0

aiSni

B =15∑i=0

biSni

I Deliver SQ for sample readout.




Algorithm

In 32 clock cycles, we need to do 32 multiplications, read 16samples Sni , SQ and 16 sets of coefficients ai , bi , ni from theRAM, and write one sample S0.

With implicit n0 = 0. I.e., the first sample is always S0, which neednot be read from the RAM. The read slot for S0 is used to readSQ , and the storage for the coefficient n0 = Q is used to tell howfar back in time the sample readout shall happen.

The RAM is 128 words deep, by 32 bits. Coefficients are stored inthe even addresses, the samples in the odd addresses. Coefficientswaste 3/4 of the addresses, the samples leave 20 bits unused.There is space for 64 samples, that is how far back in time theanalysis can go.



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