ise10.1 guideforschematicdesigns spartan-iiandspartan ...larry.aamodt/engr433/... · 16 10.1....
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Spartan-II and Spartan-IIE LibrariesGuide for Schematic Designs
ISE 10.1
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Table of ContentsAbout this Guide ........................................................................................................................................ 11Functional Categories ................................................................................................................................. 13About Design Elements............................................................................................................................... 29
ACC16 ................................................................................................................................................ 30ACC4.................................................................................................................................................. 32ACC8.................................................................................................................................................. 34ADD16................................................................................................................................................ 36ADD4 ................................................................................................................................................. 38ADD8 ................................................................................................................................................. 40ADSU16 .............................................................................................................................................. 42ADSU4................................................................................................................................................ 44ADSU8................................................................................................................................................ 46AND12................................................................................................................................................ 48AND16................................................................................................................................................ 49AND2 ................................................................................................................................................. 50AND2B1.............................................................................................................................................. 51AND2B2.............................................................................................................................................. 52AND3 ................................................................................................................................................. 53AND3B1.............................................................................................................................................. 54AND3B2.............................................................................................................................................. 55AND3B3.............................................................................................................................................. 56AND4 ................................................................................................................................................. 57AND4B1.............................................................................................................................................. 58AND4B2.............................................................................................................................................. 59AND4B3.............................................................................................................................................. 60AND4B4.............................................................................................................................................. 61AND5 ................................................................................................................................................. 62AND5B1.............................................................................................................................................. 63AND5B2.............................................................................................................................................. 64AND5B3.............................................................................................................................................. 65AND5B4.............................................................................................................................................. 66AND5B5.............................................................................................................................................. 67AND6 ................................................................................................................................................. 68AND7 ................................................................................................................................................. 69AND8 ................................................................................................................................................. 70AND9 ................................................................................................................................................. 71BRLSHFT4 .......................................................................................................................................... 72BRLSHFT8 .......................................................................................................................................... 73BSCAN_SPARTAN2 ............................................................................................................................ 75BUF .................................................................................................................................................... 76BUFCF ................................................................................................................................................ 77BUFE .................................................................................................................................................. 78BUFE16 ............................................................................................................................................... 79BUFE4................................................................................................................................................. 80BUFE8................................................................................................................................................. 81BUFG.................................................................................................................................................. 82BUFGDLL ........................................................................................................................................... 83BUFGP................................................................................................................................................ 84BUFT .................................................................................................................................................. 85BUFT16 ............................................................................................................................................... 86BUFT4................................................................................................................................................. 88BUFT8................................................................................................................................................. 90CAPTURE_SPARTAN2 ........................................................................................................................ 92CB16CE............................................................................................................................................... 93CB16CLE............................................................................................................................................. 95CB16CLED .......................................................................................................................................... 97
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CB16RE............................................................................................................................................... 99CB2CE ............................................................................................................................................... 101CB2CLE ............................................................................................................................................. 103CB2CLED........................................................................................................................................... 105CB2RE................................................................................................................................................ 107CB4CE ............................................................................................................................................... 109CB4CLE ............................................................................................................................................. 111CB4CLED........................................................................................................................................... 113CB4RE................................................................................................................................................ 115CB8CE ............................................................................................................................................... 117CB8CLE ............................................................................................................................................. 119CB8CLED........................................................................................................................................... 121CB8RE................................................................................................................................................ 123CC16CE ............................................................................................................................................. 125CC16CLE ........................................................................................................................................... 127CC16CLED......................................................................................................................................... 129CC16RE.............................................................................................................................................. 131CC8CE ............................................................................................................................................... 133CC8CLE ............................................................................................................................................. 135CC8CLED .......................................................................................................................................... 137CC8RE ............................................................................................................................................... 139CD4CE............................................................................................................................................... 141CD4CLE............................................................................................................................................. 143CD4RE ............................................................................................................................................... 145CD4RLE............................................................................................................................................. 147CJ4CE ................................................................................................................................................ 149CJ4RE ................................................................................................................................................ 150CJ5CE ................................................................................................................................................ 151CJ5RE ................................................................................................................................................ 152CJ8CE ................................................................................................................................................ 153CJ8RE ................................................................................................................................................ 154CLKDLL ............................................................................................................................................ 155CLKDLLE .......................................................................................................................................... 157CLKDLLHF........................................................................................................................................ 159COMP16 ............................................................................................................................................ 161COMP2 .............................................................................................................................................. 162COMP4 .............................................................................................................................................. 163COMP8 .............................................................................................................................................. 164COMPM16 ......................................................................................................................................... 165COMPM2........................................................................................................................................... 167COMPM4........................................................................................................................................... 168COMPM8........................................................................................................................................... 169COMPMC16....................................................................................................................................... 171COMPMC8 ........................................................................................................................................ 173CR16CE.............................................................................................................................................. 175CR8CE ............................................................................................................................................... 176D2_4E ................................................................................................................................................ 177D3_8E ................................................................................................................................................ 178D4_16E............................................................................................................................................... 179DEC_CC16 ......................................................................................................................................... 180DEC_CC4........................................................................................................................................... 182DEC_CC8........................................................................................................................................... 183DECODE16 ........................................................................................................................................ 184DECODE32 ........................................................................................................................................ 185DECODE4 .......................................................................................................................................... 186DECODE64 ........................................................................................................................................ 187DECODE8 .......................................................................................................................................... 188FD ..................................................................................................................................................... 189FD_1 .................................................................................................................................................. 190
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FD16CE.............................................................................................................................................. 191FD16RE.............................................................................................................................................. 192FD4CE ............................................................................................................................................... 193FD4RE ............................................................................................................................................... 195FD8CE ............................................................................................................................................... 197FD8RE ............................................................................................................................................... 198FDC ................................................................................................................................................... 199FDC_1................................................................................................................................................ 200FDCE ................................................................................................................................................. 201FDCE_1.............................................................................................................................................. 202FDCP ................................................................................................................................................. 203FDCP_1.............................................................................................................................................. 205FDCPE ............................................................................................................................................... 206FDCPE_1............................................................................................................................................ 209FDE ................................................................................................................................................... 211FDE_1 ................................................................................................................................................ 212FDP ................................................................................................................................................... 213FDP_1 ................................................................................................................................................ 215FDPE ................................................................................................................................................. 216FDPE_1 .............................................................................................................................................. 217FDR ................................................................................................................................................... 218FDR_1................................................................................................................................................ 219FDRE ................................................................................................................................................. 220FDRE_1.............................................................................................................................................. 221FDRS ................................................................................................................................................. 222FDRS_1 .............................................................................................................................................. 224FDRSE ............................................................................................................................................... 225FDRSE_1 ............................................................................................................................................ 227FDS.................................................................................................................................................... 229FDS_1 ................................................................................................................................................ 230FDSE.................................................................................................................................................. 231FDSE_1 .............................................................................................................................................. 233FJKC .................................................................................................................................................. 234FJKCE ................................................................................................................................................ 235FJKP .................................................................................................................................................. 236FJKPE ................................................................................................................................................ 237FJKRSE .............................................................................................................................................. 238FJKSRE .............................................................................................................................................. 240FMAP ................................................................................................................................................ 242FTC.................................................................................................................................................... 243FTCE.................................................................................................................................................. 244FTCLE ............................................................................................................................................... 245FTCLEX ............................................................................................................................................. 246FTP .................................................................................................................................................... 247FTPE.................................................................................................................................................. 248FTPLE................................................................................................................................................ 249FTRSE ................................................................................................................................................ 250FTRSLE.............................................................................................................................................. 251FTSRE................................................................................................................................................ 253FTSRLE.............................................................................................................................................. 254GND.................................................................................................................................................. 256IBUF .................................................................................................................................................. 257IBUF16 ............................................................................................................................................... 259IBUF4................................................................................................................................................. 260IBUF8................................................................................................................................................. 261IBUFG................................................................................................................................................ 262IFD .................................................................................................................................................... 263IFD_1 ................................................................................................................................................. 264IFD16 ................................................................................................................................................. 265
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IFD4................................................................................................................................................... 266IFD8................................................................................................................................................... 267IFDI ................................................................................................................................................... 268IFDI_1................................................................................................................................................ 269IFDX .................................................................................................................................................. 270IFDX_1............................................................................................................................................... 271IFDX16............................................................................................................................................... 272IFDX4 ................................................................................................................................................ 273IFDX8 ................................................................................................................................................ 274IFDXI ................................................................................................................................................. 275IFDXI_1.............................................................................................................................................. 276ILD .................................................................................................................................................... 277ILD_1................................................................................................................................................. 278ILD16................................................................................................................................................. 279ILD4 .................................................................................................................................................. 280ILD8 .................................................................................................................................................. 281ILDI ................................................................................................................................................... 282ILDI_1................................................................................................................................................ 283ILDX.................................................................................................................................................. 284ILDX_1............................................................................................................................................... 285ILDX16............................................................................................................................................... 286ILDX4 ................................................................................................................................................ 287ILDX8 ................................................................................................................................................ 288ILDXI................................................................................................................................................. 289ILDXI_1 ............................................................................................................................................. 290INV.................................................................................................................................................... 291INV16 ................................................................................................................................................ 292INV4.................................................................................................................................................. 293INV8.................................................................................................................................................. 294IOBUF................................................................................................................................................ 295KEEPER ............................................................................................................................................. 297LD ..................................................................................................................................................... 298LD_1.................................................................................................................................................. 299LD16.................................................................................................................................................. 300LD16CE ............................................................................................................................................. 301LD4.................................................................................................................................................... 303LD4CE ............................................................................................................................................... 304LD8.................................................................................................................................................... 306LD8CE ............................................................................................................................................... 307LDC................................................................................................................................................... 309LDC_1................................................................................................................................................ 310LDCE................................................................................................................................................. 311LDCE_1 ............................................................................................................................................. 312LDCP................................................................................................................................................. 314LDCP_1.............................................................................................................................................. 316LDCPE............................................................................................................................................... 318LDCPE_1 ........................................................................................................................................... 320LDE ................................................................................................................................................... 322LDE_1................................................................................................................................................ 323LDP ................................................................................................................................................... 324LDP_1................................................................................................................................................ 325LDPE ................................................................................................................................................. 326LDPE_1.............................................................................................................................................. 327LUT1 ................................................................................................................................................. 329LUT1_D ............................................................................................................................................. 331LUT1_L.............................................................................................................................................. 333LUT2 ................................................................................................................................................. 335LUT2_D ............................................................................................................................................. 337LUT2_L.............................................................................................................................................. 339
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LUT3 ................................................................................................................................................. 341LUT3_D ............................................................................................................................................. 343LUT3_L.............................................................................................................................................. 345LUT4 ................................................................................................................................................. 347LUT4_D ............................................................................................................................................. 349LUT4_L.............................................................................................................................................. 351M16_1E .............................................................................................................................................. 353M2_1.................................................................................................................................................. 355M2_1B1 .............................................................................................................................................. 356M2_1B2 .............................................................................................................................................. 357M2_1E................................................................................................................................................ 358M4_1E................................................................................................................................................ 359M8_1E................................................................................................................................................ 360MULT_AND....................................................................................................................................... 362MUXCY ............................................................................................................................................. 363MUXCY_D ......................................................................................................................................... 364MUXCY_L.......................................................................................................................................... 365MUXF5 .............................................................................................................................................. 366MUXF5_D .......................................................................................................................................... 367MUXF5_L........................................................................................................................................... 368MUXF6 .............................................................................................................................................. 369MUXF6_D .......................................................................................................................................... 370MUXF6_L........................................................................................................................................... 371NAND12............................................................................................................................................ 372NAND16............................................................................................................................................ 373NAND2 ............................................................................................................................................. 374NAND2B1.......................................................................................................................................... 375NAND2B2.......................................................................................................................................... 376NAND3 ............................................................................................................................................. 377NAND3B1.......................................................................................................................................... 378NAND3B2.......................................................................................................................................... 379NAND3B3.......................................................................................................................................... 380NAND4 ............................................................................................................................................. 381NAND4B1.......................................................................................................................................... 382NAND4B2.......................................................................................................................................... 383NAND4B3.......................................................................................................................................... 384NAND4B4.......................................................................................................................................... 385NAND5 ............................................................................................................................................. 386NAND5B1.......................................................................................................................................... 387NAND5B2.......................................................................................................................................... 388NAND5B3.......................................................................................................................................... 389NAND5B4.......................................................................................................................................... 390NAND5B5.......................................................................................................................................... 391NAND6 ............................................................................................................................................. 392NAND7 ............................................................................................................................................. 393NAND8 ............................................................................................................................................. 394NAND9 ............................................................................................................................................. 395NOR12............................................................................................................................................... 396NOR16............................................................................................................................................... 397NOR2................................................................................................................................................. 398NOR2B1............................................................................................................................................. 399NOR2B2............................................................................................................................................. 400NOR3................................................................................................................................................. 401NOR3B1............................................................................................................................................. 402NOR3B2............................................................................................................................................. 403NOR3B3............................................................................................................................................. 404NOR4................................................................................................................................................. 405NOR4B1............................................................................................................................................. 406NOR4B2............................................................................................................................................. 407
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NOR4B3............................................................................................................................................. 408NOR4B4............................................................................................................................................. 409NOR5................................................................................................................................................. 410NOR5B1............................................................................................................................................. 411NOR5B2............................................................................................................................................. 412NOR5B3............................................................................................................................................. 413NOR5B4............................................................................................................................................. 414NOR5B5............................................................................................................................................. 415NOR6................................................................................................................................................. 416NOR7................................................................................................................................................. 417NOR8................................................................................................................................................. 418NOR9................................................................................................................................................. 419OBUF................................................................................................................................................. 420OBUF16 ............................................................................................................................................. 421OBUF4 ............................................................................................................................................... 422OBUF8 ............................................................................................................................................... 423OBUFE............................................................................................................................................... 424OBUFE16 ........................................................................................................................................... 425OBUFE4 ............................................................................................................................................. 426OBUFE8 ............................................................................................................................................. 427OBUFT............................................................................................................................................... 428OBUFT16 ........................................................................................................................................... 430OBUFT4 ............................................................................................................................................. 431OBUFT8 ............................................................................................................................................. 433OFD................................................................................................................................................... 434OFD_1 ............................................................................................................................................... 435OFD16 ............................................................................................................................................... 436OFD4 ................................................................................................................................................. 437OFD8 ................................................................................................................................................. 438OFDE................................................................................................................................................. 439OFDE_1 ............................................................................................................................................. 440OFDE16 ............................................................................................................................................. 441OFDE4 ............................................................................................................................................... 442OFDE8 ............................................................................................................................................... 443OFDI.................................................................................................................................................. 444OFDI_1 .............................................................................................................................................. 445OFDT................................................................................................................................................. 446OFDT_1 ............................................................................................................................................. 447OFDT16 ............................................................................................................................................. 448OFDT4 ............................................................................................................................................... 449OFDT8 ............................................................................................................................................... 450OFDX................................................................................................................................................. 451OFDX_1 ............................................................................................................................................. 452OFDX16 ............................................................................................................................................. 453OFDX4............................................................................................................................................... 454OFDX8............................................................................................................................................... 455OFDXI ............................................................................................................................................... 456OFDXI_1 ............................................................................................................................................ 457OR12.................................................................................................................................................. 458OR16.................................................................................................................................................. 459OR2 ................................................................................................................................................... 460OR2B1................................................................................................................................................ 461OR2B2................................................................................................................................................ 462OR3 ................................................................................................................................................... 463OR3B1................................................................................................................................................ 464OR3B2................................................................................................................................................ 465OR3B3................................................................................................................................................ 466OR4 ................................................................................................................................................... 467OR4B1................................................................................................................................................ 468
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OR4B2................................................................................................................................................ 469OR4B3................................................................................................................................................ 470OR4B4................................................................................................................................................ 471OR5 ................................................................................................................................................... 472OR5B1................................................................................................................................................ 473OR5B2................................................................................................................................................ 474OR5B3................................................................................................................................................ 475OR5B4................................................................................................................................................ 476OR5B5................................................................................................................................................ 477OR6 ................................................................................................................................................... 478OR7 ................................................................................................................................................... 479OR8 ................................................................................................................................................... 480OR9 ................................................................................................................................................... 481PULLDOWN...................................................................................................................................... 482PULLUP............................................................................................................................................. 483RAM16X1D ........................................................................................................................................ 484RAM16X1D_1..................................................................................................................................... 486RAM16X1S......................................................................................................................................... 488RAM16X1S_1...................................................................................................................................... 490RAM16X2D ........................................................................................................................................ 492RAM16X2S......................................................................................................................................... 494RAM16X4D ........................................................................................................................................ 496RAM16X4S......................................................................................................................................... 498RAM16X8D ........................................................................................................................................ 500RAM16X8S......................................................................................................................................... 502RAM32X1S......................................................................................................................................... 504RAM32X1S_1...................................................................................................................................... 506RAM32X2S......................................................................................................................................... 508RAM32X4S......................................................................................................................................... 510RAM32X8S......................................................................................................................................... 512RAMB4_S1 ......................................................................................................................................... 514RAMB4_S1_S1 .................................................................................................................................... 516RAMB4_S1_S16 .................................................................................................................................. 518RAMB4_S1_S2 .................................................................................................................................... 520RAMB4_S1_S4 .................................................................................................................................... 524RAMB4_S1_S8 .................................................................................................................................... 526RAMB4_S16 ....................................................................................................................................... 528RAMB4_S16_S16................................................................................................................................. 530RAMB4_S2 ......................................................................................................................................... 532RAMB4_S2_S16 .................................................................................................................................. 534RAMB4_S2_S2 .................................................................................................................................... 537RAMB4_S2_S4 .................................................................................................................................... 539RAMB4_S2_S8 .................................................................................................................................... 541RAMB4_S4 ......................................................................................................................................... 543RAMB4_S4_S16 .................................................................................................................................. 545RAMB4_S4_S4 .................................................................................................................................... 548RAMB4_S4_S8 .................................................................................................................................... 551RAMB4_S8 ......................................................................................................................................... 553RAMB4_S8_S16 .................................................................................................................................. 555RAMB4_S8_S8 .................................................................................................................................... 558ROM16X1........................................................................................................................................... 561ROM32X1........................................................................................................................................... 563SOP3.................................................................................................................................................. 565SOP3B1A ........................................................................................................................................... 566SOP3B1B ............................................................................................................................................ 567SOP3B2A ........................................................................................................................................... 568SOP3B2B ............................................................................................................................................ 569SOP3B3 .............................................................................................................................................. 570SOP4.................................................................................................................................................. 571
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SOP4B1 .............................................................................................................................................. 572SOP4B2A ........................................................................................................................................... 573SOP4B2B ............................................................................................................................................ 574SOP4B3 .............................................................................................................................................. 575SOP4B4 .............................................................................................................................................. 576SR16CE .............................................................................................................................................. 577SR16CLE ............................................................................................................................................ 579SR16CLED.......................................................................................................................................... 581SR16RE .............................................................................................................................................. 583SR16RLE ............................................................................................................................................ 585SR16RLED.......................................................................................................................................... 587SR4CE................................................................................................................................................ 589SR4CLE.............................................................................................................................................. 591SR4CLED ........................................................................................................................................... 593SR4RE................................................................................................................................................ 595SR4RLE.............................................................................................................................................. 597SR4RLED ........................................................................................................................................... 599SR8CE................................................................................................................................................ 601SR8CLE.............................................................................................................................................. 603SR8CLED ........................................................................................................................................... 605SR8RE................................................................................................................................................ 607SR8RLE.............................................................................................................................................. 609SR8RLED ........................................................................................................................................... 611SRL16 ................................................................................................................................................ 613SRL16_1 ............................................................................................................................................. 615SRL16E .............................................................................................................................................. 617SRL16E_1 ........................................................................................................................................... 619STARTBUF_SPARTAN2 ...................................................................................................................... 621STARTUP_SPARTAN2........................................................................................................................ 622VCC................................................................................................................................................... 623XNOR2 .............................................................................................................................................. 624XNOR3 .............................................................................................................................................. 625XNOR4 .............................................................................................................................................. 626XNOR5 .............................................................................................................................................. 627XNOR6 .............................................................................................................................................. 628XNOR7 .............................................................................................................................................. 629XNOR8 .............................................................................................................................................. 630XNOR9 .............................................................................................................................................. 631XOR2 ................................................................................................................................................. 632XOR3 ................................................................................................................................................. 633XOR4 ................................................................................................................................................. 634XOR5 ................................................................................................................................................. 635XOR6 ................................................................................................................................................. 636XOR7 ................................................................................................................................................. 637XOR8 ................................................................................................................................................. 638XOR9 ................................................................................................................................................. 639XORCY .............................................................................................................................................. 640XORCY_D.......................................................................................................................................... 641XORCY_L .......................................................................................................................................... 642
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About this GuideThis HDL guide is part of the ISE documentation collection. A separate version of this guide is available if youprefer to work with schematics.
This guide contains the following:
• Introduction.
• A list of design elements supported in this architecture, organized by functional categories.
• Individual descriptions of each available primitive.
About Design ElementsThis version of the Libraries Guide describes design elements available for this architecture. There are severalcategories of design elements:
• Primitives - The simplest design elements in the Xilinx libraries. Primitives are the design element "atoms."Examples of Xilinx primitives are the simple buffer, BUF, and the D flip-flop with clock enable and clear,FDCE.
• Macros - The design element "molecules" of the Xilinx libraries. Macros can be created from the designelement primitives or macros. For example, the FD4CE flip-flop macro is a composite of 4 FDCE primitives.
Xilinx maintains software libraries with hundreds of functional design elements (macros and primitives) fordifferent device architectures. New functional elements are assembled with each release of development systemsoftware. This guide is one in a series of architecture-specific libraries.
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Functional CategoriesThis section categorizes, by function, the circuit design elements described in detail later in this guide. Theelements (primitives and macros) are listed in alphanumeric order under each functional category.
Arithmetic General Map
Buffer IO Memory
Carry Logic IO FlipFlop Mux
Comparator IO Latch Shift Register
Counter Latch Shifter
Decoder Logic Spartan2E Components
Flip Flop LUT
ArithmeticDesign Element Description
ACC16 Macro: 16-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, andSynchronous Reset
ACC4 Macro: 4-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, andSynchronous Reset
ACC8 Macro: 8-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, andSynchronous Reset
ADD16 Macro: 16-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow
ADD4 Macro: 4-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow
ADD8 Macro: 8-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow
ADSU16 Macro: 16-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow
ADSU4 Macro: 4-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow
ADSU8 Macro: 8-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow
BufferDesign Element Description
BUF Primitive: General Purpose Buffer
BUFCF Primitive: Fast Connect Buffer
BUFE Primitive: Internal 3-State Buffer with Active High Enable
BUFE16 Macro: 16-Bit Internal 3-State Buffer with Active High Enable
BUFE4 Macro: 4-BitInternal 3-State Buffer with Active High Enable
BUFE8 Macro: 8-Bit Internal 3-State Buffer with Active High Enable
BUFG Primitive: Global Clock Buffer
BUFGP Primitive: Primary Global Buffer for Driving Clocks or Longlines (Four per PLDDevice)
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Functional Categories
Design Element Description
BUFT Primitive: Internal 3-State Buffer with Active Low Enable
BUFT16 Macro: 16-Bit Internal 3-State Buffers with Active Low Enable
BUFT4 Macro: 4-Bit Internal 3-State Buffers with Active Low Enable
BUFT8 Macro: 8-Bit Internal 3-State Buffers with Active Low Enable
Carry LogicDesign Element Description
MUXCY Primitive: 2-to-1 Multiplexer for Carry Logic with General Output
MUXCY_D Primitive: 2-to-1 Multiplexer for Carry Logic with Dual Output
MUXCY_L Primitive: 2-to-1 Multiplexer for Carry Logic with Local Output
XORCY Primitive: XOR for Carry Logic with General Output
XORCY_D Primitive: XOR for Carry Logic with Dual Output
XORCY_L Primitive: XOR for Carry Logic with Local Output
ComparatorDesign Element Description
COMP16 Macro: 16-Bit Identity Comparator
COMP2 Macro: 2-Bit Identity Comparator
COMP4 Macro: 4-Bit Identity Comparator
COMP8 Macro: 8-Bit Identity Comparator
COMPM16 Macro: 16-Bit Magnitude Comparator
COMPM2 Macro: 2-Bit Magnitude Comparator
COMPM4 Macro: 4-Bit Magnitude Comparator
COMPM8 Macro: 8-Bit Magnitude Comparator
COMPMC16 Macro: 16-Bit Magnitude Comparator
COMPMC8 Macro: 8-Bit Magnitude Comparator
CounterDesign Element Description
CB16CE Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
CB16CLE Macro: 16-Bit Loadable Cascadable Binary Counters with Clock Enable andAsynchronous Clear
CB16CLED Macro: 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enableand Asynchronous Clear
CB16RE Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
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Functional Categories
Design Element Description
CB2CE Macro: 2-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
CB2CLE Macro: 2-Bit Loadable Cascadable Binary Counters with Clock Enable andAsynchronous Clear
CB2CLED Macro: 2-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enableand Asynchronous Clear
CB2RE Macro: 2-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
CB4CE Macro: 4-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
CB4CLE Macro: 4-Bit Loadable Cascadable Binary Counters with Clock Enable andAsynchronous Clear
CB4CLED Macro: 4-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enableand Asynchronous Clear
CB4RE Macro: 4-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
CB8CE Macro: 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
CB8CLE Macro: 8-Bit Loadable Cascadable Binary Counters with Clock Enable andAsynchronous Clear
CB8CLED Macro: 8-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enableand Asynchronous Clear
CB8RE Macro: 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
CC16CE Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
CC16CLE Macro: 16-Bit Loadable Cascadable Binary Counter with Clock Enable andAsynchronous Clear
CC16CLED Macro: 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enableand Asynchronous Clear
CC16RE Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
CC8CE Macro: 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
CC8CLE Macro: 8-Bit Loadable Cascadable Binary Counter with Clock Enable andAsynchronous Clear
CC8CLED Macro: 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enableand Asynchronous Clear
CC8RE Macro: 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
CD4CE Macro: 4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear
CD4CLE Macro: 4-Bit Loadable Cascadable BCD Counter with Clock Enable and AsynchronousClear
CD4RE Macro: 4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset
CD4RLE Macro: 4-Bit Loadable Cascadable BCD Counter with Clock Enable and SynchronousReset
CJ4CE Macro: 4-Bit Johnson Counter with Clock Enable and Asynchronous Clear
CJ4RE Macro: 4-Bit Johnson Counter with Clock Enable and Synchronous Reset
CJ5CE Macro: 5-Bit Johnson Counter with Clock Enable and Asynchronous Clear
CJ5RE Macro: 5-Bit Johnson Counter with Clock Enable and Synchronous Reset
CJ8CE Macro: 8-Bit Johnson Counter with Clock Enable and Asynchronous Clear
CJ8RE Macro: 8-Bit Johnson Counter with Clock Enable and Synchronous Reset
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Functional Categories
Design Element Description
CR16CE Macro: 16-Bit Negative-Edge Binary Ripple Counter with Clock Enable andAsynchronous Clear
CR8CE Macro: 8-Bit Negative-Edge Binary Ripple Counter with Clock Enable andAsynchronous Clear
DecoderDesign Element Description
D2_4E Macro: 2- to 4-Line Decoder/Demultiplexer with Enable
D3_8E Macro: 3- to 8-Line Decoder/Demultiplexer with Enable
D4_16E Macro: 4- to 16-Line Decoder/Demultiplexer with Enable
DEC_CC16 Macro: 16-Bit Active Low Decoder
DEC_CC4 Macro: 4-Bit Active Low Decoder
DEC_CC8 Macro: 8-Bit Active Low Decoder
DECODE16 Macro: 16-Bit Active-Low Decoder
DECODE32 Macro: 32-Bit Active-Low Decoder
DECODE4 Macro: 4-Bit Active-Low Decoder
DECODE64 Macro: 64-Bit Active-Low Decoder
DECODE8 Macro: 8-Bit Active-Low Decoder
Flip FlopDesign Element Description
FD Primitive: D Flip-Flop
FD_1 Primitive: D Flip-Flop with Negative-Edge Clock
FD16CE Macro: 16-Bit Data Register with Clock Enable and Asynchronous Clear
FD16RE Macro: 16-Bit Data Register with Clock Enable and Synchronous Reset
FD4CE Macro: 4-Bit Data Register with Clock Enable and Asynchronous Clear
FD4RE Macro: 4-Bit Data Register with Clock Enable and Synchronous Reset
FD8CE Macro: 8-Bit Data Register with Clock Enable and Asynchronous Clear
FD8RE Macro: 8-Bit Data Register with Clock Enable and Synchronous Reset
FDC Primitive: D Flip-Flop with Asynchronous Clear
FDC_1 Primitive: D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
FDCE Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear
FDCE_1 Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and AsynchronousClear
FDCP Primitive: D Flip-Flop with Asynchronous Preset and Clear
FDCP_1 Primitive: D Flip-Flop with Negative-Edge Clock and Asynchronous Preset and Clear
FDCPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
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Functional Categories
Design Element Description
FDCPE_1 Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and AsynchronousPreset and Clear
FDE Primitive: D Flip-Flop with Clock Enable
FDE_1 Primitive: D Flip-Flop with Negative-Edge Clock and Clock Enable
FDP Primitive: D Flip-Flop with Asynchronous Preset
FDP_1 Primitive: D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
FDPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset
FDPE_1 Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and AsynchronousPreset
FDR Primitive: D Flip-Flop with Synchronous Reset
FDR_1 Primitive: D Flip-Flop with Negative-Edge Clock and Synchronous Reset
FDRE Primitive: D Flip-Flop with Clock Enable and Synchronous Reset
FDRE_1 Primitive: D Flip-Flop with Negative-Clock Edge, Clock Enable, and SynchronousReset
FDRS Primitive: D Flip-Flop with Synchronous Reset and Set
FDRS_1 Primitive: D Flip-Flop with Negative-Clock Edge and Synchronous Reset and Set
FDRSE Primitive: D Flip-Flop with Synchronous Reset and Set and Clock Enable
FDRSE_1 Primitive: D Flip-Flop with Negative-Clock Edge, Synchronous Reset and Set, andClock Enable
FDS Primitive: D Flip-Flop with Synchronous Set
FDS_1 Primitive: D Flip-Flop with Negative-Edge Clock and Synchronous Set
FDSE Primitive: D Flip-Flop with Clock Enable and Synchronous Set
FDSE_1 Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and Synchronous Set
FJKC Macro: J-K Flip-Flop with Asynchronous Clear
FJKCE Macro: J-K Flip-Flop with Clock Enable and Asynchronous Clear
FJKP Macro: J-K Flip-Flop with Asynchronous Preset
FJKPE Macro: J-K Flip-Flop with Clock Enable and Asynchronous Preset
FJKRSE Macro: J-K Flip-Flop with Clock Enable and Synchronous Reset and Set
FJKSRE Macro: J-K Flip-Flop with Clock Enable and Synchronous Set and Reset
FTC Macro: Toggle Flip-Flop with Asynchronous Clear
FTCE Macro: Toggle Flip-Flop with Clock Enable and Asynchronous Clear
FTCLE Macro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Clear
FTCLEX Macro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Clear
FTP Macro: Toggle Flip-Flop with Asynchronous Preset
FTPE Macro: Toggle Flip-Flop with Clock Enable and Asynchronous Preset
FTPLE Macro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Preset
FTRSE Macro: Toggle Flip-Flop with Clock Enable and Synchronous Reset and Set
FTRSLE Macro: Toggle/Loadable Flip-Flop with Clock Enable and Synchronous Reset and Set
FTSRE Macro: Toggle Flip-Flop with Clock Enable and Synchronous Set and Reset
FTSRLE Macro: Toggle/Loadable Flip-Flop with Clock Enable and Synchronous Set and Reset
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Functional Categories
GeneralDesign Element Description
BSCAN_SPARTAN2 Primitive: Spartan-II Boundary Scan Logic Control Circuit
BUFGDLL Primitive: Clock Delay Locked Loop Buffer
CAPTURE_SPARTAN2 Primitive: Spartan-II Register State Capture for Bitstream Readback
CLKDLL Primitive: Clock Delay Locked Loop
CLKDLLHF Primitive: High Frequency Clock Delay Locked Loop
GND Primitive: Ground-Connection Signal Tag
KEEPER Primitive: KEEPER Symbol
PULLDOWN Primitive: Resistor to GND for Input Pads, Open-Drain, and 3-State Outputs
PULLUP Primitive: Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs
STARTBUF_SPARTAN2 Primitive: VHDL Simulation of FPGA Designs
STARTUP_SPARTAN2 Primitive: Spartan-II User Interface to Global Clock, Reset, and 3-State Controls
VCC Primitive: VCC-Connection Signal Tag
IODesign Element Description
IBUF Primitive: Input Buffer
IBUF16 Macro: 16-Bit Input Buffer
IBUF4 Macro: 4-Bit Input Buffer
IBUF8 Macro: 8-Bit Input Buffer
IBUFG Primitive: Dedicated Input Clock Buffer
IOBUF Primitive: Bi-Directional Buffer
OBUF Primitive: Output Buffer
OBUF16 Macro: 16-Bit Output Buffer
OBUF4 Macro: 4-Bit Output Buffer
OBUF8 Macro: 8-Bit Output Buffer
OBUFE Macro: 3-State Output Buffer with Active-High Output Enable
OBUFE16 Macro: 16-Bit 3-State Output Buffer with Active-High Output Enable
OBUFE4 Macro: 4-Bit 3-State Output Buffer with Active-High Output Enable
OBUFE8 Macro: 8-Bit 3-State Output Buffer with Active-High Output Enable
OBUFT Primitive: 3-State Output Buffer with Active Low Output Enable
OBUFT16 Macro: 16-Bit 3-State Output Buffer with Active Low Output Enable
OBUFT4 Macro: 4-Bit 3-State Output Buffers with Active-Low Output Enable
OBUFT8 Macro: 8-Bit 3-State Output Buffers with Active-Low Output Enable
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Functional Categories
IO FlipFlop
Design Element Description
IFD Macro: Input D Flip-Flop
IFD_1 Macro: Input D Flip-Flop with Inverted Clock (Asynchronous Preset)
IFD16 Macro: 16-Bit Input D Flip-Flop
IFD4 Macro: 4-Bit Input D Flip-Flop
IFD8 Macro: 8-Bit Input D Flip-Flop
IFDI Macro: Input D Flip-Flop (Asynchronous Preset)
IFDI_1 Macro: Input D Flip-Flop with Inverted Clock (Asynchronous Preset)
IFDX Macro: Input D Flip-Flop with Clock Enable
IFDX_1 Macro: Input D Flip-Flop with Inverted Clock and Clock Enable
IFDX16 Macro: 16-Bit Input D Flip-Flops with Clock Enable
IFDX4 Macro: 4-Bit Input D Flip-Flop with Clock Enable
IFDX8 Macro: 8-Bit Input D Flip-Flop with Clock Enable
IFDXI Macro: Input D Flip-Flop with Clock Enable (Asynchronous Preset)
IFDXI_1 Macro: Input D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)
OFD Macro: Output D Flip-Flop
OFD_1 Macro: Output D Flip-Flop with Inverted Clock
OFD16 Macro: 16-Bit Output D Flip-Flop
OFD4 Macro: 4-Bit Output D Flip-Flop
OFD8 Macro: 8-Bit Output D Flip-Flop
OFDE Macro: D Flip-Flop with Active-High Enable Output Buffers
OFDE_1 Macro: D Flip-Flop with Active-High Enable Output Buffer and Inverted Clock
OFDE16 Macro: 16-Bit D Flip-Flop with Active-High Enable Output Buffers
OFDE4 Macro: 4-Bit D Flip-Flop with Active-High Enable Output Buffers
OFDE8 Macro: 8-Bit D Flip-Flop with Active-High Enable Output Buffers
OFDI Macro: Output D Flip-Flop (Asynchronous Preset)
OFDI_1 Macro: Output D Flip-Flop with Inverted Clock (Asynchronous Preset)
OFDT Macro: D Flip-Flop with Active-Low 3-State Output Buffer
OFDT_1 Macro: D Flip-Flop with Active-Low 3-State Output Buffer and Inverted Clock
OFDT16 Macro: 16-Bit D Flip-Flop with Active-Low 3-State Output Buffers
OFDT4 Macro: 4-Bit D Flip-Flop with Active-Low 3-State Output Buffers
OFDT8 Macro: 8-Bit D Flip-Flop with Active-Low 3-State Output Buffers
OFDX Macro: Output D Flip-Flop with Clock Enable
OFDX_1 Macro: Output D Flip-Flop with Inverted Clock and Clock Enable
OFDX16 Macro: 16-Bit Output D Flip-Flop with Clock Enable
OFDX4 Macro: 4-Bit Output D Flip-Flop with Clock Enable
OFDX8 Macro: 8-Bit Output D Flip-Flop with Clock Enable
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Functional Categories
Design Element Description
OFDXI Macro: Output D Flip-Flop with Clock Enable (Asynchronous Preset)
OFDXI_1 Macro: Output D Flip-Flop with Inverted Clock and Clock Enable (AsynchronousPreset)
IO Latch
Design Element Description
ILD Macro: Transparent Input Data Latch
ILD_1 Macro: Transparent Input Data Latch with Inverted Gate
ILD16 Macro: Transparent Input Data Latch
ILD4 Macro: Transparent Input Data Latch
ILD8 Macro: Transparent Input Data Latch
ILDI Macro: Transparent Input Data Latch (Asynchronous Preset)
ILDI_1 Macro: Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)
ILDX Macro: Transparent Input Data Latch
ILDX_1 Macro: Transparent Input Data Latch with Inverted Gate
ILDX16 Macro: Transparent Input Data Latch
ILDX4 Macro: Transparent Input Data Latch
ILDX8 Macro: Transparent Input Data Latch
ILDXI Macro: Transparent Input Data Latch (Asynchronous Preset)
ILDXI_1 Macro: Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)
Latch
Design Element Description
LD Primitive: Transparent Data Latch
LD_1 Primitive: Transparent Data Latch with Inverted Gate
LD16 Macro: Multiple Transparent Data Latch
LD16CE Macro: Transparent Data Latch with Asynchronous Clear and Gate Enable
LD4 Macro: Multiple Transparent Data Latch
LD4CE Macro: Transparent Data Latch with Asynchronous Clear and Gate Enable
LD8 Macro: Multiple Transparent Data Latch
LD8CE Macro: Transparent Data Latch with Asynchronous Clear and Gate Enable
LDC Primitive: Transparent Data Latch with Asynchronous Clear
LDC_1 Primitive: Transparent Data Latch with Asynchronous Clear and Inverted Gate
LDCE Primitive: Transparent Data Latch with Asynchronous Clear and Gate Enable
LDCE_1 Primitive: Transparent Data Latch with Asynchronous Clear, Gate Enable, andInverted Gate
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Functional Categories
Design Element Description
LDCP Primitive: Transparent Data Latch with Asynchronous Clear and Preset
LDCP_1 Primitive: Transparent Data Latch with Asynchronous Clear and Preset and InvertedGate
LDCPE Primitive: Transparent Data Latch with Asynchronous Clear and Preset and GateEnable
LDCPE_1 Primitive: Transparent Data Latch with Asynchronous Clear and Preset, Gate Enable,and Inverted Gate
LDE Primitive: Transparent Data Latch with Gate Enable
LDE_1 Primitive: Transparent Data Latch with Gate Enable and Inverted Gate
LDP Primitive: Transparent Data Latch with Asynchronous Preset
LDP_1 Primitive: Transparent Data Latch with Asynchronous Preset and Inverted Gate
LDPE Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable
LDPE_1 Primitive: Transparent Data Latch with Asynchronous Preset, Gate Enable, andInverted Gate
Logic
Design Element Description
AND12 Macro: 12- Input AND Gate with Non-Inverted Inputs
AND16 Macro: 16- Input AND Gate with Non-Inverted Inputs
AND2 Primitive: 2-Input AND Gate with Non-Inverted Inputs
AND2B1 Primitive: 2-Input AND Gate with 1 Inverted and 1 Non-Inverted Inputs
AND2B2 Primitive: 2-Input AND Gate with Inverted Inputs
AND3 Primitive: 3-Input AND Gate with Non-Inverted Inputs
AND3B1 Primitive: 3-Input AND Gate with 1 Inverted and 2 Non-Inverted Inputs
AND3B2 Primitive: 3-Input AND Gate with 2 Inverted and 1 Non-Inverted Inputs
AND3B3 Primitive: 3-Input AND Gate with Inverted Inputs
AND4 Primitive: 4-Input AND Gate with Non-Inverted Inputs
AND4B1 Primitive: 4-Input AND Gate with 1 Inverted and 3 Non-Inverted Inputs
AND4B2 Primitive: 4-Input AND Gate with 2 Inverted and 2 Non-Inverted Inputs
AND4B3 Primitive: 4-Input AND Gate with 3 Inverted and 1 Non-Inverted Inputs
AND4B4 Primitive: 4-Input AND Gate with Inverted Inputs
AND5 Primitive: 5-Input AND Gate with Non-Inverted Inputs
AND5B1 Primitive: 5-Input AND Gate with 1 Inverted and 4 Non-Inverted Inputs
AND5B2 Primitive: 5-Input AND Gate with 2 Inverted and 3 Non-Inverted Inputs
AND5B3 Primitive: 5-Input AND Gate with 3 Inverted and 2 Non-Inverted Inputs
AND5B4 Primitive: 5-Input AND Gate with 4 Inverted and 1 Non-Inverted Inputs
AND5B5 Primitive: 5-Input AND Gate with Inverted Inputs
AND6 Macro: 6-Input AND Gate with Non-Inverted Inputs
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Functional Categories
Design Element Description
AND7 Macro: 7-Input AND Gate with Non-Inverted Inputs
AND8 Macro: 8-Input AND Gate with Non-Inverted Inputs
AND9 Macro: 9-Input AND Gate with Non-Inverted Inputs
INV Primitive: Inverter
INV16 Macro: 16 Inverters
INV4 Macro: Four Inverters
INV8 Macro: Eight Inverters
MULT_AND Primitive: Fast Multiplier AND
NAND12 Macro: 12- Input NAND Gate with Non-Inverted Inputs
NAND16 Macro: 16- Input NAND Gate with Non-Inverted Inputs
NAND2 Primitive: 2-Input NAND Gate with Non-Inverted Inputs
NAND2B1 Primitive: 2-Input NAND Gate with 1 Inverted and 1 Non-Inverted Inputs
NAND2B2 Primitive: 2-Input NAND Gate with Inverted Inputs
NAND3 Primitive: 3-Input NAND Gate with Non-Inverted Inputs
NAND3B1 Primitive: 3-Input NAND Gate with 1 Inverted and 2 Non-Inverted Inputs
NAND3B2 Primitive: 3-Input NAND Gate with 2 Inverted and 1 Non-Inverted Inputs
NAND3B3 Primitive: 3-Input NAND Gate with Inverted Inputs
NAND4 Primitive: 4-Input NAND Gate with Non-Inverted Inputs
NAND4B1 Primitive: 4-Input NAND Gate with 1 Inverted and 3 Non-Inverted Inputs
NAND4B2 Primitive: 4-Input NAND Gate with 2 Inverted and 2 Non-Inverted Inputs
NAND4B3 Primitive: 4-Input NAND Gate with 3 Inverted and 1 Non-Inverted Inputs
NAND4B4 Primitive: 4-Input NAND Gate with Inverted Inputs
NAND5 Primitive: 5-Input NAND Gate with Non-Inverted Inputs
NAND5B1 Primitive: 5-Input NAND Gate with 1 Inverted and 4 Non-Inverted Inputs
NAND5B2 Primitive: 5-Input NAND Gate with 2 Inverted and 3 Non-Inverted Inputs
NAND5B3 Primitive: 5-Input NAND Gate with 3 Inverted and 2 Non-Inverted Inputs
NAND5B4 Primitive: 5-Input NAND Gate with 4 Inverted and 1 Non-Inverted Inputs
NAND5B5 Primitive: 5-Input NAND Gate with Inverted Inputs
NAND6 Macro: 6-Input NAND Gate with Non-Inverted Inputs
NAND7 Macro: 7-Input NAND Gate with Non-Inverted Inputs
NAND8 Macro: 8-Input NAND Gate with Non-Inverted Inputs
NAND9 Macro: 9-Input NAND Gate with Non-Inverted Inputs
NOR12 Macro: 12-Input NOR Gate with Non-Inverted Inputs
NOR16 Macro: 16-Input NOR Gate with Non-Inverted Inputs
NOR2 Primitive: 2-Input NOR Gate with Non-Inverted Inputs
NOR2B1 Primitive: 2-Input NOR Gate with 1 Inverted and 1 Non-Inverted Inputs
NOR2B2 Primitive: 2-Input NOR Gate with Inverted Inputs
NOR3 Primitive: 3-Input NOR Gate with Non-Inverted Inputs
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Functional Categories
Design Element Description
NOR3B1 Primitive: 3-Input NOR Gate with 1 Inverted and 2 Non-Inverted Inputs
NOR3B2 Primitive: 3-Input NOR Gate with 2 Inverted and 1 Non-Inverted Inputs
NOR3B3 Primitive: 3-Input NOR Gate with Inverted Inputs
NOR4 Primitive: 4-Input NOR Gate with Non-Inverted Inputs
NOR4B1 Primitive: 4-Input NOR Gate with 1 Inverted and 3 Non-Inverted Inputs
NOR4B2 Primitive: 4-Input NOR Gate with 2 Inverted and 2 Non-Inverted Inputs
NOR4B3 Primitive: 4-Input NOR Gate with 3 Inverted and 1 Non-Inverted Inputs
NOR4B4 Primitive: 4-Input NOR Gate with Inverted Inputs
NOR5 Primitive: 5-Input NOR Gate with Non-Inverted Inputs
NOR5B1 Primitive: 5-Input NOR Gate with 1 Inverted and 4 Non-Inverted Inputs
NOR5B2 Primitive: 5-Input NOR Gate with 2 Inverted and 3 Non-Inverted Inputs
NOR5B3 Primitive: 5-Input NOR Gate with 3 Inverted and 2 Non-Inverted Inputs
NOR5B4 Primitive: 5-Input NOR Gate with 4 Inverted and 1 Non-Inverted Inputs
NOR5B5 Primitive: 5-Input NOR Gate with Inverted Inputs
NOR6 Macro: 6-Input NOR Gate with Non-Inverted Inputs
NOR7 Macro: 7-Input NOR Gate with Non-Inverted Inputs
NOR8 Macro: 8-Input NOR Gate with Non-Inverted Inputs
NOR9 Macro: 9-Input NOR Gate with Non-Inverted Inputs
OR12 Macro: 12-Input OR Gate with Non-Inverted Inputs
OR16 Macro: 16-Input OR Gate with Non-Inverted Inputs
OR2 Primitive: 2-Input OR Gate with Non-Inverted Inputs
OR2B1 Primitive: 2-Input OR Gate with 1 Inverted and 1 Non-Inverted Inputs
OR2B2 Primitive: 2-Input OR Gate with Inverted Inputs
OR3 Primitive: 3-Input OR Gate with Non-Inverted Inputs
OR3B1 Primitive: 3-Input OR Gate with 1 Inverted and 2 Non-Inverted Inputs
OR3B2 Primitive: 3-Input OR Gate with 2 Inverted and 1 Non-Inverted Inputs
OR3B3 Primitive: 3-Input OR Gate with Inverted Inputs
OR4 Primitive: 4-Input OR Gate with Non-Inverted Inputs
OR4B1 Primitive: 4-Input OR Gate with 1 Inverted and 3 Non-Inverted Inputs
OR4B2 Primitive: 4-Input OR Gate with 2 Inverted and 2 Non-Inverted Inputs
OR4B3 Primitive: 4-Input OR Gate with 3 Inverted and 1 Non-Inverted Inputs
OR4B4 Primitive: 4-Input OR Gate with Inverted Inputs
OR5 Primitive: 5-Input OR Gate with Non-Inverted Inputs
OR5B1 Primitive: 5-Input OR Gate with 1 Inverted and 4 Non-Inverted Inputs
OR5B2 Primitive: 5-Input OR Gate with 2 Inverted and 3 Non-Inverted Inputs
OR5B3 Primitive: 5-Input OR Gate with 3 Inverted and 2 Non-Inverted Inputs
OR5B4 Primitive: 5-Input OR Gate with 4 Inverted and 1 Non-Inverted Inputs
OR5B5 Primitive: 5-Input OR Gate with Inverted Inputs
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Functional Categories
Design Element Description
OR6 Macro: 6-Input OR Gate with Non-Inverted Inputs
OR7 Macro: 7-Input OR Gate with Non-Inverted Inputs
OR8 Macro: 8-Input OR Gate with Non-Inverted Inputs
OR9 Macro: 9-Input OR Gate with Non-Inverted Inputs
SOP3 Macro: Sum of Products
SOP3B1A Macro: Sum of Products
SOP3B1B Macro: Sum of Products
SOP3B2A Macro: Sum of Products
SOP3B2B Macro: Sum of Products
SOP3B3 Macro: Sum of Products
SOP4 Macro: Sum of Products
SOP4B1 Macro: Sum of Products
SOP4B2A Macro: Sum of Products
SOP4B2B Macro: Sum of Products
SOP4B3 Macro: Sum of Products
SOP4B4 Macro: Sum of Products
XNOR2 Primitive: 2-Input XNOR Gate with Non-Inverted Inputs
XNOR3 Primitive: 3-Input XNOR Gate with Non-Inverted Inputs
XNOR4 Primitive: 4-Input XNOR Gate with Non-Inverted Inputs
XNOR5 Primitive: 5-Input XNOR Gate with Non-Inverted Inputs
XNOR6 Macro: 6-Input XNOR Gate with Non-Inverted Inputs
XNOR7 Macro: 7-Input XNOR Gate with Non-Inverted Inputs
XNOR8 Macro: 8-Input XNOR Gate with Non-Inverted Inputs
XNOR9 Macro: 9-Input XNOR Gate with Non-Inverted Inputs
XOR2 Primitive: 2-Input XOR Gate with Non-Inverted Inputs
XOR3 Primitive: 3-Input XOR Gate with Non-Inverted Inputs
XOR4 Primitive: 4-Input XOR Gate with Non-Inverted Inputs
XOR5 Primitive: 5-Input XOR Gate with Non-Inverted Inputs
XOR6 Macro: 6-Input XOR Gate with Non-Inverted Inputs
XOR7 Macro: 7-Input XOR Gate with Non-Inverted Inputs
XOR8 Macro: 8-Input XOR Gate with Non-Inverted Inputs
XOR9 Macro: 9-Input XOR Gate with Non-Inverted Inputs
LUT
Design Element Description
LUT1 Primitive: 1-Bit Look-Up-Table with General Output
LUT1_D Primitive: 1-Bit Look-Up-Table with Dual Output
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Design Element Description
LUT1_L Primitive: 1-Bit Look-Up-Table with Local Output
LUT2 Primitive: 2-Bit Look-Up-Table with General Output
LUT2_D Primitive: 2-Bit Look-Up-Table with Dual Output
LUT2_L Primitive: 2-Bit Look-Up-Table with Local Output
LUT3 Primitive: 3-Bit Look-Up-Table with General Output
LUT3_D Primitive: 3-Bit Look-Up-Table with Dual Output
LUT3_L Primitive: 3-Bit Look-Up-Table with Local Output
LUT4 Primitive: 4-Bit Look-Up-Table with General Output
LUT4_D Primitive: 4-Bit Look-Up-Table with Dual Output
LUT4_L Primitive: 4-Bit Look-Up-Table with Local Output
MapDesign Element Description
FMAP Primitive: F Function Generator Partitioning Control Symbol
MemoryDesign Element Description
RAM16X1D Primitive: 16-Deep by 1-Wide Static Dual Port Synchronous RAM
RAM16X1D_1 Primitive: 16-Deep by 1-Wide Static Dual Port Synchronous RAM with Negative-EdgeClock
RAM16X1S Primitive: 16-Deep by 1-Wide Static Synchronous RAM
RAM16X1S_1 Primitive: 16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
RAM16X2D Macro: 16-Deep by 2-Wide Static Dual Port Synchronous RAM
RAM16X2S Macro: 16-Deep by 2-Wide Static Synchronous RAM
RAM16X4D Macro: 16-Deep by 4-Wide Static Dual Port Synchronous RAM
RAM16X4S Macro: 16-Deep by 4-Wide Static Synchronous RAM
RAM16X8D Macro: 16-Deep by 8-Wide Static Dual Port Synchronous RAM
RAM16X8S Macro: 16-Deep by 8-Wide Static Synchronous RAM
RAM32X1S Primitive: 32-Deep by 1-Wide Static Synchronous RAM
RAM32X1S_1 Primitive: 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
RAM32X2S Primitive: 32-Deep by 2-Wide Static Synchronous RAM
RAM32X4S Primitive: 32-Deep by 4-Wide Static Synchronous RAM
RAM32X8S Primitive: 32-Deep by 8-Wide Static Synchronous RAM
RAMB4_S1 Primitive: 4K-bit Single-Port Synchronous Block RAM with Port Width Configured to1 Bit
RAMB4_S1_S1 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to1-bit
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Functional Categories
Design Element Description
RAMB4_S1_S16 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 1-bit and 16-bits
RAMB4_S1_S2 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 1-bit and 2-bits
RAMB4_S1_S4 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 1-bit and 4-bits
RAMB4_S1_S8 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 1-bit and 8-bits
RAMB4_S16 Primitive: 4096-Bit Single-Port Synchronous Block RAM with Port Width Configuredto 16 Bits
RAMB4_S16_S16 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 16-bits
RAMB4_S2 Primitive: 4K-bit Single-Port Synchronous Block RAM with Port Width Configuredto 2-bits
RAMB4_S2_S16 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to2-bits and 16-bits
RAMB4_S2_S2 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 2-bits and 2-bits
RAMB4_S2_S4 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 2-bits and 4-bits
RAMB4_S2_S8 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 2-bits and 8-bits
RAMB4_S4 Primitive: 4k-bit Single-Port Synchronous Block RAM with Port Width Configuredto 4-bits
RAMB4_S4_S16 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to4-bits and 16-bits
RAMB4_S4_S4 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 4-bits and 4-bits
RAMB4_S4_S8 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 4-bits and 8-bits
RAMB4_S8 Primitive: 4k-bit Single-Port Synchronous Block RAM with Port Width Configuredto 8-bits
RAMB4_S8_S16 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to8-bits and 16-bits
RAMB4_S8_S8 Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configuredto 8-bits
ROM16X1 Primitive: 16-Deep by 1-Wide ROM
ROM32X1 Primitive: 32-Deep by 1-Wide ROM
Mux
Design Element Description
M16_1E Macro: 16-to-1 Multiplexer with Enable
M2_1 Macro: 2-to-1 Multiplexer
M2_1B1 Macro: 2-to-1 Multiplexer with D0 Inverted
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Design Element Description
M2_1B2 Macro: 2-to-1 Multiplexer with D0 and D1 Inverted
M2_1E Macro: 2-to-1 Multiplexer with Enable
M4_1E Macro: 4-to-1 Multiplexer with Enable
M8_1E Macro: 8-to-1 Multiplexer with Enable
MUXF5 Primitive: 2-to-1 Look-Up Table Multiplexer with General Output
MUXF5_D Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output
MUXF5_L Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output
MUXF6 Primitive: 2-to-1 Look-Up Table Multiplexer with General Output
MUXF6_D Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output
MUXF6_L Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output
Shift RegisterDesign Element Description
SR16CE Macro: 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable andAsynchronous Clear
SR16CLE Macro: 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Asynchronous Clear
SR16CLED Macro: 16-Bit Shift Register with Clock Enable and Asynchronous Clear
SR16RE Macro: 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and SynchronousReset
SR16RLE Macro: 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Synchronous Reset
SR16RLED Macro: 16-Bit Shift Register with Clock Enable and Synchronous Reset
SR4CE Macro: 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and AsynchronousClear
SR4CLE Macro: 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Asynchronous Clear
SR4CLED Macro: 4-Bit Shift Register with Clock Enable and Asynchronous Clear
SR4RE Macro: 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and SynchronousReset
SR4RLE Macro: 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Synchronous Reset
SR4RLED Macro: 4-Bit Shift Register with Clock Enable and Synchronous Reset
SR8CE Macro: 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and AsynchronousClear
SR8CLE Macro: 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Asynchronous Clear
SR8CLED Macro: 8-Bit Shift Register with Clock Enable and Asynchronous Clear
SR8RE Macro: 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and SynchronousReset
SR8RLE Macro: 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enableand Synchronous Reset
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Functional Categories
Design Element Description
SR8RLED Macro: 8-Bit Shift Register with Clock Enable and Synchronous Reset
SRL16 Primitive: 16-Bit Shift Register Look-Up-Table (LUT)
SRL16_1 Primitive: 16-Bit Shift Register Look-Up-Table (LUT) with Negative-Edge Clock
SRL16E Primitive: 16-Bit Shift Register Look-Up-Table (LUT) with Clock Enable
SRL16E_1 Primitive: 16-Bit Shift Register Look-Up-Table (LUT) with Negative-Edge Clock andClock Enable
Shifter
Design Element Description
BRLSHFT4 Macro: 4-Bit Barrel Shifter
BRLSHFT8 Macro: 8-Bit Barrel Shifter
Spartan2E Components
Design Element Description
CLKDLLE Primitive: Clock Delay Locked Loop with Expanded Output
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28 www.xilinx.com 10.1
About Design ElementsThis section describes the design elements that can be used with this architecture. The design elements areorganized alphabetically.
The following information is provided for each design element, where applicable:
• Name of element
• Brief description
• Schematic symbol (if any)
• Logic Table (if any)
• Port Descriptions (if any)
• Design Entry Method
• Available Attributes (if any)
• For more information
You can find examples of VHDL and Verilog instantiation code in the ISE software (in the main menu, select Edit> Language Templates or in the Libraries Guide for HDL Designs for this architecture.
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About Design Elements
ACC16Macro: 16-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset
IntroductionThis design element can add or subtract a 16-bit unsigned-binary, respectively or twos-complement word toor from the contents of a 16-bit data register and store the results in the register. The register can be loadedwith the 16-bit word.
When the load input (L) is High, CE is ignored and the data on the D inputs is loaded into the register during theLow-to-High clock (C) transition. ACC16 loads the data on inputs D15 – D0 into the 16-bit register.
This design element operates on either 16-bit unsigned binary numbers or 16-bit twos-complement numbers. Ifthe inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as twos complement, the output can be interpreted as twos complement. The only functionaldifference between an unsigned binary operation and a twos-complement operation is how they determine when“overflow” occurs. Unsigned binary uses carry-out (CO), while twos complement uses OFL to determinewhen “overflow” occurs.• For unsigned binary operation, ACC16 can represent numbers between 0 and 15, inclusive. In add mode,
CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is anactive-Low borrow-out and goes Low when the difference exceeds the bounds. The carry-out (CO) isnot registered synchronously with the data outputs. CO always reflects the accumulation of the B inputs(B15 – B0 for ACC16). This allows the cascading of ACC16s by connecting CO of one stage to CI of thenext stage. An unsigned binary “overflow” that is always active-High can be generated by gating theADD signal and CO as follows:unsigned overflow = CO XOR ADD
Ignore OFL in unsigned binary operation.
• For twos-complement operation, ACC16 represents numbers between -8 and +7, inclusive. If an additionor subtraction operation result exceeds this range, the OFL output goes High. The overflow (OFL) is notregistered synchronously with the data outputs. OFL always reflects the accumulation of the B inputs (B15 –B0 for ACC16) and the contents of the register, which allows cascading of ACC4s by connecting OFL of onestage to CI of the next stage.Ignore CO in twos-complement operation.
The synchronous reset (R) has priority over all other inputs, and when set to High, causes all outputs to go tologic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clockenable (CE) is Low.
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About Design Elements
This design element is asynchronously cleared, outputs Low, when power is applied. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInput Output
R L CE ADD D C Q
1 x x x x ↑ 0
0 1 x x Dn ↑ Dn
0 0 1 1 x ↑ Q0+Bn+CI
0 0 1 0 x ↑ Q0-Bn-CI
0 0 0 x x ↑ No Change
Q0: Previous value of Q
Bn: Value of Data input B
CI: Value of input CI
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
ACC4Macro: 4-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset
IntroductionThis design element can add or subtract a 4-bit unsigned-binary, respectively or twos-complement word to orfrom the contents of a 4-bit data register and store the results in the register. The register can be loaded with the4-bit word.
When the load input (L) is High, CE is ignored and the data on the D inputs is loaded into the register during theLow-to-High clock (C) transition. ACC4 loads the data on inputs D3 – D0 into the 4-bit register.
This design element operates on either 4-bit unsigned binary numbers or 4-bit twos-complement numbers. Ifthe inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as twos complement, the output can be interpreted as twos complement. The only functionaldifference between an unsigned binary operation and a twos-complement operation is how they determine when“overflow” occurs. Unsigned binary uses carry-out (CO), while twos complement uses OFL to determinewhen “overflow” occurs.• For unsigned binary operation, ACC4 can represent numbers between 0 and 15, inclusive. In add mode,
CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is anactive-Low borrow-out and goes Low when the difference exceeds the bounds. The carry-out (CO) isnot registered synchronously with the data outputs. CO always reflects the accumulation of the B inputs(B3 – B0 for ACC4). This allows the cascading of ACC4s by connecting CO of one stage to CI of the nextstage. An unsigned binary “overflow” that is always active-High can be generated by gating the ADDsignal and CO as follows:unsigned overflow = CO XOR ADD
Ignore OFL in unsigned binary operation.
• For twos-complement operation, ACC4 represents numbers between -8 and +7, inclusive. If an additionor subtraction operation result exceeds this range, the OFL output goes High. The overflow (OFL) is notregistered synchronously with the data outputs. OFL always reflects the accumulation of the B inputs (B3 –B0 for ACC4) and the contents of the register, which allows cascading of ACC4s by connecting OFL of onestage to CI of the next stage.
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About Design Elements
Ignore CO in twos-complement operation.
The synchronous reset (R) has priority over all other inputs, and when set to High, causes all outputs to go tologic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clockenable (CE) is Low.
This design element is asynchronously cleared, outputs Low, when power is applied. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInput Output
R L CE ADD D C Q
1 x x x x ↑ 0
0 1 x x Dn ↑ Dn
0 0 1 1 x ↑ Q0+Bn+CI
0 0 1 0 x ↑ Q0-Bn-CI
0 0 0 x x ↑ No Change
Q0: Previous value of Q
Bn: Value of Data input B
CI: Value of input CI
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
ACC8Macro: 8-Bit Loadable Cascadable Accumulator with Carry-In, Carry-Out, and Synchronous Reset
IntroductionThis design element can add or subtract a 8-bit unsigned-binary, respectively or twos-complement word to orfrom the contents of a 8-bit data register and store the results in the register. The register can be loaded with the8-bit word.
When the load input (L) is High, CE is ignored and the data on the D inputs is loaded into the register during theLow-to-High clock (C) transition. ACC8 loads the data on inputs D7 – D0 into the 8-bit register.
This design element operates on either 8-bit unsigned binary numbers or 8-bit twos-complement numbers. Ifthe inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as twos complement, the output can be interpreted as twos complement. The only functionaldifference between an unsigned binary operation and a twos-complement operation is how they determine when“overflow” occurs. Unsigned binary uses carry-out (CO), while twos complement uses OFL to determinewhen “overflow” occurs.• For unsigned binary operation, ACC8 can represent numbers between 0 and 255, inclusive. In add mode,
CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is anactive-Low borrow-out and goes Low when the difference exceeds the bounds. The carry-out (CO) isnot registered synchronously with the data outputs. CO always reflects the accumulation of the B inputs(B3 – B0 for ACC4). This allows the cascading of ACC8s by connecting CO of one stage to CI of the nextstage. An unsigned binary “overflow” that is always active-High can be generated by gating the ADDsignal and CO as follows:unsigned overflow = CO XOR ADD
Ignore OFL in unsigned binary operation.
• For twos-complement operation, ACC8 represents numbers between -128 and +127, inclusive. If an additionor subtraction operation result exceeds this range, the OFL output goes High. The overflow (OFL) is notregistered synchronously with the data outputs. OFL always reflects the accumulation of the B inputs (B3 –B0 for ACC8) and the contents of the register, which allows cascading of ACC8s by connecting OFL of onestage to CI of the next stage.Ignore CO in twos-complement operation.
The synchronous reset (R) has priority over all other inputs, and when set to High, causes all outputs to go tologic level zero during the Low-to-High clock (C) transition. Clock (C) transitions are ignored when clockenable (CE) is Low.
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About Design Elements
This design element is asynchronously cleared, outputs Low, when power is applied. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInput Output
R L CE ADD D C Q
1 x x x x ↑ 0
0 1 x x Dn ↑ Dn
0 0 1 1 x ↑ Q0+Bn+CI
0 0 1 0 x ↑ Q0-Bn-CI
0 0 0 x x ↑ No Change
Q0: Previous value of Q
Bn: Value of Data input B
CI: Value of input CI
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
ADD16
Macro: 16-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow
IntroductionThis design element adds two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow(OFL). The factors added are A15 – A0, B15 – B0 and CI, producing the sum output S15 – S0 and CO (or OFL).
Logic TableInput Output
A B S
An Bn An+Bn+CI
CI: Value of input CI.
Unsigned Binary Versus Twos ComplementThis design element can operate on either 16-bit unsigned binary numbers or 16-bit twos-complement numbers,respectively. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. Ifthe inputs are interpreted as twos complement, the output can be interpreted as twos complement. The onlyfunctional difference between an unsigned binary operation and a twos-complement operation is the way theydetermine when “overflow” occurs. Unsigned binary uses CO, while twos-complement uses OFL to determinewhen “overflow” occurs. To interpret the inputs as unsigned binary, follow the CO output. To interpret theinputs as twos complement, follow the OFL output.
Unsigned Binary OperationFor unsigned binary operation, this element represents numbers between 0 and 65535, inclusive. OFL is ignoredin unsigned binary operation.
Twos-Complement OperationFor twos-complement operation, this element can represent numbers between -32768 and +32767, inclusive. OFLis active (High) when the sum exceeds the bounds of the adder. CO is ignored in twos-complement operation.
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About Design Elements
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
ADD4Macro: 4-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow
IntroductionThis design element adds two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow(OFL). The factors added are A3 – A0, B3 – B0, and CI producing the sum output S3 – S0 and CO (or OFL).
Logic TableInput Output
A B S
An Bn An+Bn+CI
CI: Value of input CI.
Unsigned Binary Versus Twos ComplementThis design element can operate on either 4-bit unsigned binary numbers or 4-bit twos-complement numbers,respectively. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. Ifthe inputs are interpreted as twos complement, the output can be interpreted as twos complement. The onlyfunctional difference between an unsigned binary operation and a twos-complement operation is the way theydetermine when “overflow” occurs. Unsigned binary uses CO, while twos-complement uses OFL to determinewhen “overflow” occurs. To interpret the inputs as unsigned binary, follow the CO output. To interpret theinputs as twos complement, follow the OFL output.
Unsigned Binary Operation
For unsigned binary operation, this element represents numbers from 0 to 15, inclusive. OFL is ignoredin unsigned binary operation.
Twos-Complement OperationFor twos-complement operation, this element can represent numbers between -8 and +7, inclusive. OFL is active(High) when the sum exceeds the bounds of the adder. CO is ignored in twos-complement operation.
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About Design Elements
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
ADD8
Macro: 8-Bit Cascadable Full Adder with Carry-In, Carry-Out, and Overflow
IntroductionThis design element adds two words and a carry-in (CI), producing a sum output and carry-out (CO) or overflow(OFL). The factors added are A7 – A0, B7 – B0, and CI, producing the sum output S7 – S0 and CO (or OFL).
Logic TableInput Output
A B S
An Bn An+Bn+CI
CI: Value of input CI.
Unsigned Binary Versus Twos ComplementThis design element can operate on either 8-bit unsigned binary numbers or 8-bit twos-complement numbers,respectively. If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. Ifthe inputs are interpreted as twos complement, the output can be interpreted as twos complement. The onlyfunctional difference between an unsigned binary operation and a twos-complement operation is the way theydetermine when “overflow” occurs. Unsigned binary uses CO, while twos-complement uses OFL to determinewhen “overflow” occurs. To interpret the inputs as unsigned binary, follow the CO output. To interpret theinputs as twos complement, follow the OFL output.
Unsigned Binary OperationFor unsigned binary operation, this element represents numbers between 0 and 255, inclusive. OFL is ignoredin unsigned binary operation.
Twos-Complement OperationFor twos-complement operation, this element can represent numbers between -128 and +127, inclusive. OFL isactive (High) when the sum exceeds the bounds of the adder. CO is ignored in twos-complement operation.
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About Design Elements
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
ADSU16
Macro: 16-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow
IntroductionWhen the ADD input is High, this element adds two 16-bit words (A15 – A0 and B15 – B0) and a carry-in (CI),producing a 16-bit sum output (S15 – S0) and carry-out (CO) or overflow (OFL).
When the ADD input is Low, this element subtracts B15 – B0 from A15– A0, producing a difference output anda carry-out (CO) or an overflow (OFL).
In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low. OFL is active-High inadd and subtract modes.
Logic TableInput Output
ADD A B S
1 An Bn An+Bn+CI*
0 An Bn An-Bn-CI*
CI*: ADD = 0, CI, CO active LOW
CI*: ADD = 1, CI, CO active HIGH
Unsigned Binary Versus Twos Complement
This design element can operate on either 16-bit unsigned binary numbers or 16-bit twos-complement numbers.If the inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as twos complement, the output can be interpreted as twos complement. The only functionaldifference between an unsigned binary operation and a twos-complement operation is the way they determinewhen “overflow” occurs. Unsigned binary uses CO, while twos complement uses OFL to determine when“overflow” occurs.
With adder/subtracters, either unsigned binary or twos-complement operations cause an overflow. If the resultcrosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-outboundary, a carry-out is generated.
Unsigned Binary Operation
For unsigned binary operation, this element can represent numbers between 0 and 65535, inclusive. In addmode, CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is anactive-Low borrow-out and goes Low when the difference exceeds the bounds.
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About Design Elements
An unsigned binary “overflow” that is always active-High can be generated by gating the ADD signal and COas follows:unsigned overflow = CO XOR ADD
OFL is ignored in unsigned binary operation.
Twos-Complement Operation
For twos-complement operation, this element can represent numbers between -32768 and +32767, inclusive.
If an addition or subtraction operation result exceeds this range, the OFL output goes High. CO is ignoredin twos-complement operation.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 43
About Design Elements
ADSU4
Macro: 4-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow
IntroductionWhen the ADD input is High, this element adds two 4-bit words (A3 – A0 and B3 – B0) and a carry-in (CI),producing a 4-bit sum output (S3 – S0) and a carry-out (CO) or an overflow (OFL).
When the ADD input is Low, this element subtracts B3 – B0 from A3– A0, producing a 4-bit difference output(S3 – S0) and a carry-out (CO) or an overflow (OFL).
In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low. OFL is active-High inadd and subtract modes.
Logic TableInput Output
ADD A B S
1 An Bn An+Bn+CI*
0 An Bn An-Bn-CI*
CI*: ADD = 0, CI, CO active LOW
CI*: ADD = 1, CI, CO active HIGH
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About Design Elements
Unsigned Binary Versus Twos Complement
This design element can operate on either 4-bit unsigned binary numbers or 4-bit twos-complement numbers. Ifthe inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as twos complement, the output can be interpreted as twos complement. The only functionaldifference between an unsigned binary operation and a twos-complement operation is the way they determinewhen “overflow” occurs. Unsigned binary uses CO, while twos complement uses OFL to determine when“overflow” occurs.
With adder/subtracters, either unsigned binary or twos-complement operations cause an overflow. If the resultcrosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-outboundary, a carry-out is generated.
Unsigned Binary Operation
For unsigned binary operation, ADSU4 can represent numbers between 0 and 15, inclusive. In add mode, CO isactive (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is an active-Lowborrow-out and goes Low when the difference exceeds the bounds.
An unsigned binary “overflow” that is always active-High can be generated by gating the ADD signal and COas follows:unsigned overflow = CO XOR ADD
OFL is ignored in unsigned binary operation.
Twos-Complement Operation
For twos-complement operation, this element can represent numbers between -8 and +7, inclusive.
If an addition or subtraction operation result exceeds this range, the OFL output goes High. CO is ignoredin twos-complement operation.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
ADSU8
Macro: 8-Bit Cascadable Adder/Subtracter with Carry-In, Carry-Out, and Overflow
IntroductionWhen the ADD input is High, this element adds two 8-bit words (A7 – A0 and B7 – B0) and a carry-in (CI),producing, an 8-bit sum output (S7 – S0) and carry-out (CO) or an overflow (OFL).
When the ADD input is Low, this element subtracts B7 – B0 from A7 – A0, producing an 8-bit difference output(S7 – S0) and a carry-out (CO) or an overflow (OFL).
In add mode, CO and CI are active-High. In subtract mode, CO and CI are active-Low. OFL is active-High inadd and subtract modes.
Logic TableInput Output
ADD A B S
1 An Bn An+Bn+CI*
0 An Bn An-Bn-CI*
CI*: ADD = 0, CI, CO active LOW
CI*: ADD = 1, CI, CO active HIGH
Unsigned Binary Versus Twos Complement
This design element can operate on either 8-bit unsigned binary numbers or 8-bit twos-complement numbers. Ifthe inputs are interpreted as unsigned binary, the result can be interpreted as unsigned binary. If the inputsare interpreted as twos complement, the output can be interpreted as twos complement. The only functionaldifference between an unsigned binary operation and a twos-complement operation is the way they determinewhen “overflow” occurs. Unsigned binary uses CO, while twos complement uses OFL to determine when“overflow” occurs.
With adder/subtracters, either unsigned binary or twos-complement operations cause an overflow. If the resultcrosses the overflow boundary, an overflow is generated. Similarly, when the result crosses the carry-outboundary, a carry-out is generated.
Unsigned Binary Operation
For unsigned binary operation, this element can represent numbers between 0 and 255, inclusive. In add mode,CO is active (High) when the sum exceeds the bounds of the adder/subtracter. In subtract mode, CO is anactive-Low borrow-out and goes Low when the difference exceeds the bounds.
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About Design Elements
An unsigned binary “overflow” that is always active-High can be generated by gating the ADD signal and COas follows:unsigned overflow = CO XOR ADD
OFL is ignored in unsigned binary operation.
Twos-Complement Operation
For twos-complement operation, this element can represent numbers between -128 and +127, inclusive.
If an addition or subtraction operation result exceeds this range, the OFL output goes High. CO is ignoredin twos-complement operation.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 47
About Design Elements
AND12
Macro: 12- Input AND Gate with Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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AND16
Macro: 16- Input AND Gate with Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
AND2
Primitive: 2-Input AND Gate with Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
AND2B1
Primitive: 2-Input AND Gate with 1 Inverted and 1 Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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AND2B2
Primitive: 2-Input AND Gate with Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND3
Primitive: 3-Input AND Gate with Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
AND3B1
Primitive: 3-Input AND Gate with 1 Inverted and 2 Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND3B2
Primitive: 3-Input AND Gate with 2 Inverted and 1 Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND3B3
Primitive: 3-Input AND Gate with Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND4
Primitive: 4-Input AND Gate with Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND4B1
Primitive: 4-Input AND Gate with 1 Inverted and 3 Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND4B2
Primitive: 4-Input AND Gate with 2 Inverted and 2 Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
AND4B3
Primitive: 4-Input AND Gate with 3 Inverted and 1 Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND4B4
Primitive: 4-Input AND Gate with Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND5
Primitive: 5-Input AND Gate with Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND5B1
Primitive: 5-Input AND Gate with 1 Inverted and 4 Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND5B2
Primitive: 5-Input AND Gate with 2 Inverted and 3 Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND5B3
Primitive: 5-Input AND Gate with 3 Inverted and 2 Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
AND5B4
Primitive: 5-Input AND Gate with 4 Inverted and 1 Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND5B5
Primitive: 5-Input AND Gate with Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND6
Macro: 6-Input AND Gate with Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND7
Macro: 7-Input AND Gate with Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
AND8
Macro: 8-Input AND Gate with Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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AND9
Macro: 9-Input AND Gate with Non-Inverted Inputs
IntroductionAND functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ANDfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with noninverting inputs. To make someor all inputs inverting, use external inverters. Because each input uses a CLB resource, replace functions withunused inputs with functions having the appropriate number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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BRLSHFT4
Macro: 4-Bit Barrel Shifter
IntroductionThis design element is a 4-bit barrel shifter that can rotate four inputs (I3 – I0) up to four places. The controlinputs (S1 and S0) determine the number of positions, from one to four, that the data is rotated. The four outputs(O3 – O0) reflect the shifted data inputs.
Logic TableInputs Outputs
S1 S0 I0 I1 I2 I3 O0 O1 O2 O3
0 0 a b c d a b c d
0 1 a b c d b c d a
1 0 a b c d c d a b
1 1 a b c d d a b c
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BRLSHFT8Macro: 8-Bit Barrel Shifter
IntroductionThis design element is an 8-bit barrel shifter, can rotate the eight inputs (I7 – I0) up to eight places. The controlinputs (S2 – S0) determine the number of positions, from one to eight, that the data is rotated. The eight outputs(O7 – O0) reflect the shifted data inputs.
Logic TableInputs Outputs
S2 S1 S0 I0 I1 I2 I3 I4 I5 I6 I7 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 a b c d e f g h a b c d e f g h
0 0 1 a b c d e f g h b c d e f g h a
0 1 0 a b c d e f g h c d e f g h a b
0 1 1 a b c d e f g h d e f g h a b c
1 0 0 a b c d e f g h e f g h a b c d
1 0 1 a b c d e f g h f g h a b c d e
1 1 0 a b c d e f g h g h a b c d e f
1 1 1 a b c d e f g h h a b c d e f g
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
BSCAN_SPARTAN2
Primitive: Spartan-II Boundary Scan Logic Control Circuit
IntroductionThis design element creates internal boundary scan chains in a Spartan-II device. The 4-pin JTAG interface (TDI,TDO, TCK, and TMS) are dedicated pins in Spartan-II. To use normal JTAG for boundary scan purposes, justhook up the JTAG pins to the port and go. The pins on the BSCAN_SPARTAN2 symbol do not need to beconnected, unless those special functions are needed to drive an internal scan chain.
A signal on the TDO1 input is passed to the external TDO output when the USER1 instruction is executed; theSEL1 output goes High to indicate that the USER1 instruction is active.The DRCK1 output provides USER1 accessto the data register clock (generated by the TAP controller). The TDO2 and SEL2 pins perform a similar functionfor the USER2 instruction and the DRCK2 output provides USER2 access to the data register clock (generatedby the TAP controller). The RESET, UPDATE, and SHIFT pins represent the decoding of the correspondingstate of the boundary scan internal state machine. The TDI pin provides access to the TDI signal of the JTAGport in order to shift data into an internal scan chain.
Note For specific information on boundary scan for an architecture, see The Programmable Logic Data Sheets
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
BUF
Primitive: General Purpose Buffer
IntroductionThis is a general-purpose, non-inverting buffer.
This element is not necessary and is removed by the partitioning software (MAP).
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BUFCF
Primitive: Fast Connect Buffer
IntroductionThis design element is a single fast connect buffer used to connect the outputs of the LUTs and some dedicatedlogic directly to the input of another LUT. Using this buffer implies CLB packing. No more than four LUTsmay be connected together as a group.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
BUFE
Primitive: Internal 3-State Buffer with Active High Enable
IntroductionThis design element is a single, 3-state buffer with input I and output O, and an active-High output enable (E).When E is High, data on the input of the buffer is transferred to the corresponding output. When E is Low, theoutput is high impedance (Z state or Off). The outputs of the buffers are connected to horizontal longlinesin FPGA architectures.
The outputs of separate symbols for this entity can be tied together to form a bus or a multiplexer. Make surethat only one E is High at any one time. If none of the E inputs is active-High, a “weak-keeper” circuit keepsthe output bus from floating but does not guarantee that the bus remains at the last value driven onto it. Forcertain CPLD devices, output from nets assume the High logic level when all connected BUFE/BUFT buffersare disabled. For FPGA devices, elements need a PULLUP element connected to their output. NGDBuildinserts a PULLUP element if one is not connected.
Logic TableInputs Outputs
E I O
0 X Z
1 1 1
1 0 0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BUFE16
Macro: 16-Bit Internal 3-State Buffer with Active High Enable
IntroductionThis design element is a multiple 3-state buffer with inputs of I15 – I0 and outputs of O15 – O0 and an active-Highoutput enable (E). When E is High, data on the inputs of the buffers is transferred to the corresponding outputs.
When E is Low, the output is high impedance (Z state or Off). The outputs of the buffers are connected tohorizontal longlines in FPGA architectures. The outputs of separate BUFE elements can be tied together toform a bus or a multiplexer. Make sure that only one E is High at any one time. If none of the E inputs isactive-High, a “weak-keeper” circuit keeps the output bus from floating but does not guarantee that the busremains at the last value driven onto it.
Logic TableInputs Outputs
E I O
0 X Z
1 1 1
1 0 0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BUFE4
Macro: 4-BitInternal 3-State Buffer with Active High Enable
IntroductionThis design element is a multiple 3-state buffer with inputs of I3 – I0 and outputs of O3 – O0 and an active-Highoutput enable (E). When E is High, data on the inputs of the buffers is transferred to the corresponding outputs.
When E is Low, the output is high impedance (Z state or Off). The outputs of the buffers are connected tohorizontal longlines in FPGA architectures. The outputs of separate BUFE elements can be tied together toform a bus or a multiplexer. Make sure that only one E is High at any one time. If none of the E inputs isactive-High, a “weak-keeper” circuit keeps the output bus from floating but does not guarantee that the busremains at the last value driven onto it.
Logic TableInputs Outputs
E I O
0 X Z
1 1 1
1 0 0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BUFE8
Macro: 8-Bit Internal 3-State Buffer with Active High Enable
IntroductionThis design element is a multiple 3-state buffer with inputs of I7 – I0 and outputs of O7 – O0 and an active-Highoutput enable (E). When E is High, data on the inputs of the buffers is transferred to the corresponding outputs.
When E is Low, the output is high impedance (Z state or Off). The outputs of the buffers are connected tohorizontal longlines in FPGA architectures. The outputs of separate BUFE elements can be tied together toform a bus or a multiplexer. Make sure that only one E is High at any one time. If none of the E inputs isactive-High, a “weak-keeper” circuit keeps the output bus from floating but does not guarantee that the busremains at the last value driven onto it.
Logic TableInputs Outputs
E I O
0 X Z
1 1 1
1 0 0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BUFG
Primitive: Global Clock Buffer
IntroductionThis design element is a high-fanout buffer that connects signals to the global routing resources for low skewdistribution of the signal. BUFGs are typically used on clock nets as well other high fanout nets like sets/resetsand clock enables.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BUFGDLL
Primitive: Clock Delay Locked Loop Buffer
IntroductionThis design element is a special purpose clock delay locked loop buffer for clock skew management. Itis provided as a user convenience for the most frequently used configuration of elements for clock skewmanagement. Internally, it consists of an IBUFG driving the CLKIN pin of a CLKDLL followed by a BUFG that isdriven by the CLK0 pin of the CLKDLL. Because this element already contains an input buffer (IBUFG), it canonly be driven by a top-level port (IPAD).
Any DUTY_CYCLE_CORRECTION attribute on this design element applies to the underlying CLKDLL symbol.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BUFGP
Primitive: Primary Global Buffer for Driving Clocks or Longlines (Four per PLD Device)
IntroductionThis design element is a primary global buffer that is used to distribute high fan-out clock or control signalsthroughout in FPGA devices. It is equivalent to an IBUFG driving a BUFG.
This design element provides direct access to Configurable Logic Block (CLB) and Input Output Block (IOB)clock pins and limited access to other CLB inputs. The input to a BUFGP comes only from a dedicated IOB.Because of its structure, this element can always access a clock pin directly. However, it can access only oneof the F3, G1, C3, or C1 pins, depending on the corner in which the BUFGP is placed. When the required pincannot be accessed directly from the vertical line, PAR feeds the signal through another CLB and uses generalpurpose routing to access the load pin.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BUFT
Primitive: Internal 3-State Buffer with Active Low Enable
IntroductionThis design element is a single 3-state buffer with input I and an output of O and active-Low output enable (T).When T is Low, data on the input of the buffer is transferred to the corresponding output. When T is High,the output is high impedance (Z state or off). The output of the buffer is connected to a horizontal longlinein FPGA architectures.
The output of separate BUFT symbols can be tied together to form a bus or a multiplexer. Make sure that onlyone T is Low at one time. For CPLD devices, BUFT output nets assume the High logic level when all connectedBUFE/BUFT buffers are disabled. For FPGAs, when all BUFTs on a net are disabled, the net is High. For correctsimulation of this effect, a PULLUP element must be connected to the net. NGDBuild inserts a PULLUP elementif one is not connected so that back-annotation simulation reflects the true state of the device.
Logic TableInputs Outputs
T I O
1 X Z
0 1 1
0 0 0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BUFT16Macro: 16-Bit Internal 3-State Buffers with Active Low Enable
IntroductionThis design element is a multiple 3-state buffer with inputs I15 – 10 and outputs O15 – O0 and active-Low outputenable (T). When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When Tis High, the output is high impedance (Z state or off). The outputs of the buffers are connected to horizontallonglines in FPGA architectures.
This design element is a dedicated random access memory blocks with synchronous write capability. The blockRAM port has 16384 bits of data memory. The cell configuration for this element is listed in the following table.
Logic TableInputs Outputs
GSR EN SSR WE CLK ADDR DI DIP DO DOP RAM Contents
Data RAM Parity RAM
1 X X X X X X X INIT INIT No Change No Change
0 0 X X X X X X NoChange
NoChange No Change No Change
0 1 1 0 ↑ X X X SRVAL SRVAL No Change No Change
0 1 1 1 ↑ addr data pdata SRVAL SRVAL RAM(addr)=>data
RAM(addr)=>pdata
0 1 0 0 ↑ addr X X RAM(addr) RAM(addr) No Change No Change
0 1 0 1 ↑ addr data pdata NoChange(a)RAM(addr)(b)data(c)
NoChange(a)RAM(addr)(b)pdata(c)
RAM(addr)=>data
RAM(addr)=>pdata
GSR=Global Set Reset signal
INIT=Value specified by the INIT attribute for data memory. Default is all zeros.
SRVAL=Value after assertion of SSR as specified by the SRVAL attribute.
addr=RAM address.
RAM(addr)=RAM contents at address ADDR.
data=RAM input data.
pdata=RAM parity data.
(a) WRITE_MODE=NO_CHANGE
(b) WRITE_MODE=READ_FIRST
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Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
BUFT4
Macro: 4-Bit Internal 3-State Buffers with Active Low Enable
IntroductionThis design element is a multiple 3-state buffer with inputs I3 – I0 and outputs O3 – O0 and active-Low outputenable (T). When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When Tis High, the output is high impedance (Z state or off). The outputs of the buffers are connected to horizontallonglines in FPGA architectures.
This design element is a dedicated random access memory blocks with synchronous write capability. The blockRAM port has 16384 bits of data memory. The cell configuration for this element is listed in the following table.
Logic TableInputs Outputs
GSR EN SSR WE CLK ADDR DI DIP DO DOP RAM Contents
Data RAM Parity RAM
1 X X X X X X X INIT INIT No Change No Change
0 0 X X X X X X NoChange
NoChange No Change No Change
0 1 1 0 ↑ X X X SRVAL SRVAL No Change No Change
0 1 1 1 ↑ addr data pdata SRVAL SRVAL RAM(addr)=>data
RAM(addr)=>pdata
0 1 0 0 ↑ addr X X RAM(addr) RAM(addr) No Change No Change
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Inputs Outputs
GSR EN SSR WE CLK ADDR DI DIP DO DOP RAM Contents
Data RAM Parity RAM
0 1 0 1 ↑ addr data pdata NoChange(a)RAM(addr)(b)data(c)
NoChange(a)RAM(addr)(b)pdata(c)
RAM(addr)=>data
RAM(addr)=>pdata
GSR=Global Set Reset signal
INIT=Value specified by the INIT attribute for data memory. Default is all zeros.
SRVAL=Value after assertion of SSR as specified by the SRVAL attribute.
addr=RAM address.
RAM(addr)=RAM contents at address ADDR.
data=RAM input data.
pdata=RAM parity data.
(a) WRITE_MODE=NO_CHANGE
(b) WRITE_MODE=READ_FIRST
(c) WRITE_MODE=WRITE_FIRST
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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BUFT8Macro: 8-Bit Internal 3-State Buffers with Active Low Enable
IntroductionThis design element is a multiple 3-state buffer with inputs I7 – I0 and outputs O7 – O0 and active-Low outputenable (T). When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When Tis High, the output is high impedance (Z state or off). The outputs of the buffers are connected to horizontallonglines in FPGA architectures.
This design element is a dedicated random access memory blocks with synchronous write capability. The blockRAM port has 16384 bits of data memory. The cell configuration for this element is listed in the following table.
Logic TableInputs Outputs
GSR EN SSR WE CLK ADDR DI DIP DO DOP RAM Contents
Data RAM Parity RAM
1 X X X X X X X INIT INIT No Change No Change
0 0 X X X X X X NoChange
NoChange No Change No Change
0 1 1 0 ↑ X X X SRVAL SRVAL No Change No Change
0 1 1 1 ↑ addr data pdata SRVAL SRVAL RAM(addr)=>data
RAM(addr)=>pdata
0 1 0 0 ↑ addr X X RAM(addr) RAM(addr) No Change No Change
0 1 0 1 ↑ addr data pdata NoChange(a)RAM(addr)(b)data(c)
NoChange(a)RAM(addr)(b)pdata(c)
RAM(addr)=>data
RAM(addr)=>pdata
GSR=Global Set Reset signal
INIT=Value specified by the INIT attribute for data memory. Default is all zeros.
SRVAL=Value after assertion of SSR as specified by the SRVAL attribute.
addr=RAM address.
RAM(addr)=RAM contents at address ADDR.
data=RAM input data.
pdata=RAM parity data.
(a) WRITE_MODE=NO_CHANGE
(b) WRITE_MODE=READ_FIRST
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Design Entry MethodThis design element can be used in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CAPTURE_SPARTAN2Primitive: Spartan-II Register State Capture for Bitstream Readback
IntroductionThis element provides user control and synchronization over when and how the capture register (flip-flop andlatch) information task is requested. The readback function is provided through dedicated configuration portinstructions. However, without this element, the readback data is synchronized to the configuration clock.Only register (flip-flop and latch) states can be captured. Although LUT RAM, SRL, and block RAM statesare readback, they cannot be captured.
An asserted high CAP signal indicates that the registers in the device are to be captured at the next Low-to-Highclock transition. By default, data is captured after every trigger when transition on CLK while CAP is asserted.To limit the readback operation to a single data capture, add the ONESHOT=TRUE attribute to this element.
Port DescriptionsPort Direction Width Function
CAP Input 1 Readback capture trigger
CLK Input 1 Readback capture clock
Design Entry MethodThis design element can be used in schematics.
Connect all inputs and outputs to the design in order to ensure proper operation.
Available Attributes
Attribute Type Allowed Values Default Description
ONESHOT Boolean TRUE, FALSE TRUE Specifies the procedure for performing single readback perCAP trigger.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB16CEMacro: 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is an asynchronously clearable, cascadable binary counter. The asynchronous clear (CLR)input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out(CEO) to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input(CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Qz-Q0 TC CEO
1 X X 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB16CLE
Macro: 16-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
IntroductionThis element is a synchronously loadable, asynchronously clearable, cascadable binary counter. Theasynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminalcount (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data on theD inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clocktransition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during theLow-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is Highwhen all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C Dz – D0 Qz – Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X No change No change 0
0 0 1 ↑ X Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
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Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB16CLED
Macro: 16-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable andAsynchronous Clear
IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs,terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data onthe D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock(C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High andUP is Low during the Low-to- High clock transition. The Q outputs increment when CE and UP are High. Thecounter ignores clock transitions when CE is Low.
For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.
For CPLD parts, see “CB2X1”, “CB4X1”, “CB8X1”, “CB16X1” for high-performance cascadable, bidirectionalcounters.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 0 0 X X X No change No change 0
0 0 1 ↑ 1 X Inc TC CEO
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Inputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
0 0 1 ↑ 0 X Dec TC CEO
z = bit width - 1
TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB16REMacro: 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
IntroductionThis design element is a synchronous, resettable, cascadable binary counter. The synchronous reset (R), whenHigh, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) tozero on the Low-to-High clock transition. The Q outputs increment when the clock enable input (CE) is Highduring the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TCoutput is High when both Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE C Qz-Q0 TC CEO
1 X ↑ 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB2CE
Macro: 2-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is an asynchronously clearable, cascadable binary counter. The asynchronous clear (CLR)input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out(CEO) to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input(CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Qz-Q0 TC CEO
1 X X 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB2CLE
Macro: 2-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
IntroductionThis element is a synchronously loadable, asynchronously clearable, cascadable binary counter. Theasynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminalcount (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data on theD inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clocktransition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during theLow-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is Highwhen all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C Dz – D0 Qz – Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X No change No change 0
0 0 1 ↑ X Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
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Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB2CLED
Macro: 2-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable andAsynchronous Clear
IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs,terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data onthe D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock(C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High andUP is Low during the Low-to- High clock transition. The Q outputs increment when CE and UP are High. Thecounter ignores clock transitions when CE is Low.
For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.
For CPLD parts, see “CB2X1”, “CB4X1”, “CB8X1”, “CB16X1” for high-performance cascadable, bidirectionalcounters.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 0 0 X X X No change No change 0
0 0 1 ↑ 1 X Inc TC CEO
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Inputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
0 0 1 ↑ 0 X Dec TC CEO
z = bit width - 1
TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB2RE
Macro: 2-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
IntroductionThis design element is a synchronous, resettable, cascadable binary counter. The synchronous reset (R), whenHigh, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) tozero on the Low-to-High clock transition. The Q outputs increment when the clock enable input (CE) is Highduring the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TCoutput is High when both Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE C Qz-Q0 TC CEO
1 X ↑ 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB4CE
Macro: 4-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is an asynchronously clearable, cascadable binary counter. The asynchronous clear (CLR)input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out(CEO) to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input(CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Qz-Q0 TC CEO
1 X X 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB4CLE
Macro: 4-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
IntroductionThis element is a synchronously loadable, asynchronously clearable, cascadable binary counter. Theasynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminalcount (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data on theD inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clocktransition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during theLow-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is Highwhen all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C Dz – D0 Qz – Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X No change No change 0
0 0 1 ↑ X Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
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Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB4CLEDMacro: 4-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable andAsynchronous Clear
IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs,terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data onthe D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock(C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High andUP is Low during the Low-to- High clock transition. The Q outputs increment when CE and UP are High. Thecounter ignores clock transitions when CE is Low.
For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.
For CPLD parts, see “CB2X1”, “CB4X1”, “CB8X1”, “CB16X1” for high-performance cascadable, bidirectionalcounters.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 0 0 X X X No change No change 0
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Inputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
0 0 1 ↑ 1 X Inc TC CEO
0 0 1 ↑ 0 X Dec TC CEO
z = bit width - 1
TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB4RE
Macro: 4-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
IntroductionThis design element is a synchronous, resettable, cascadable binary counter. The synchronous reset (R), whenHigh, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) tozero on the Low-to-High clock transition. The Q outputs increment when the clock enable input (CE) is Highduring the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TCoutput is High when both Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE C Qz-Q0 TC CEO
1 X ↑ 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB8CEMacro: 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is an asynchronously clearable, cascadable binary counter. The asynchronous clear (CLR)input, when High, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out(CEO) to logic level zero, independent of clock transitions. The Q outputs increment when the clock enable input(CE) is High during the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Qz-Q0 TC CEO
1 X X 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB8CLEMacro: 8-Bit Loadable Cascadable Binary Counters with Clock Enable and Asynchronous Clear
IntroductionThis element is a synchronously loadable, asynchronously clearable, cascadable binary counter. Theasynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs, terminalcount (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data on theD inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clocktransition, independent of the state of clock enable (CE). The Q outputs increment when CE is High during theLow-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is Highwhen all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C Dz – D0 Qz – Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X No change No change 0
0 0 1 ↑ X Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB8CLED
Macro: 8-Bit Loadable Cascadable Bidirectional Binary Counters with Clock Enable andAsynchronous Clear
IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. The asynchronous clear (CLR) input, when High, overrides all other inputs and forces the Q outputs,terminal count (TC), and clock enable out (CEO) to logic level zero, independent of clock transitions. The data onthe D inputs is loaded into the counter when the load enable input (L) is High during the Low-to-High clock(C) transition, independent of the state of clock enable (CE). The Q outputs decrement when CE is High andUP is Low during the Low-to- High clock transition. The Q outputs increment when CE and UP are High. Thecounter ignores clock transitions when CE is Low.
For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.
For CPLD parts, see “CB2X1”, “CB4X1”, “CB8X1”, “CB16X1” for high-performance cascadable, bidirectionalcounters.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 0 0 X X X No change No change 0
0 0 1 ↑ 1 X Inc TC CEO
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Inputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
0 0 1 ↑ 0 X Dec TC CEO
z = bit width - 1
TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CB8REMacro: 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
IntroductionThis design element is a synchronous, resettable, cascadable binary counter. The synchronous reset (R), whenHigh, overrides all other inputs and forces the Q outputs, terminal count (TC), and clock enable out (CEO) tozero on the Low-to-High clock transition. The Q outputs increment when the clock enable input (CE) is Highduring the Low-to-High clock (C) transition. The counter ignores clock transitions when CE is Low. The TCoutput is High when both Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE C Qz-Q0 TC CEO
1 X ↑ 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CC16CE
Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is an asynchronously clearable, cascadable binary counter. It is implemented using carrylogic with relative location constraints to ensure efficient logic placement. The asynchronous clear (CLR) is thehighest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), andclock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment whenthe clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clocktransitions when CE is Low. The TC output is High when all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Qz-Q0 TC CEO
1 X X 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CC16CLE
Macro: 16-Bit Loadable Cascadable Binary Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable binary counter. It isimplemented using carry logic with relative location constraints to ensure efficient logic placement. Theasynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored;the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clocktransitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during theLow-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs increment whenCE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C Dz – D0 Qz – Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X No change No change 0
0 0 1 ↑ X Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
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Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CC16CLED
Macro: 16-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable andAsynchronous Clear
IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. It is implemented using carry logic with relative location constraints, which assures most efficient logicplacement. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs areignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent ofclock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is Highduring the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputsdecrement when CE is High and UP is Low during the Low-to-High clock transition. The Q outputs incrementwhen CE and UP are High. The counter ignores clock transitions when CE is Low.
For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 0 0 X X X No change No change 0
0 0 1 ↑ 1 X Inc TC CEO
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Inputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
0 0 1 ↑ 0 X Dec TC CEO
z = bit width - 1
TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CC16RE
Macro: 16-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
IntroductionThis design element is a synchronous resettable, cascadable binary counter. These counters are implementedusing carry logic with relative location constraints to ensure efficient logic placement. The synchronous reset(R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count(TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q outputsincrement when the clock enable input (CE) is High during the Low-to-High clock transition. The counterignores clock transitions when CE is Low. The TC output is High when all Q outputs and CE are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE C Qz-Q0 TC CEO
1 X ↑ 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CC8CE
Macro: 8-Bit Cascadable Binary Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is an asynchronously clearable, cascadable binary counter. It is implemented using carrylogic with relative location constraints to ensure efficient logic placement. The asynchronous clear (CLR) is thehighest priority input. When CLR is High, all other inputs are ignored; the Q outputs, terminal count (TC), andclock enable out (CEO) go to logic level zero, independent of clock transitions. The Q outputs increment whenthe clock enable input (CE) is High during the Low-to-High clock (C) transition. The counter ignores clocktransitions when CE is Low. The TC output is High when all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Qz-Q0 TC CEO
1 X X 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CC8CLE
Macro: 8-Bit Loadable Cascadable Binary Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable binary counter. It isimplemented using carry logic with relative location constraints to ensure efficient logic placement. Theasynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs are ignored;the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clocktransitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during theLow-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputs increment whenCE is High during the Low-to-High clock transition. The counter ignores clock transitions when CE is Low.The TC output is High when all Q outputs are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C Dz – D0 Qz – Q0 TC CEO
1 X X X X 0 0 0
0 1 X ↑ Dn Dn TC CEO
0 0 0 X X No change No change 0
0 0 1 ↑ X Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0
CEO = TC•CE
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Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CC8CLED
Macro: 8-Bit Loadable Cascadable Bidirectional Binary Counter with Clock Enable andAsynchronous Clear
IntroductionThis design element is a synchronously loadable, asynchronously clearable, cascadable, bidirectional binarycounter. It is implemented using carry logic with relative location constraints, which assures most efficient logicplacement. The asynchronous clear (CLR) is the highest priority input. When CLR is High, all other inputs areignored; the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent ofclock transitions. The data on the D inputs is loaded into the counter when the load enable input (L) is Highduring the Low-to-High clock (C) transition, independent of the state of clock enable (CE). The Q outputsdecrement when CE is High and UP is Low during the Low-to-High clock transition. The Q outputs incrementwhen CE and UP are High. The counter ignores clock transitions when CE is Low.
For counting up, the TC output is High when all Q outputs and UP are High. For counting down, the TCoutput is High when all Q outputs and UP are Low.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, UP, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. Themaximum length of the counter is determined by the accumulated CE-to-TC propagation delays versus the clockperiod. The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC isthe CE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counteruses the CE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
1 X X X X X 0 0 0
0 1 X ↑ X Dn Dn TC CEO
0 0 0 X X X No change No change 0
0 0 1 ↑ 1 X Inc TC CEO
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Inputs Outputs
CLR L CE C UP Dz – D0 Qz – Q0 TC CEO
0 0 1 ↑ 0 X Dec TC CEO
z = bit width - 1
TC = (Qz•Q(z-1)•Q(z-2)•...•Q0•UP) + (Qz•Q(z-1)•Q(z-2)•...•Q0•UP)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CC8RE
Macro: 8-Bit Cascadable Binary Counter with Clock Enable and Synchronous Reset
IntroductionThis design element is a synchronous resettable, cascadable binary counter. These counters are implementedusing carry logic with relative location constraints to ensure efficient logic placement. The synchronous reset(R) is the highest priority input. When R is High, all other inputs are ignored; the Q outputs, terminal count(TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock (C) transition. The Q outputsincrement when the clock enable input (CE) is High during the Low-to-High clock transition. The counterignores clock transitions when CE is Low. The TC output is High when all Q outputs and CE are High.
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. .For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE C Qz-Q0 TC CEO
1 X ↑ 0 0 0
0 0 X No change No change 0
0 1 ↑ Inc TC CEO
z = bit width - 1
TC = Qz•Q(z-1)•Q(z-2)•...•Q0)
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CD4CEMacro: 4-Bit Cascadable BCD Counter with Clock Enable and Asynchronous Clear
IntroductionCD4CE is a 4-bit (stage), asynchronous clearable, cascadable binary-coded-decimal (BCD) counter. Theasynchronous clear input (CLR) is the highest priority input. When CLR is High, all other inputs are ignored;the Q outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independent of clocktransitions. The Q outputs increment when clock enable (CE) is High during the Low-to-High clock (C)transition. The counter ignores clock transitions when CE is Low. The TC output is High when Q3 and Q0 areHigh and Q2 and Q1 are Low.
The counter recovers from any of six possible illegal states and returns to a normal count sequence within twoclock cycles for Xilinx® devices, as shown in the following state diagram:
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Q3 Q2 Q1 Q0 TC CEO
1 X X 0 0 0 0 0 0
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Inputs Outputs
CLR CE C Q3 Q2 Q1 Q0 TC CEO
0 1 ↑ Inc Inc Inc Inc TC CEO
0 0 X No Change No Change No Change No Change TC 0
0 1 X 1 0 0 1 1 1
TC = Q3•!Q2•!Q1•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CD4CLE
Macro: 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Asynchronous Clear
IntroductionCD4CLE is a 4-bit (stage), synchronously loadable, asynchronously clearable, binarycoded- decimal (BCD)counter. The asynchronous clear input (CLR) is the highest priority input. When (CLR) is High, all other inputsare ignored; the (Q) outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero, independentof clock transitions. The data on the (D) inputs is loaded into the counter when the load enable input (L) is Highduring the Low-to-High clock (C) transition. The (Q) outputs increment when clock enable input (CE) is Highduring the Low- to-High clock transition. The counter ignores clock transitions when (CE) is Low. The (TC)output is High when Q3 and Q0 are High and Q2 and Q1 are Low.
The counter recovers from any of six possible illegal states and returns to a normal count sequence within twoclock cycles for Xilinx® devices, as shown in the following state diagram:
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and CLR inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
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Logic TableInputs Outputs
CLR L CE D3 – D0 C Q3 Q2 Q1 Q0 TC CEO
1 X X X X 0 0 0 0 0 0
0 1 X D3 – D0 ↑ D3 D2 D1 D0 TC CEO
0 0 1 X ↑ Inc Inc Inc Inc TC CEO
0 0 0 X X NoChange
NoChange
NoChange
NoChange
TC 0
0 0 1 X X 1 0 0 1 1 1
TC = Q3•!Q2•!Q1•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CD4REMacro: 4-Bit Cascadable BCD Counter with Clock Enable and Synchronous Reset
IntroductionCD4RE is a 4-bit (stage), synchronous resettable, cascadable binary-coded-decimal (BCD) counter. Thesynchronous reset input (R) is the highest priority input. When (R) is High, all other inputs are ignored; the(Q) outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clock(C) transition. The (Q) outputs increment when the clock enable input (CE) is High during the Low-to- Highclock transition. The counter ignores clock transitions when (CE) is Low. The (TC) output is High when Q3and Q0 are High and Q2 and Q1 are Low.
The counter recovers from any of six possible illegal states and returns to a normal count sequence within twoclock cycles for Xilinx® devices, as shown in the following state diagram:
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximum lengthof the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period. Theclock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is the CE-to-TCpropagation delay of each stage. When cascading counters, use the CEO output if the counter uses the CEinput or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE C Q3 Q2 Q1 Q0 TC CEO
1 X ↑ 0 0 0 0 0 0
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Inputs Outputs
R CE C Q3 Q2 Q1 Q0 TC CEO
0 1 ↑ Inc Inc Inc Inc TC CEO
0 0 X No Change No Change No Change No Change TC 0
0 1 X 1 0 0 1 1 1
TC = Q3•!Q2•!Q1•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CD4RLE
Macro: 4-Bit Loadable Cascadable BCD Counter with Clock Enable and Synchronous Reset
IntroductionCD4RLE is a 4-bit (stage), synchronous loadable, resettable, binary-coded-decimal (BCD) counter. Thesynchronous reset input (R) is the highest priority input. When R is High, all other inputs are ignored; theQ outputs, terminal count (TC), and clock enable out (CEO) go to logic level zero on the Low-to-High clocktransitions. The data on the D inputs is loaded into the counter when the load enable input (L) is High during theLow-to-High clock (C) transition. The Q outputs increment when the clock enable input (CE) is High during theLow-to-High clock transition. The counter ignores clock transitions when CE is Low. The TC output is Highwhen Q3 and Q0 are High and Q2 and Q1 are Low.
The counter recovers from any of six possible illegal states and returns to a normal count sequence within twoclock cycles for Xilinx® devices, as shown in the following state diagram:
Create larger counters by connecting the CEO output of each stage to the CE input of the next stage andconnecting the C, L, and R inputs in parallel. CEO is active (High) when TC and CE are High. The maximumlength of the counter is determined by the accumulated CE-to-TC propagation delays versus the clock period.The clock period must be greater than n (tCE-TC), where n is the number of stages and the time tCE-TC is theCE-to-TC propagation delay of each stage. When cascading counters, use the CEO output if the counter uses theCE input or use the TC output if it does not.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
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Logic TableInputs Outputs
R L CE D3 – D0 C Q3 Q2 Q1 Q0 TC CEO
1 X X X ↑ 0 0 0 0 0 0
0 1 X D3 – D0 ↑ D3 D D D0 TC CEO
0 0 1 X ↑ Inc Inc Inc Inc TC CEO
0 0 0 X X No Change NoChange
NoChange
NoChange
TC 0
0 0 1 X X 1 0 0 1 1 1
TC = Q3•!Q2•!Q1•Q0
CEO = TC•CE
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CJ4CE
Macro: 4-Bit Johnson Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is a clearable Johnson/shift counter. The asynchronous clear (CLR) input, when High,overrides all other inputs and forces the data (Q) outputs to logic level zero, independent of clock (C) transitions.The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when (CE) is Low.
The Q3 output is inverted and fed back to input Q0 to provide continuous counting operation.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Q0 Q1 through Q3
1 X X 0 0
0 0 X No change No change
0 1 ↑ !q3 q0 through q2
q = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CJ4RE
Macro: 4-Bit Johnson Counter with Clock Enable and Synchronous Reset
IntroductionThis design element is a resettable Johnson/shift counter. The synchronous reset (R) input, when High, overridesall other inputs and forces the data (Q) outputs to logic level zero during the Low-to-High clock (C) transition.The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when CE is Low.
The Q3 output is inverted and fed back to input Q0 to provide continuous counting operation.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE C Q0 Q1 through Q3
1 X ↑ 0 0
0 0 X No change No change
0 1 ↑ !q3 q0 through q2
q = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CJ5CE
Macro: 5-Bit Johnson Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is a clearable Johnson/shift counter. The asynchronous clear (CLR) input, when High,overrides all other inputs and forces the data (Q) outputs to logic level zero, independent of clock (C) transitions.The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when (CE) is Low.
The Q4 output is inverted and fed back to input Q0 to provide continuous counting operation.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Q0 Q1 through Q4
1 X X 0 0
0 0 X No change No change
0 1 ↑ !q4 q0 through q3
q = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CJ5RE
Macro: 5-Bit Johnson Counter with Clock Enable and Synchronous Reset
IntroductionThis design element is a resettable Johnson/shift counter. The synchronous reset (R) input, when High, overridesall other inputs and forces the data (Q) outputs to logic level zero during the Low-to-High clock (C) transition.The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when CE is Low.
The Q4 output is inverted and fed back to input Q0 to provide continuous counting operation.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE C Q0 Q1 through Q4
1 X ↑ 0 0
0 0 X No change No change
0 1 ↑ !q4 q0 through q3
q = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CJ8CE
Macro: 8-Bit Johnson Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is a clearable Johnson/shift counter. The asynchronous clear (CLR) input, when High,overrides all other inputs and forces the data (Q) outputs to logic level zero, independent of clock (C) transitions.The counter increments (shifts Q0 to Q1, Q1 to Q2,and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when (CE) is Low.
The Q7 output is inverted and fed back to input Q0 to provide continuous counting operation.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Q0 Q1 through Q8
1 X X 0 0
0 0 X No change No change
0 1 ↑ !q7 q0 through q7
q = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CJ8RE
Macro: 8-Bit Johnson Counter with Clock Enable and Synchronous Reset
IntroductionThis design element is a resettable Johnson/shift counter. The synchronous reset (R) input, when High, overridesall other inputs and forces the data (Q) outputs to logic level zero during the Low-to-High clock (C) transition.The counter increments (shifts Q0 to Q1, Q1 to Q2, and so forth) when the clock enable input (CE) is High duringthe Low-to-High clock transition. Clock transitions are ignored when CE is Low.
The Q7 output is inverted and fed back to input Q0 to provide continuous counting operation.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE C Q0 Q1 through Q7
1 X ↑ 0 0
0 0 X No change No change
0 1 ↑ !q7 q0 through q6
q = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CLKDLLPrimitive: Clock Delay Locked Loop
IntroductionThis design element is a clock delay locked loop used to minimize clock skew. It synchronizes the clock signal atthe feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) ishigh when the two signals are in phase. The signals are considered to be in phase when their rising edges arewithin a specific range of each other (see The Programmable Logic Data Sheets for the most current value).
The frequency of the clock signal at the CLKIN input must be in a specific range depending on speed grade (seeThe Programmable Logic Data Sheets for the most current values). The CLKIN pin must be driven by an IBUFGor a BUFG. If phase alignment is not required, CLKIN can also be driven by IBUF.
On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock networkdriven by a BUFG, a global clock buffer. The BUFG connected to the CLKFB input of the CLKDLL must besourced from either the CLK0 or CLK2X outputs of the same CLKDLL. The CLKIN input should be connected tothe output of an IBUFG, with the IBUFG input connected to a pad driven by the system clock.
Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFGinput connected to a pad. Either the CLK0 or CLK2X output can be used but not both. The CLK0 or CLK2X mustbe connected to the input of OBUF, an output buffer.
The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, inwhich case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs(CLK90, CLK180, and CLK270) is the same as that of the CLK0 output. The duty cycle of the CLK2X andCLKDV outputs is always 50-50. The frequency of the CLKDV output is determined by the value assigned tothe CLKDV_DIVIDE attribute.
The master reset input (RST) resets CLKDLL to its initial (power-on) state. The signal at the RST input isasynchronous and must be held High for just 2ns.
Port DescriptionsPort Function
CLK0 Clock at 1x CLKIN frequency
CLK180 Clock at 1x CLKIN frequency, shifted 180 o with regards to CLK0
CLK270 Clock at 1x CLKIN frequency, shifted 270 o with regards to CLK0
CLK2X Clock at 2x CLKIN frequency, in phase with CLK0
CLK90 Clock at 1x CLKIN frequency, shifted 90 o with regards to CLK0
CLKDV Clock at (1/n)x CLKIN frequency, n=CLKDV_DIVIDE value. CLKDV is in phase with CLK0.
LOCKED CLKDLL locked
Note See the "PERIOD Specifications on CLKDLLs and DCM" in the Constraints Guide for additionalinformation on using the TNM, TNM_NET, and PERIOD attributes with CLKDLL components.
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Design Entry MethodThis design element can be used in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CLKDLLEPrimitive: Clock Delay Locked Loop with Expanded Output
IntroductionThis design element is a clock delay locked loop used to minimize clock skew. It synchronizes the clock signal atthe feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The locked output (LOCKED) ishigh when the two signals are in phase. The signals are considered to be in phase when their rising edges arewithin a specific range of each other (see The Programmable Logic Data Sheets for the most current value).
The frequency of the clock signal at the CLKIN input must be in a specific range depending on speed grade(see The Programmable Logic Data Sheets for the most current values). The CLKIN pin must be driven by anIBUFG or a BUFG.
On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock networkdriven by a BUFG, a global clock buffer. The BUFG input can only be connected to the CLK0 or CLK2X output ofCLKDLLE. The BUFG connected to the CLKFB input of the CLKDLLE must be sourced from either the CLK0or CLK2X outputs of the same CLKDLLE. The CLKIN input should be connected to the output of an IBUFG,with the IBUFG input connected to a pad driven by the system clock.
Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with the IBUFGinput connected to a pad. Either the CLK0 or CLK2X output can be used but not both. The CLK0 or CLK2X mustbe connected to the input of OBUF, an output buffer.
The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, inwhich case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted outputs(CLK90, CLK180, and CLK270) is the same as that of the CLK0 output. The duty cycle of the CLK2X andCLKDV outputs is always 50-50. The frequency of the CLKDV output is determined by the value assigned tothe CLKDV_DIVIDE attribute.
The master reset input (RST) resets CLKDLL to its initial (power-on) state. The signal at the RST input isasynchronous and must be held High for just 2ns.
Port DescriptionsPort Function
CLK0 Clock at 1x CLKIN frequency
CLK180 Clock at 1x CLK0 frequency, shifted 180 o with regards to CLK0
CLK270 Clock at 1x CLK0 frequency, shifted 270 o with regards to CLK0
CLK2X Clock at 2x CLK0 frequency, in phase with CLK0
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Port Function
CLK2X180 Clock at 1x CLK2X frequency shifted 180 o with regards to CLK2X
CLK90 Clock at 1x CLK0 frequency, shifted 90 o with regards to CLK0
CLKDV Clock at (1/n) x CLK0 frequency, where n=CLKDV_DIVIDE value. CLKDV is in phase withCLK0.
LOCKED CLKDLLE locked. CLKIN and CLKFB synchronized.
Note See the "PERIOD Specifications on CLKDLLs and DCM" in the Constraints Guide for additionalinformation on using the TNM, TNM_NET, and PERIOD attributes with CLKDLLE components.
Design Entry MethodThis design element can be used in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CLKDLLHF
Primitive: High Frequency Clock Delay Locked Loop
IntroductionThis design element is a high frequency clock delay locked loop used to minimize clock skew. It synchronizesthe clock signal at the feedback clock input (CLKFB) to the clock signal at the input clock (CLKIN). The lockedoutput (LOCKED) is high when the two signals are in phase. The signals are considered to be in phase whentheir rising edges are within a specific range of each other (see The Programmable Logic Data Sheets for themost current value).
The frequency of the clock signal at the CLKIN input must be in a specific range depending on speed grade(see The Programmable Logic Data Sheets for the most current values). The CLKIN pin must be driven by anIBUFG or a BUFG.
On-chip synchronization is achieved by connecting the CLKFB input to a point on the global clock networkdriven by a BUFG, a global clock buffer. The BUFG input can only be connected to the CLK0 output ofCLKDLLHF. The BUFG connected to the CLKFB input of the CLKDLLHF must be sourced from the CLK0 outputof the same CLKDLLHF. The CLKIN input should be connected to the output of an IBUFG, with the IBUFGinput connected to a pad driven by the system clock.
Off-chip synchronization is achieved by connecting the CLKFB input to the output of an IBUFG, with theIBUFG input connected to a pad. Only the CLK0 output can be used. CLK0 must be connected to the input ofOBUF, an output buffer.
The duty cycle of the CLK0 output is 50-50 unless the DUTY_CYCLE_CORRECTION attribute is set to FALSE, inwhich case the duty cycle is the same as that of the CLKIN input. The duty cycle of the phase shifted output(CLK180) is the same as that of the CLK0 output. The frequency of the CLKDV output is determined by the valueassigned to the CLKDV_DIVIDE attribute.
The master reset input (RST) resets CLKDLL to its initial (power-on) state. The signal at the RST input isasynchronous and must be held High for just 2ns.
Port DescriptionsOutput Function
CLK0 Clock at 1x CLKIN frequency
CLK180 Clock at 1x CLKIN frequency, shifted 180o with regards to CLK0
CLKDV Clock at (1/n)x CLKIN frequency, n=CLKDV_DIVIDE value. CLKDV is in phase with CLK0.
LOCKED CLKDLLHF locked
Note See the "PERIOD Specifications on CLKDLLs and DCM" section of the "Xilinx Constraints P" chapterin the Constraints Guide for additional information on using the TNM, TNM_NET, and PERIOD attributeswith CLKDLLHF components.
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Design Entry MethodThis design element can be used in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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COMP16
Macro: 16-Bit Identity Comparator
IntroductionThis design element is a 16-bit identity comparator. The equal output (EQ) is high when A15 – A0 and B15 –B0 are equal.
Equality is determined by a bit comparison of the two words. When any two of the corresponding bits fromeach word are not the same, the EQ output is Low.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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COMP2
Macro: 2-Bit Identity Comparator
IntroductionThis design element is a 2-bit identity comparator. The equal output (EQ) is High when the two words A1 – A0and B1 – B0 are equal.
Equality is determined by a bit comparison of the two words. When any two of the corresponding bits fromeach word are not the same, the EQ output is Low.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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COMP4
Macro: 4-Bit Identity Comparator
IntroductionThis design element is a 4-bit identity comparator. The equal output (EQ) is high when A3 – A0 and B3 –B0 are equal.
Equality is determined by a bit comparison of the two words. When any two of the corresponding bits fromeach word are not the same, the EQ output is Low.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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COMP8
Macro: 8-Bit Identity Comparator
IntroductionThis design element is an 8-bit identity comparator. The equal output (EQ) is high when A7 – A0 and B7 –B0 are equal.
Equality is determined by a bit comparison of the two words. When any two of the corresponding bits fromeach word are not the same, the EQ output is Low.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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COMPM16
Macro: 16-Bit Magnitude Comparator
IntroductionThis design element is a 16-bit magnitude comparator that compare two positive Binary-weighted words. Itcompares A15 – A0 and B15 – B0, where A15 and B15 are the most significant bits.
The greater-than output (GT) is High when A > B, and the less-than output (LT) is High when A < B Whenthe two words are equal, both GT and LT are Low. Equality can be measured with this macro by comparingboth outputs with a NOR gate.
Logic TableInputs Outputs
A7, B7 A6, B6 A5, B5 A4, B4 A3, B3 A2, B2 A1, B1 A0, B0 GT LT
A7>B7 X X X X X X X 1 0
A7<B7 X X X X X X X 0 1
A7=B7 A6>B6 X X X X X X 1 0
A7=B7 A6<B6 X X X X X X 0 1
A7=B7 A6=B6 A5>B5 X X X X X 1 0
A7=B7 A6=B6 A5<B5 X X X X X 0 1
A7=B7 A6=B6 A5=B5 A4>B4 X X X X 1 0
A7=B7 A6=B6 A5=B5 A4<B4 X X X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3>B3 X X X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3<B3 X X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2>B2 X X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2<B2 X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1>B1 X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1<B1 X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0>B0 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0<B0 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0=B0 0 0
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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COMPM2
Macro: 2-Bit Magnitude Comparator
IntroductionThis design element is a 2-bit magnitude comparator that compare two positive Binary-weighted words. Itcompares A1 – A0 and B1 – B0, where A1 and B1 are the most significant bits.
The greater-than output (GT) is High when A > B, and the less-than output (LT) is High when A < B Whenthe two words are equal, both GT and LT are Low. Equality can be measured with this macro by comparingboth outputs with a NOR gate.
Logic TableInputs Outputs
A1 B1 A0 B0 GT LT
0 0 0 0 0 0
0 0 1 0 1 0
0 0 0 1 0 1
0 0 1 1 0 0
1 1 0 0 0 0
1 1 1 0 1 0
1 1 0 1 0 1
1 1 1 1 0 0
1 0 X X 1 0
0 1 X X 0 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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COMPM4
Macro: 4-Bit Magnitude Comparator
IntroductionThis design element is a 4-bit magnitude comparator that compare two positive Binary-weighted words. Itcompares A3 – A0 and B3 – B0, where A3 and B3 are the most significant bits.
The greater-than output (GT) is High when A > B, and the less-than output (LT) is High when A < B Whenthe two words are equal, both GT and LT are Low. Equality can be measured with this macro by comparingboth outputs with a NOR gate.
Logic TableInputs Outputs
A3, B3 A2, B2 A1, B1 A0, B0 GT LT
A3>B3 X X X 1 0
A3<B3 X X X 0 1
A3=B3 A2>B2 X X 1 0
A3=B3 A2<B2 X X 0 1
A3=B3 A2=B2 A1>B1 X 1 0
A3=B3 A2=B2 A1<B1 X 0 1
A3=B3 A2=A2 A1=B1 A0>B0 1 0
A3=B3 A2=B2 A1=B1 A0<B0 0 1
A3=B3 A2=B2 A1=B1 A0=B0 0 0
Design Entry MethodThis design element is only for use in schematics.
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COMPM8
Macro: 8-Bit Magnitude Comparator
IntroductionThis design element is an 8-bit magnitude comparator that compare two positive Binary-weighted words. Itcompares A7 – A0 and B7 – B0, where A7 and B7 are the most significant bits.
The greater-than output (GT) is High when A > B, and the less-than output (LT) is High when A < B Whenthe two words are equal, both GT and LT are Low. Equality can be measured with this macro by comparingboth outputs with a NOR gate.
Logic TableInputs Outputs
A7, B7 A6, B6 A5, B5 A4, B4 A3, B3 A2, B2 A1, B1 A0, B0 GT LT
A7>B7 X X X X X X X 1 0
A7<B7 X X X X X X X 0 1
A7=B7 A6>B6 X X X X X X 1 0
A7=B7 A6<B6 X X X X X X 0 1
A7=B7 A6=B6 A5>B5 X X X X X 1 0
A7=B7 A6=B6 A5<B5 X X X X X 0 1
A7=B7 A6=B6 A5=B5 A4>B4 X X X X 1 0
A7=B7 A6=B6 A5=B5 A4<B4 X X X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3>B3 X X X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3<B3 X X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2>B2 X X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2<B2 X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1>B1 X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1<B1 X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0>B0 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0<B0 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0=B0 0 0
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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COMPMC16
Macro: 16-Bit Magnitude Comparator
IntroductionThis design element is a 16-bit, magnitude comparator that compares two positive Binary weighted words A15 –A0 and B15 – B0, where A15 and B15 are the most significant bits.
This comparator is implemented using carry logic with relative location constraints to ensure efficient logicplacement.
The greater-than output (GT) is High when A>B, and the less-than output (LT) is High when A<B. When thetwo words are equal, both GT and LT are Low. Equality can be flagged with this macro by connecting bothoutputs to a NOR gate.
Logic TableInputs Outputs
A7, B7 A6, B6 A5, B5 A4, B4 A3, B3 A2, B2 A1, B1 A0, B0 GT LT
A7>B7 X X X X X X X 1 0
A7<B7 X X X X X X X 0 1
A7=B7 A6>B6 X X X X X X 1 0
A7=B7 A6<B6 X X X X X X 0 1
A7=B7 A6=B6 A5>B5 X X X X X 1 0
A7=B7 A6=B6 A5<B5 X X X X X 0 1
A7=B7 A6=B6 A5=B5 A4>B4 X X X X 1 0
A7=B7 A6=B6 A5=B5 A4<B4 X X X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3>B3 X X X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3<B3 X X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2>B2 X X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2<B2 X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1>B1 X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1<B1 X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0>B0 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0<B0 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0=B0 0 0
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Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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COMPMC8
Macro: 8-Bit Magnitude Comparator
IntroductionThis design element is an 8-bit, magnitude comparator that compares two positive Binaryweighted words A7 –A0 and B7 – B0, where A7 and B7 are the most significant bits.
This comparator is implemented using carry logic with relative location constraints to ensure efficient logicplacement.
The greater-than output (GT) is High when A>B, and the less-than output (LT) is High when A<B. When thetwo words are equal, both GT and LT are Low. Equality can be flagged with this macro by connecting bothoutputs to a NOR gate.
Logic TableInputs Outputs
A7, B7 A6, B6 A5, B5 A4, B4 A3, B3 A2, B2 A1, B1 A0, B0 GT LT
A7>B7 X X X X X X X 1 0
A7<B7 X X X X X X X 0 1
A7=B7 A6>B6 X X X X X X 1 0
A7=B7 A6<B6 X X X X X X 0 1
A7=B7 A6=B6 A5>B5 X X X X X 1 0
A7=B7 A6=B6 A5<B5 X X X X X 0 1
A7=B7 A6=B6 A5=B5 A4>B4 X X X X 1 0
A7=B7 A6=B6 A5=B5 A4<B4 X X X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3>B3 X X X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3<B3 X X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2>B2 X X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2<B2 X X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1>B1 X 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1<B1 X 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0>B0 1 0
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0<B0 0 1
A7=B7 A6=B6 A5=B5 A4=B4 A3=B3 A2=B2 A1=B1 A0=B0 0 0
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Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CR16CE
Macro: 16-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is a 16-bit cascadable, clearable, binary ripple counter with clock enable and asynchronousclear.
Larger counters can be created by connecting the last Q output of the first stage to the clock input of the nextstage. CLR and CE inputs are connected in parallel. The clock period is not affected by the overall length of aripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the number of stages and the timetC - Q is the C-to-Qz propagation delay of each stage.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Qz – Q0
1 X X 0
0 0 X No Change
0 1 ↓ Inc
z = bit width - 1
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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CR8CE
Macro: 8-Bit Negative-Edge Binary Ripple Counter with Clock Enable and Asynchronous Clear
IntroductionThis design element is an 8-bit cascadable, clearable, binary, ripple counter with clock enable and asynchronousclear.
The asynchronous clear (CLR), when High, overrides all other inputs and causes the Q outputs to go to logiclevel zero. The counter increments when the clock enable input (CE) is High during the High-to-Low clock (C)transition. The counter ignores clock transitions when CE is Low.
Larger counters can be created by connecting the last Q output of the first stage to the clock input of the nextstage. CLR and CE inputs are connected in parallel. The clock period is not affected by the overall length of aripple counter. The overall clock-to-output propagation is n(tC - Q), where n is the number of stages and the timetC - Q is the C-to-Qz propagation delay of each stage.
This counter is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE C Qz – Q0
1 X X 0
0 0 X No Change
0 1 ↓ Inc
z = bit width - 1
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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D2_4E
Macro: 2- to 4-Line Decoder/Demultiplexer with Enable
IntroductionThis design element is a decoder/demultiplexer. When the enable (E) input of this element is High, one offour active-High outputs (D3 – D0) is selected with a 2-bit binary address (A1 – A0) input. The non-selectedoutputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the Einput is the data input.
Logic TableInputs Outputs
A1 A0 E D3 D2 D1 D0
X X 0 0 0 0 0
0 0 1 0 0 0 1
0 1 1 0 0 1 0
1 0 1 0 1 0 0
1 1 1 1 0 0 0
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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D3_8E
Macro: 3- to 8-Line Decoder/Demultiplexer with Enable
IntroductionWhen the enable (E) input of the D3_8E decoder/demultiplexer is High, one of eight active-High outputs (D7 –D0) is selected with a 3-bit binary address (A2 – A0) input. The non-selected outputs are Low. Also, when the Einput is Low, all outputs are Low. In demultiplexer applications, the E input is the data input.
Logic TableInputs Outputs
A2 A1 A0 E D7 D6 D5 D4 D3 D2 D1 D0
X X X 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0 0 1
0 0 1 1 0 0 0 0 0 0 1 0
0 1 0 1 0 0 0 0 0 1 0 0
0 1 1 1 0 0 0 0 1 0 0 0
1 0 0 1 0 0 0 1 0 0 0 0
1 0 1 1 0 0 1 0 0 0 0 0
1 1 0 1 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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D4_16E
Macro: 4- to 16-Line Decoder/Demultiplexer with Enable
IntroductionThis design element is a decoder/demultiplexer. When the enable (E) input of this design element is High, oneof 16 active-High outputs (D15 – D0) is selected with a 4-bit binary address (A3 – A0) input. The non-selectedoutputs are Low. Also, when the E input is Low, all outputs are Low. In demultiplexer applications, the Einput is the data input.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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DEC_CC16
Macro: 16-Bit Active Low Decoder
IntroductionThis design element is a 16-bit decoder that is used to build wide-decoder functions. It is implemented bycascading CY_MUX elements driven by Look-Up Tables (LUTs). The C_IN pin can only be driven by the output(O) of a previous decode stage. When one or more of the inputs (A) are Low, the output is Low. When all theinputs are High and the C_IN input is High, the output is High. You can decode patterns by adding inverters toinputs.
Logic TableInputs Outputs
A0 A1 … Az C_IN O
1 1 1 1 1 1
X X X X 0 0
0 X X X X 0
X 0 X X X 0
X X X 0 X 0
z = 3 for DEC_CC4; z = 7 for DEC_CC8; z = 15 for DEC_CC16
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Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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DEC_CC4
Macro: 4-Bit Active Low Decoder
IntroductionThis design element is a 4-bit decoder that is used to build wide-decoder functions. It is implemented bycascading CY_MUX elements driven by Look-Up Tables (LUTs). The C_IN pin can only be driven by the output(O) of a previous decode stage. When one or more of the inputs (A) are Low, the output is Low. When all theinputs are High and the C_IN input is High, the output is High. You can decode patterns by adding inverters toinputs.
Logic TableInputs Outputs
A0 A1 … Az C_IN O
1 1 1 1 1 1
X X X X 0 0
0 X X X X 0
X 0 X X X 0
X X X 0 X 0
z = 3 for DEC_CC4; z = 7 for DEC_CC8; z = 15 for DEC_CC16
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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DEC_CC8
Macro: 8-Bit Active Low Decoder
IntroductionThis design element is a 8-bit decoder that is used to build wide-decoder functions. It is implemented bycascading CY_MUX elements driven by Look-Up Tables (LUTs). The C_IN pin can only be driven by the output(O) of a previous decode stage. When one or more of the inputs (A) are Low, the output is Low. When all theinputs are High and the C_IN input is High, the output is High. You can decode patterns by adding inverters toinputs.
Logic TableInputs Outputs
A0 A1 … Az C_IN O
1 1 1 1 1 1
X X X X 0 0
0 X X X X 0
X 0 X X X 0
X X X 0 X 0
z = 3 for DEC_CC4; z = 7 for DEC_CC8; z = 15 for DEC_CC16
Design Entry MethodThis design element is only for use in schematics.
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DECODE16
Macro: 16-Bit Active-Low Decoder
IntroductionThis design element is a 4-bit, active-low decoder that is implemented using combinations of LUTs and MUXCYs.
Logic TableInputs Outputs*
A0 A1 … Az O
1 1 1 1 1
0 X X X 0
X 0 X X 0
X X X 0 0
z = bitwidth -1
*A pull-up resistor must be connected to the output to establish High-level drive current.
Design Entry MethodThis design element is only for use in schematics.
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DECODE32
Macro: 32-Bit Active-Low Decoder
IntroductionThis design element is a 32-bit active-low decoder that is implemented using combinations of LUTs andMUXCYs.
Logic TableInputs Outputs
A0 A1 … Az O
1 1 1 1 1
0 X X X 0
X 0 X X 0
X X X 0 0
z = 31 for DECODE32, z = 63 for DECODE64
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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DECODE4
Macro: 4-Bit Active-Low Decoder
IntroductionThis design element is a 4-bit, active-low decoder that is implemented using combinations of LUTs and MUXCYs.
Logic TableInputs Outputs*
A0 A1 … Az O
1 1 1 1 1
0 X X X 0
X 0 X X 0
X X X 0 0
z = bitwidth -1
*A pull-up resistor must be connected to the output to establish High-level drive current.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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DECODE64
Macro: 64-Bit Active-Low Decoder
IntroductionThis design element is a 64-bit active-low decoder that is implemented using combinations of LUTs andMUXCYs.
Logic TableInputs Outputs
A0 A1 … Az O
1 1 1 1 1
0 X X X 0
X 0 X X 0
X X X 0 0
z = 31 for DECODE32, z = 63 for DECODE64
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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DECODE8
Macro: 8-Bit Active-Low Decoder
IntroductionThis design element is a 8-bit, active-low decoder that is implemented using combinations of LUTs andMUXCY’s.
Logic TableInputs Outputs*
A0 A1 … Az O
1 1 1 1 1
0 X X X 0
X 0 X X 0
X X X 0 0
z = bitwidth -1
*A pull-up resistor must be connected to the output to establish High-level drive current.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
FD
Primitive: D Flip-Flop
IntroductionThis design element is a D-type flip-flop with data input (D) and data output (Q). The data on the D inputs isloaded into the flip-flop during the Low-to-High clock (C) transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
0 ↑ 0
1 ↑ 1
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0, 1 0 Sets the initial value of Q output after configuration
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FD_1
Primitive: D Flip-Flop with Negative-Edge Clock
IntroductionThis design element is a single D-type flip-flop with data input (D) and data output (Q). The data on the (D)input is loaded into the flip-flop during the High-to-Low clock (C) transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
0 X 0
1 ↓ 1
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0, 1 0 Sets the initial value of Q output after configuration
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FD16CE
Macro: 16-Bit Data Register with Clock Enable and Asynchronous Clear
IntroductionThis design element is a 16-bit data register with clock enable and asynchronous clear. When clock enable (CE) isHigh and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the correspondingdata outputs (Q) during the Low-to-High clock (C) transition. When CLR is High, it overrides all other inputsand resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored.
This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE Dz – D0 C Qz – Q0
1 X X X 0
0 0 X X No Change
0 1 Dn ↑ Dn
z = bit-width - 1
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary Any 16-bitValue
All zeros Sets the initial value of Q output after configuration
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
FD16RE
Macro: 16-Bit Data Register with Clock Enable and Synchronous Reset
IntroductionThis design element is a 16-bit data registers. When the clock enable (CE) input is High, and the synchronousreset (R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0)during the Low-to-High clock (C) transition. When R is High, it overrides all other inputs and resets the dataoutputs (Q) Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored.
This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE Dz – D0 C Qz – Q0
1 X X ↑ 0
0 0 X X No Change
0 1 Dn ↑ Dn
z = bit-width - 1
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary Any 16-Bit Value All zeros Sets the initial value of Q output afterconfiguration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
FD4CE
Macro: 4-Bit Data Register with Clock Enable and Asynchronous Clear
IntroductionThis design element is a 4-bit data register with clock enable and asynchronous clear. When clock enable (CE) isHigh and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the correspondingdata outputs (Q) during the Low-to-High clock (C) transition. When CLR is High, it overrides all other inputsand resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored.
This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE Dz – D0 C Qz – Q0
1 X X X 0
0 0 X X No Change
0 1 Dn ↑ Dn
z = bit-width - 1
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary Any 4-Bit Value All zeros Sets the initial value of Q output afterconfiguration.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FD4RE
Macro: 4-Bit Data Register with Clock Enable and Synchronous Reset
IntroductionThis design element is a 4-bit data registers. When the clock enable (CE) input is High, and the synchronous reset(R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0) during theLow-to-High clock (C) transition. When R is High, it overrides all other inputs and resets the data outputs (Q)Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored.
This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE Dz – D0 C Qz – Q0
1 X X ↑ 0
0 0 X X No Change
0 1 Dn ↑ Dn
z = bit-width - 1
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary Any 4-Bit Value All zeros Sets the initial value of Q output after configuration.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FD8CE
Macro: 8-Bit Data Register with Clock Enable and Asynchronous Clear
IntroductionThis design element is a 8-bit data register with clock enable and asynchronous clear. When clock enable (CE) isHigh and asynchronous clear (CLR) is Low, the data on the data inputs (D) is transferred to the correspondingdata outputs (Q) during the Low-to-High clock (C) transition. When CLR is High, it overrides all other inputsand resets the data outputs (Q) Low. When CE is Low, clock transitions are ignored.
This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE Dz – D0 C Qz – Q0
1 X X X 0
0 0 X X No Change
0 1 Dn ↑ Dn
z = bit-width - 1
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary Any 8-Bit Value All zeros Sets the initial value of Q output afterconfiguration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FD8RE
Macro: 8-Bit Data Register with Clock Enable and Synchronous Reset
IntroductionThis design element is an 8-bit data register. When the clock enable (CE) input is High, and the synchronous reset(R) input is Low, the data on the data inputs (D) is transferred to the corresponding data outputs (Q0) during theLow-to-High clock (C) transition. When R is High, it overrides all other inputs and resets the data outputs (Q)Low on the Low-to-High clock transition. When CE is Low, clock transitions are ignored.
This register is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE Dz – D0 C Qz – Q0
1 X X ↑ 0
0 0 X X No Change
0 1 Dn ↑ Dn
z = bit-width - 1
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary Any 8-Bit Value Allzeros
Sets the initial value of Q output afterconfiguration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDC
Primitive: D Flip-Flop with Asynchronous Clear
IntroductionThis design element is a single D-type flip-flop with data (D) and asynchronous clear (CLR) inputs and dataoutput (Q). The asynchronous CLR, when High, overrides all other inputs and sets the (Q) output Low. The dataon the (D) input is loaded into the flip-flop when CLR is Low on the Low-to-High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR D C Q
1 X X 0
0 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0, 1 0 Sets the initial value of Q output after configuration
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDC_1
Primitive: D Flip-Flop with Negative-Edge Clock and Asynchronous Clear
IntroductionFDC_1 is a single D-type flip-flop with data input (D), asynchronous clear input (CLR), and data output (Q). Theasynchronous CLR, when active, overrides all other inputs and sets the (Q) output Low. The data on the (D)input is loaded into the flip-flop during the High-to-Low clock (C) transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR D C Q
1 X X 0
0 D ↓ D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0, 1 0 Sets the initial value of Q output after configuration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDCEPrimitive: D Flip-Flop with Clock Enable and Asynchronous Clear
IntroductionThis design element is a single D-type flip-flop with clock enable and asynchronous clear. When clock enable(CE) is High and asynchronous clear (CLR) is Low, the data on the data input (D) of this design element istransferred to the corresponding data output (Q) during the Low-to-High clock (C) transition. When CLR is High,it overrides all other inputs and resets the data output (Q) Low. When CE is Low, clock transitions are ignored.
For XC9500XL and XC9500XV devices, logic connected to the clock enable (CE) input may be implemented usingthe clock enable product term (p-term) in the macrocell, provided the logic can be completely implemented usingthe single p-term available for clock enable without requiring feedback from another macrocell. Only FDCE andFDPE flip-flops may take advantage of the clock-enable p-term.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE D C Q
1 X X X 0
0 0 X X No Change
0 1 D ↑ D
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0,1 0 Sets the initial value of Q output after configuration.
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FDCE_1Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Clear
IntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), asynchronous clear (CLR) inputs,and data output (Q). The asynchronous CLR input, when High, overrides all other inputs and sets the Q outputLow. The data on the (D) input is loaded into the flip-flop when CLR is Low and CE is High on the High-to-Lowclock (C) transition. When CE is Low, the clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE D C Q
1 X X X 0
0 0 X ? No Change
0 1 1 ? 1
0 1 0 ? 0
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0,1 0 Sets the initial valueof Q output afterconfiguration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDCPPrimitive: D Flip-Flop with Asynchronous Preset and Clear
IntroductionThis design element is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR)inputs, and data output (Q). The asynchronous PRE, when High, sets the (Q) output High; CLR, when High,resets the output Low. Data on the (D) input is loaded into the flip-flop when PRE and CLR are Low on theLow-to-High clock (C) transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR PRE D C Q
1 X X X 0
0 1 X X 1
0 0 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output afterconfiguration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
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FDCP_1Primitive: D Flip-Flop with Negative-Edge Clock and Asynchronous Preset and Clear
IntroductionThis design element is a single D-type flip-flop with data (D), asynchronous preset (PRE) and clear (CLR)inputs, and data output (Q). The asynchronous PRE, when High, sets the (Q) output High; CLR, when High,resets the output Low. Data on the (D) input is loaded into the flip-flop when PRE and CLR are Low on theHigh-to-Low clock (C) transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR PRE D C Q
1 X X X 0
0 1 X X 1
0 0 0 ↓ 0
0 0 1 ↓ 1
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0,1 0 Sets the initial value of Q output afterconfiguration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDCPEPrimitive: D Flip-Flop with Clock Enable and Asynchronous Preset and Clear
IntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE),and asynchronous clear (CLR) inputs. The asynchronous active high PRE sets the Q output High; that activehigh CLR resets the output Low and has precedence over the PRE input. Data on the D input is loaded into theflip-flop when PRE and CLR are Low and CE is High on the Low-to-High clock (C) transition. When CE is Low,the clock transitions are ignored and the previous value is retained. The FDCPE is generally implemented as aslice or IOB register within the device.
For FPGA devices, upon power-up, the initial value of this component is specified by the INIT attribute. If asubsequent GSR (Global Set/Reset) is asserted, the flop is asynchronously set to the INIT value.
Note While this device supports the use of asynchronous set and reset, it is not generally recommended tobe used for in most cases. Use of asynchronous signals pose timing issues within the design that are difficultto detect and control and also have an adverse affect on logic optimization causing a larger design that canconsume more power than if a synchronous set or reset is used.
Logic TableInputs Outputs
CLR PRE CE D C Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Change
0 0 1 D ↑ D
Port DescriptionsPort Direction Width Function
Q Output 1 Data output
C Input 1 Clock input
CE Input 1 Clock enable input
CLR Input 1 Asynchronous clear input
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Port Direction Width Function
D Input 1 Data input
PRE Input 1 Asynchronous set input
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0,1 0 Sets the initial value of Q output afterconfiguration and on GSR.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDCPE_1Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset and Clear
IntroductionFDCPE_1 is a single D-type flip-flop with data (D), clock enable (CE), asynchronous preset (PRE), andasynchronous clear (CLR) inputs and data output (Q). The asynchronous PRE, when High, sets the (Q) outputHigh; CLR, when High, resets the output Low. Data on the (D) input is loaded into the flip-flop when PRE andCLR are Low and CE is High on the High-to-Low clock (C) transition. When CE is Low, the clock transitionsare ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR PRE CE D C Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Change
0 0 1 D ↓ D
Port DescriptionsPort Direction Width Function
Q Output 1 Data output
C Input 1 Clock input
CE Input 1 Clock enable input
CLR Input 1 Asynchronous clear input
D Input 1 Data input
PRE Input 1 Asynchronous set input
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0,1 0 Sets the initial value of Q output afterconfiguration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDE
Primitive: D Flip-Flop with Clock Enable
IntroductionThis design element is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).When clock enable is High, the data on the (D) input is loaded into the flip-flop during the Low-to-High clock(C) transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
0 X X No Change
1 0 ↑ 0
1 1 ↑ 1
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDE_1
Primitive: D Flip-Flop with Negative-Edge Clock and Clock Enable
IntroductionThis design element is a single D-type flip-flop with data input (D), clock enable (CE), and data output (Q).When clock enable is High, the data on the (D) input is loaded into the flip-flop during the High-to-Low clock(C) transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
0 X X No Change
1 0 ↓ 0
1 1 ↓ 1
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDP
Primitive: D Flip-Flop with Asynchronous Preset
IntroductionThis design element is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and dataoutput (Q). The asynchronous PRE, when High, overrides all other inputs and presets the (Q) output High. Thedata on the (D) input is loaded into the flip-flop when PRE is Low on the Low-to-High clock (C) transition.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE C D Q
1 X X 1
0 ↑ D D
0 ↑ 0 0
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDP_1
Primitive: D Flip-Flop with Negative-Edge Clock and Asynchronous Preset
IntroductionThis design element is a single D-type flip-flop with data (D) and asynchronous preset (PRE) inputs and dataoutput (Q). The asynchronous PRE, when High, overrides all other inputs and presets the Q output High. Thedata on the D input is loaded into the flip-flop when PRE is Low on the High-to-Low clock (C) transition.
This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE C D Q
1 X X 1
0 ↓ D D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute Type Allowed Values Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration
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FDPEPrimitive: D Flip-Flop with Clock Enable and Asynchronous Preset
IntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset(PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the(Q) output High. Data on the (D) input is loaded into the flip-flop when PRE is Low and CE is High on theLow-to-High clock (C) transition. When CE is Low, the clock transitions are ignored.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE CE D C Q
1 X X X 1
0 0 X X No Change
0 1 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration
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FDPE_1Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and Asynchronous Preset
IntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), and asynchronous preset(PRE) inputs and data output (Q). The asynchronous PRE, when High, overrides all other inputs and sets the(Q) output High. Data on the (D) input is loaded into the flip-flop when PRE is Low and CE is High on theHigh-to-Low clock (C) transition. When CE is Low, the clock transitions are ignored.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE CE D C Q
1 X X X 1
0 0 X X No Change
0 1 D ↓ D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration
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FDR
Primitive: D Flip-Flop with Synchronous Reset
IntroductionThis design element is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output(Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Low onthe Low-to-High clock (C) transition. The data on the (D) input is loaded into the flip-flop when R is Lowduring the Low-to- High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R D C Q
1 X ↑ 0
0 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value ofQ output after configuration
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDR_1
Primitive: D Flip-Flop with Negative-Edge Clock and Synchronous Reset
IntroductionThis design element is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output(Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Low onthe High-to-Low clock (C) transition. The data on the (D) input is loaded into the flip-flop when R is Lowduring the High-to- Low clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R D C Q
1 X ↓ 0
0 D ↓ D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDRE
Primitive: D Flip-Flop with Clock Enable and Synchronous Reset
IntroductionThis design element is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputsand data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q)output Low on the Low-to-High clock (C) transition. The data on the (D) input is loaded into the flip-flop when Ris Low and CE is High during the Low-to-High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE D C Q
1 X X ↑ 0
0 0 X X No Change
0 1 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDRE_1
Primitive: D Flip-Flop with Negative-Clock Edge, Clock Enable, and Synchronous Reset
IntroductionFDRE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and dataoutput (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Lowon the High-to-Low clock (C) transition. The data on the (D) input is loaded into the flip-flop when R is Low andCE is High during the High-to-Low clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R CE D C Q
1 X X ↓ 0
0 0 X X No Change
0 1 D ↓ D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDRS
Primitive: D Flip-Flop with Synchronous Reset and Set
IntroductionFDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and dataoutput (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Lowduring the Low-to-High clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, theflip-flop is set, output High, during the Low-to-High clock transition. When R and S are Low, data on the (D)input is loaded into the flip-flop during the Low-to-High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R S D C Q
1 X X ↓ 0
0 1 X ↓ 1
0 0 D ↓ D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
IN Binary 0 or 1 0 Sets the initial value of Q output after configuration.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDRS_1Primitive: D Flip-Flop with Negative-Clock Edge and Synchronous Reset and Set
IntroductionFDRS_1 is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and dataoutput (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Lowduring the High-to-Low clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, theflip-flop is set, output High, during the High-to-Low clock transition. When R and S are Low, data on the (D)input is loaded into the flip-flop during the High-to-Low clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R S D C Q
1 X X ↓ 0
0 1 X ↓ 1
0 0 D ↓ D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output afterconfiguration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDRSE
Primitive: D Flip-Flop with Synchronous Reset and Set and Clock Enable
IntroductionFDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), clock enable (CE) inputs.The reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-Highclock transition. (Reset has precedence over Set.) When the set (S) input is High and R is Low, the flip-flop is set,output High, during the Low-to-High clock (C) transition. Data on the D input is loaded into the flip-flop whenR and S are Low and CE is High during the Low-to-High clock transition.
Upon power-up, the initial value of this component is specified by the INIT attribute. If a subsequent GSR(Global Set/Reset) is asserted, the flop is asynchronously set to the INIT value.
Logic TableInputs Outputs
R S CE D C Q
1 X X X ↑ 0
0 1 X X ↑ 1
0 0 0 X X No Change
0 0 1 1 ↑ 1
0 0 1 0 ↑ 0
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration and on GSR.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDRSE_1Primitive: D Flip-Flop with Negative-Clock Edge, Synchronous Reset and Set, and Clock Enable
IntroductionFDRSE_1 is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE)inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the (Q) outputLow during the High-to-Low clock transition. (Reset has precedence over Set.) When the set (S) input is Highand R is Low, the flip-flop is set, output High, during the High-to-Low clock (C) transition. Data on the (D) inputis loaded into the flip-flop when (R) and (S) are Low and (CE) is High during the High-to-Low clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R S CE D C Q
1 X X X ↓ 0
0 1 X X ↓ 1
0 0 0 X X No Change
0 0 1 D ↓ D
Design Entry MethodThis design element can be used in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration and on GSR.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDS
Primitive: D Flip-Flop with Synchronous Set
IntroductionFDS is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). Thesynchronous set input, when High, sets the Q output High on the Low-to-High clock (C) transition. The data onthe D input is loaded into the flip-flop when S is Low during the Low-to-High clock (C) transition.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic Table
Inputs Outputs
S D C Q
1 X ↑ 1
0 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDS_1
Primitive: D Flip-Flop with Negative-Edge Clock and Synchronous Set
IntroductionFDS is a single D-type flip-flop with data (D) and synchronous set (S) inputs and data output (Q). Thesynchronous set input, when High, sets the Q output High on the Low-to-High clock (C) transition. The data onthe D input is loaded into the flip-flop when S is Low during the Low-to-High clock (C) transition.
This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
S D C Q
1 X ↓ 1
0 D ↓ D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output afterconfiguration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDSE
Primitive: D Flip-Flop with Clock Enable and Synchronous Set
IntroductionFDSE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and data output(Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Q output Highduring the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when S is Lowand CE is High during the Low-to-High clock (C) transition.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
S CE D C Q
1 X X ↑ 1
0 0 X X No Change
0 1 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FDSE_1
Primitive: D Flip-Flop with Negative-Edge Clock, Clock Enable, and Synchronous Set
IntroductionFDSE_1 is a single D-type flip-flop with data (D), clock enable (CE), and synchronous set (S) inputs and dataoutput (Q). The synchronous set (S) input, when High, overrides the clock enable (CE) input and sets the Qoutput High during the High-to-Low clock (C) transition. The data on the D input is loaded into the flip-flopwhen S is Low and CE is High during the High-to-Low clock (C) transition.
This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
S CE D C Q
1 X X ↓ 1
0 0 X X No Change
0 1 D ↓ D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary 0 or 1 0 Sets the initial value of Q output after configuration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FJKC
Macro: J-K Flip-Flop with Asynchronous Clear
IntroductionThis design element is a single J-K-type flip-flop with J, K, and asynchronous clear (CLR) inputs and data output(Q). The asynchronous clear (CLR) input, when High, overrides all other inputs and resets the Q output Low.When CLR is Low, the output responds to the state of the J and K inputs, as shown in the following logictable, during the Low-to-High clock (C) transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR J K C Q
1 X X X 0
0 0 0 ↑ No Change
0 0 1 ↑ 0
0 1 0 ↑ 1
0 1 1 ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FJKCE
Macro: J-K Flip-Flop with Clock Enable and Asynchronous Clear
IntroductionThis design element is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous clear (CLR)inputs and data output (Q). The asynchronous clear (CLR), when High, overrides all other inputs and resets theQ output Low. When CLR is Low and CE is High, Q responds to the state of the J and K inputs, as shown in thefollowing logic table, during the Low-to-High clock transition. When CE is Low, the clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE J K C Q
1 X X X X 0
0 0 X X X No Change
0 1 0 0 X No Change
0 1 0 1 ↑ 0
0 1 1 0 ↑ 1
0 1 1 1 ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FJKP
Macro: J-K Flip-Flop with Asynchronous Preset
IntroductionThis design element is a single J-K-type flip-flop with J, K, and asynchronous preset (PRE) inputs and dataoutput (Q). The asynchronous preset (PRE) input, when High, overrides all other inputs and sets the (Q) outputHigh. When (PRE) is Low, the (Q) output responds to the state of the J and K inputs, as shown in the followinglogic table, during the Low-to-High clock transition.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE J K C Q
1 X X X 1
0 0 0 X No Change
0 0 1 ↑ 0
0 1 0 ↑ 1
0 1 1 ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FJKPEMacro: J-K Flip-Flop with Clock Enable and Asynchronous Preset
IntroductionThis design element is a single J-K-type flip-flop with J, K, clock enable (CE), and asynchronous preset (PRE)inputs and data output (Q). The asynchronous preset (PRE), when High, overrides all other inputs and sets the(Q) output High. When (PRE) is Low and (CE) is High, the (Q) output responds to the state of the J and Kinputs, as shown in the logic table, during the Low-to-High clock (C) transition. When (CE) is Low, clocktransitions are ignored.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE CE J K C Q
1 X X X X 1
0 0 X X X No Change
0 1 0 0 X No Change
0 1 0 1 ↑ 0
0 1 1 0 ↑ 1
0 1 1 1 ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FJKRSEMacro: J-K Flip-Flop with Clock Enable and Synchronous Reset and Set
IntroductionThis design element is a single J-K-type flip-flop with J, K, synchronous reset (R), synchronous set (S), and clockenable (CE) inputs and data output (Q). When synchronous reset (R) is High during the Low-to-High clock (C)transition, all other inputs are ignored and output (Q) is reset Low. When synchronous set (S) is High and (R) isLow, output (Q) is set High. When (R) and (S) are Low and (CE) is High, output (Q) responds to the state ofthe J and K inputs, according to the following logic table, during the Low-to-High clock (C) transition. When(CE) is Low, clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R S CE J K C Q
1 X X X X ↑ 0
0 1 X X X ↑ 1
0 0 0 X X X No Change
0 0 1 0 0 X No Change
0 0 1 0 1 ↑ 0
0 0 1 1 1 ↑ Toggle
0 0 1 1 0 ↑ 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FJKSREMacro: J-K Flip-Flop with Clock Enable and Synchronous Set and Reset
IntroductionThis design element is a single J-K-type flip-flop with J, K, synchronous set (S), synchronous reset (R), and clockenable (CE) inputs and data output (Q). When synchronous set (S) is High during the Low-to-High clock (C)transition, all other inputs are ignored and output (Q) is set High. When synchronous reset (R) is High and (S) isLow, output (Q) is reset Low. When (S) and (R) are Low and (CE) is High, output (Q) responds to the state ofthe J and K inputs, as shown in the following logic table, during the Low-to-High clock (C) transition. When(CE) is Low, clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
S R CE J K C Q
1 X X X X ↑ 1
0 1 X X X ↑ 0
0 0 0 X X X No Change
0 0 1 0 0 X No Change
0 0 1 0 1 ↑ 0
0 0 1 1 0 ↑ 1
0 0 1 1 1 ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FMAP
Primitive: F Function Generator Partitioning Control Symbol
IntroductionThe FMAP symbol is used to map logic to the function generator of a slice. See the appropriate CAE tool interfaceuser guide for information about specifying this attribute in your schematic design editor.
The MAP= type parameter can be used with the FMAP symbol to further define how much latitude you want togive the mapping program. The following table shows MAP option characters and their meanings
MAP Option Character Function
P Pins.
C Closed — Adding logic to or removing logic from the CLBis not allowed.
L Locked — Locking CLB pins.
O Open — Adding logic to or removing logic from the CLBis allowed.
U Unlocked — No locking on CLB pins.
Possible types of MAP parameters for FMAP are MAP=PUC, MAP=PLC, MAP=PLO, and MAP=PUO. Thedefault parameter is PUO. If one of the “open” parameters is used (PLO or PUO), only the output signalsmust be specified.
Note Currently, only PUC and PUO are observed. PLC and PLO are translated into PUC and PUO,respectively.
The FMAP symbol can be assigned to specific CLB locations using LOC attributes.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTC
Macro: Toggle Flip-Flop with Asynchronous Clear
IntroductionThis design element is a synchronous, resettable toggle flip-flop. The asynchronous clear (CLR) input, whenHigh, overrides all other inputs and resets the data output (Q) Low. The (Q) output toggles, or changes state,when the toggle enable (T) input is High and (CLR) is Low during the Low-to-High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR T C Q
1 X X 0
0 0 X No Change
0 1 ↑ Toggle
Design Entry MethodYou can instantiate this element when targeting a CPLD, but not when you are targeting an FPGA.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTCE
Macro: Toggle Flip-Flop with Clock Enable and Asynchronous Clear
IntroductionThis design element is a toggle flip-flop with toggle and clock enable and asynchronous clear. When theasynchronous clear (CLR) input is High, all other inputs are ignored and the data output (Q) is reset Low. WhenCLR is Low and toggle enable (T) and clock enable (CE) are High, Q output toggles, or changes state, during theLow-to-High clock (C) transition. When CE is Low, clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR CE T C Q
1 X X X 0
0 0 X X No Change
0 1 0 X No Change
0 1 1 ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTCLE
Macro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Clear
IntroductionThis design element is a toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. Whenthe asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When loadenable input (L) is High and CLR is Low, clock enable (CE) is overridden and the data on data input (D) isloaded into the flip-flop during the Low-to-High clock (C) transition. When toggle enable (T) and CE are Highand L and CLR are Low, output Q toggles, or changes state, during the Low- to-High clock transition. WhenCE is Low, clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE T D C Q
1 X X X X X 0
0 1 X X D ↑ D
0 0 0 X X X No Change
0 0 1 0 X X No Change
0 0 1 1 X ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTCLEX
Macro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Clear
IntroductionThis design element is a toggle/loadable flip-flop with toggle and clock enable and asynchronous clear. Whenthe asynchronous clear input (CLR) is High, all other inputs are ignored and output Q is reset Low. When loadenable input (L) is High, CLR is Low, and CE is High, the data on data input (D) is loaded into the flip-flop duringthe Low-to-High clock (C) transition. When toggle enable (T) and CE are High and L and CLR are Low, output Qtoggles, or changes state, during the Low- to-High clock transition. When CE is Low, clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR L CE T D C Q
1 X X X X X 0
0 1 X X D ↑ D
0 0 0 X X X No Change
0 0 1 0 X X No Change
0 0 1 1 X ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTP
Macro: Toggle Flip-Flop with Asynchronous Preset
IntroductionThis design element is a toggle flip-flop with toggle enable and asynchronous preset. When the asynchronouspreset (PRE) input is High, all other inputs are ignored and output (Q) is set High. When toggle-enable input (T)is High and (PRE) is Low, output (Q) toggles, or changes state, during the Low-to-High clock (C) transition.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE T C Q
1 X X 1
0 0 X No Change
0 1 ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTPE
Macro: Toggle Flip-Flop with Clock Enable and Asynchronous Preset
IntroductionThis design element is a toggle flip-flop with toggle and clock enable and asynchronous preset. When theasynchronous preset (PRE) input is High, all other inputs are ignored and output (Q) is set High. When thetoggle enable input (T) is High, clock enable (CE) is High, and (PRE) is Low, output (Q) toggles, or changes state,during the Low-to-High clock transition. When (CE) is Low, clock transitions are ignored.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE CE T C Q
1 X X X 1
0 0 X X No Change
0 1 0 X No Change
0 1 1 ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTPLEMacro: Toggle/Loadable Flip-Flop with Clock Enable and Asynchronous Preset
IntroductionThis design element is a toggle/loadable flip-flop with toggle and clock enable and asynchronous preset. Whenthe asynchronous preset input (PRE) is High, all other inputs are ignored and output (Q) is set High. When theload enable input (L) is High and (PRE) is Low, the clock enable (CE) is overridden and the data (D) is loadedinto the flip-flop during the Low-to-High clock transition. When L and PRE are Low and toggle-enable input(T) and (CE) are High, output (Q) toggles, or changes state, during the Low-to-High clock transition. When(CE) is Low, clock transitions are ignored.
For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE L CE T D C Q
1 X X X X X 1
0 1 X X D ↑ D
0 0 0 X X X No Change
0 0 1 0 X X No Change
0 0 1 1 X ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTRSE
Macro: Toggle Flip-Flop with Clock Enable and Synchronous Reset and Set
IntroductionThis design element is a toggle flip-flop with toggle and clock enable and synchronous reset and set. When thesynchronous reset input (R) is High, it overrides all other inputs and the data output (Q) is reset Low. When thesynchronous set input (S) is High and (R) is Low, clock enable input (CE) is overridden and output (Q) is setHigh. (Reset has precedence over Set.) When toggle enable input (T) and (CE) are High and (R) and (S) are Low,output (Q) toggles, or changes state, during the Low-to-High clock transition.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R S CE T C Q
1 X X X ↑ 0
0 1 X X ↑ 1
0 0 0 X X No Change
0 0 1 0 X No Change
0 0 1 1 ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTRSLE
Macro: Toggle/Loadable Flip-Flop with Clock Enable and Synchronous Reset and Set
IntroductionThis design element is a toggle/loadable flip-flop with toggle and clock enable and synchronous reset and set.The synchronous reset input (R), when High, overrides all other inputs and resets the data output (Q) Low.(Reset has precedence over Set.) When R is Low and synchronous set input (S) is High, the clock enable input(CE) is overridden and output Q is set High. When R and S are Low and load enable input (L) is High, CE isoverridden and data on data input (D) is loaded into the flip-flop during the Low-to-High clock transition. WhenR, S, and L are Low, CE is High and T is High, output Q toggles, or changes state, during the Low-to-High clocktransition. When CE is Low, clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
R S L CE T D C Q
1 0 X X X X ↑ 0
0 1 X X X X ↑ 1
0 0 1 X X 1 ↑ 1
0 0 1 X X 0 ↑ 0
0 0 0 0 X X X No Change
0 0 0 1 0 X X No Change
0 0 0 1 1 X ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTSRE
Macro: Toggle Flip-Flop with Clock Enable and Synchronous Set and Reset
IntroductionThis design element is a toggle flip-flop with toggle and clock enable and synchronous set and reset. Thesynchronous set input, when High, overrides all other inputs and sets data output (Q) High. (Set has precedenceover Reset.) When synchronous reset input (R) is High and S is Low, clock enable input (CE) is overridden andoutput Q is reset Low. When toggle enable input (T) and CE are High and S and R are Low, output Q toggles, orchanges state, during the Low-to-High clock transition. When CE is Low, clock transitions are ignored.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
S R CE T C Q
1 X X X ↑ 1
0 1 X X ↑ 0
0 0 0 X X No Change
0 0 1 0 X No Change
0 0 1 1 ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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FTSRLE
Macro: Toggle/Loadable Flip-Flop with Clock Enable and Synchronous Set and Reset
IntroductionThis design element is a toggle/loadable flip-flop with toggle and clock enable and synchronous set and reset.The synchronous set input (S), when High, overrides all other inputs and sets data output (Q) High. (Set hasprecedence over Reset.) When synchronous reset (R) is High and (S) is Low, clock enable input (CE) is overriddenand output (Q) is reset Low. When load enable input (L) is High and S and R are Low, CE is overridden and dataon data input (D) is loaded into the flip-flop during the Low-to-High clock transition. When the toggle enableinput (T) and (CE) are High and (S), (R), and (L) are Low, output (Q) toggles, or changes state, during the Low-to-High clock transition. When (CE) is Low, clock transitions are ignored.
For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaultsto active-High but can be inverted by adding an inverter in front of the GSR input of the appropriateSTARTUP_architecture symbol.
Logic TableInputs Outputs
S R L CE T D C Q
1 X X X X X ↑ 1
0 1 X X X X ↑ 0
0 0 1 X X 1 ↑ 1
0 0 1 X X 0 ↑ 0
0 0 0 0 X X X No Change
0 0 0 1 0 X X No Change
0 0 0 1 1 X ↑ Toggle
Design Entry MethodThis design element is only for use in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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GND
Primitive: Ground-Connection Signal Tag
IntroductionThe GND signal tag, or parameter, forces a net or input function to a Low logic level. A net tied to GND cannothave any other source.
When the logic-trimming software or fitter encounters a net or input function tied to GND, it removes any logicthat is disabled by the GND signal. The GND signal is only implemented when the disabled logic cannotbe removed.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IBUF
Primitive: Input Buffer
IntroductionThis design element is automatically inserted (inferred) by the synthesis tool to any signal directly connectedto a top-level input or in-out port of the design. You should generally let the synthesis tool infer this buffer.However, it can be instantiated into the design if required. In order to do so, connect the input port (I) directly tothe associated top-level input or in-out port, and connect the output port (O) to the logic sourced by that port.Modify any necessary generic maps (VHDL) or named parameter value assignment (Verilog) in order to changethe default behavior of the component.
Port DescriptionsPort Direction Width Function
O Output 1 Buffer input
I Input 1 Buffer output
Design Entry MethodThis design element can be used in schematics.
In general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It isgenerally not necessary to specify them in the source code however if desired, they be manually instantiated byeither copying the instantiation code from the ISE Libraries Guide HDL Template and paste it into the top-levelentity/module of your code. It is recommended to always put all I/O components on the top-level of the design tohelp facilitate hierarchical design methods. Connect the I port directly to the top-level input port of the designand the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IBUF16
Macro: 16-Bit Input Buffer
IntroductionInput Buffers isolate the internal circuit from the signals coming into the chip. This design element is containedin input/output blocks (IOBs) and allows the specification of the particular I/O Standard to configure the I/O. Ingeneral, an this element should be used for all single-ended data input or bidirectional pins.
Design Entry MethodThis design element can be used in schematics.
In general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It isgenerally not necessary to specify them in the source code however if desired, they be manually instantiated byeither copying the instantiation code from the ISE Libraries Guide HDL Template and paste it into the top-levelentity/module of your code. It is recommended to always put all I/O components on the top-level of the design tohelp facilitate hierarchical design methods. Connect the I port directly to the top-level input port of the designand the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IBUF4
Macro: 4-Bit Input Buffer
IntroductionInput Buffers isolate the internal circuit from the signals coming into the chip. This design element is containedin input/output blocks (IOBs) and allows the specification of the particular I/O Standard to configure the I/O. Ingeneral, an this element should be used for all single-ended data input or bidirectional pins.
Design Entry MethodThis design element can be used in schematics.
In general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It isgenerally not necessary to specify them in the source code however if desired, they be manually instantiated byeither copying the instantiation code from the ISE Libraries Guide HDL Template and paste it into the top-levelentity/module of your code. It is recommended to always put all I/O components on the top-level of the design tohelp facilitate hierarchical design methods. Connect the I port directly to the top-level input port of the designand the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IBUF8
Macro: 8-Bit Input Buffer
IntroductionInput Buffers isolate the internal circuit from the signals coming into the chip. This design element is containedin input/output blocks (IOBs) and allows the specification of the particular I/O Standard to configure the I/O. Ingeneral, an this element should be used for all single-ended data input or bidirectional pins.
Design Entry MethodThis design element can be used in schematics.
In general, this element is inferred by the synthesis tool for any specified top-level input port to the design. It isgenerally not necessary to specify them in the source code however if desired, they be manually instantiated byeither copying the instantiation code from the ISE Libraries Guide HDL Template and paste it into the top-levelentity/module of your code. It is recommended to always put all I/O components on the top-level of the design tohelp facilitate hierarchical design methods. Connect the I port directly to the top-level input port of the designand the O port to the logic in which this input is to source. Specify the desired generic/defparam values inorder to configure the proper behavior of the buffer.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IBUFG
Primitive: Dedicated Input Clock Buffer
IntroductionThe IBUFG is a dedicated input to the device which should be used to connect incoming clocks to the FPGAto the global clock routing resources. The IBUFG provides dedicated connections to the DCM_SP and BUFGproviding the minimum amount of clock delay and jitter to the device. The IBUFG input can only be driven bythe global clock pins. The IBUFG output can drive CLKIN of a DCM_SP, BUFG, or your choice of logic. TheIBUFG can be routed to your choice of logic to allow the use of the dedicated clock pins for general logic.
Port DescriptionsPort Direction Width Function
O Output 1 Clock Buffer input
I Input 1 Clock Buffer output
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to theelement.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFD
Macro: Input D Flip-Flop
IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected toan IPAD or an IOPAD (without using an IBUF). The (D) input provides data input for the flip-flop, whichsynchronizes data entering the chip. The data on input (D) is loaded into the flip-flop during the Low-to-Highclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
Dn ↑ Dn
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFD_1
Macro: Input D Flip-Flop with Inverted Clock (Asynchronous Preset)
IntroductionThis design element is a D-type flip flop which is contained in an input/output block (IOB). The input (D) of theflip-flop is connected to an IPAD or an IOPAD. The D input also provides data input for the flip-flop, whichsynchronizes data entering the chip. The D input data is loaded into the flip-flop during the High-to-Lowclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
0 ↓ 0
1 ↓ 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFD16
Macro: 16-Bit Input D Flip-Flop
IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected toan IPAD or an IOPAD (without using an IBUF). The (D) input provides data input for the flip-flop, whichsynchronizes data entering the chip. The data on input (D) is loaded into the flip-flop during the Low-to-Highclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
Dn ↑ Dn
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFD4
Macro: 4-Bit Input D Flip-Flop
IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected toan IPAD or an IOPAD (without using an IBUF). The (D) input provides data input for the flip-flop, whichsynchronizes data entering the chip. The data on input (D) is loaded into the flip-flop during the Low-to-Highclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
Dn ↑ Dn
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFD8
Macro: 8-Bit Input D Flip-Flop
IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connected toan IPAD or an IOPAD (without using an IBUF). The (D) input provides data input for the flip-flop, whichsynchronizes data entering the chip. The data on input (D) is loaded into the flip-flop during the Low-to-Highclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
Dn ↑ Dn
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFDI
Macro: Input D Flip-Flop (Asynchronous Preset)
IntroductionThis design element is a D-type flip-flop which is contained in an input/output block (IOB). The input (D) ofthe flip-flop is connected to an IPAD or an IOPAD. The D input provides data input for the flip-flop, whichsynchronizes data entering the chip. The D input data is loaded into the flip-flop during the Low-to-Highclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
D ↑ D
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFDI_1
Macro: Input D Flip-Flop with Inverted Clock (Asynchronous Preset)
IntroductionThe design element is a D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flopis connected to an IPAD or an IOPAD. The (D) input provides data input for the flip-flop, which synchronizes dataentering the chip. The data on input (D) is loaded into the flip-flop during the High-to-Low clock (C) transitionand appears at the output (Q). The clock input can be driven by internal logic or through another external pin.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
0 ↓ D
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFDX
Macro: Input D Flip-Flop with Clock Enable
IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connectedto an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, whichsynchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during theLow-to- High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logicor through another external pin. When CE is Low, flip-flop outputs do not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE Dn C Qn
1 Dn ↑ Dn
0 X X No Change
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFDX_1
Macro: Input D Flip-Flop with Inverted Clock and Clock Enable
IntroductionThis design element is a D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flopis connected to an IPAD or an IOPAD. The D input also provides data input for the flip-flop, which synchronizesdata entering the chip. When CE is High, the data on input D is loaded into the flip-flop during the High-to-Lowclock (C) transition and appears at the output (Q). The clock input can be driven by internal logic or throughanother external pin. When the CE pin is Low, the output (Q) does not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
1 D ↓ D
0 X X No Change
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFDX16
Macro: 16-Bit Input D Flip-Flops with Clock Enable
IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connectedto an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, whichsynchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during theLow-to- High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logicor through another external pin. When CE is Low, flip-flop outputs do not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE Dn C Qn
1 Dn ↑ Dn
0 X X No Change
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFDX4
Macro: 4-Bit Input D Flip-Flop with Clock Enable
IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connectedto an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, whichsynchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during theLow-to- High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logicor through another external pin. When CE is Low, flip-flop outputs do not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE Dn C Qn
1 Dn ↑ Dn
0 X X No Change
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFDX8
Macro: 8-Bit Input D Flip-Flop with Clock Enable
IntroductionThis D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flop is connectedto an IPAD or an IOPAD (without using an IBUF). The D input provides data input for the flip-flop, whichsynchronizes data entering the chip. When CE is High, the data on input D is loaded into the flip-flop during theLow-to- High clock (C) transition and appears at the output (Q). The clock input can be driven by internal logicor through another external pin. When CE is Low, flip-flop outputs do not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE Dn C Qn
1 Dn ↑ Dn
0 X X No Change
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFDXI
Macro: Input D Flip-Flop with Clock Enable (Asynchronous Preset)
IntroductionThe design element is a D-type flip-flop is contained in an input/output block (IOB). The input (D) of the flip-flopis connected to an IPAD or an IOPAD. The D input provides data input for the flip-flop, which synchronizes dataentering the chip. When CE is High, the data on input D is loaded into the flip-flop during the Low-to-High clock(C) transition and appears at the output (Q). The clock input can be driven by internal logic or through anotherexternal pin. When the CE pin is Low, the output (Q) does not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
1 D ↑ D
0 X X No Change
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IFDXI_1
Macro: Input D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)
IntroductionThe design element is a D-type flip-flop that is contained in an input/output block (IOB). The input (D) ofthe flip-flop is connected to an IPAD or an IOPAD. The (D) input provides data input for the flip-flop, whichsynchronizes data entering the chip. When (CE) is High, the data on input (D) is loaded into the flip-flop duringthe High-to-Low clock (C) transition and appears at the output (Q). The clock input can be driven by internallogic or through another external pin. When the (CE) pin is Low, the output (Q) does not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
1 D ↓ D
0 X X No Change
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILD
Macro: Transparent Input Data Latch
IntroductionThis design element is a single, transparent data latch that holds transient data entering a chip. This latch iscontained in an input/output block (IOB). The latch input (D) is connected to an IPAD or an IOPAD (withoutusing an IBUF). When the gate input (G) is High, data on the input (D) appears on the output (Q). Data on the Dinput during the High-to-Low G transition is stored in the latch.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Output
G D Q
1 D D
0 X No Change
Ø D D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILD_1
Macro: Transparent Input Data Latch with Inverted Gate
IntroductionThis design element is a transparent data latch that holds transient data entering a chip. When the gate input(G) is Low, data on the data input (D) appears on the data output (Q). Data on (D) during the Low-to-High (G)transition is stored in the latch.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
0 D D
1 X D
↑ D D
Design Entry MethodThis component is inside the IOB. It cannot be directly inferred. The most common design practice is to infera regular component and put an IOB=TRUE attribute on the component in the UCF file or in the code. Forinstance, to get an ILD_1, you would infer an ILD_1 and put the IOB = TRUE attribute on the component. Or, youcould use the map option –pri–pri–pri 000 to pack all input registers into the IOBs.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILD16
Macro: Transparent Input Data Latch
IntroductionThese design elements are multiple transparent data latches that hold transient data entering a chip. The ILDlatch is contained in an input/output block (IOB). The latch input (D) is connected to an IPAD or an IOPAD(without using an IBUF). When the gate input (G) is High, data on the inputs (D) appears on the outputs (Q).Data on the D inputs during the High-to-Low G transition is stored in the latch.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
1 D D
0 X No Change
↓ D D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILD4
Macro: Transparent Input Data Latch
IntroductionThese design elements are multiple transparent data latches that hold transient data entering a chip. The ILDlatch is contained in an input/output block (IOB). The latch input (D) is connected to an IPAD or an IOPAD(without using an IBUF). When the gate input (G) is High, data on the inputs (D) appears on the outputs (Q).Data on the D inputs during the High-to-Low G transition is stored in the latch.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
1 D D
0 X No Change
↓ D D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILD8
Macro: Transparent Input Data Latch
IntroductionThese design elements are multiple transparent data latches that hold transient data entering a chip. The ILDlatch is contained in an input/output block (IOB). The latch input (D) is connected to an IPAD or an IOPAD(without using an IBUF). When the gate input (G) is High, data on the inputs (D) appears on the outputs (Q).Data on the D inputs during the High-to-Low G transition is stored in the latch.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
1 D D
0 X No Change
↓ D D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILDI
Macro: Transparent Input Data Latch (Asynchronous Preset)
IntroductionThis design element is a transparent data latch that holds transient data entering a chip. When the gate input(G) is High, data on the input (D) appears on the output (Q). Data on the D input during the High-to-Low Gtransition is stored in the latch.
The ILDI is the input flip-flop master latch. It is possible to access two different outputs from the inputflip-flop: one that responds to the level of the clock signal and another that responds to an edge of the clocksignal. When using both outputs from the same input flip-flop, a transparent High latch (ILDI) corresponds toa falling edge-triggered flip-flop (IFDI_1). Similarly, a transparent Low latch (ILDI_1) corresponds to a risingedge-triggered flip-flop (IFDI).
The latch is asynchronously preset, output High, when power is applied.
For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaultsto active-High but can be inverted by adding an inverter in front of the GSR input of the appropriateSTARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
1 D D
0 X D
↓ D D
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILDI_1
Macro: Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)
IntroductionThis design element is a transparent data latch that holds transient data entering a chip. When the gate input(G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High Gtransition is stored in the latch.
The latch is asynchronously preset, output High, when power is applied.
For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaultsto active-High but can be inverted by adding an inverter in front of the GSR input of the appropriateSTARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
0 1 1
0 0 0
1 X D
↑ D D
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILDX
Macro: Transparent Input Data Latch
IntroductionThis design element is single or multiple transparent data latches that holds transient data entering a chip. Thelatch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).
The ILDX is the input flip-flop master latch. Two outputs can be accessed from the input flip-flop: one thatresponds to the level of the clock signal and another that responds to an edge of the clock signal. Whenusing both outputs from the same input flip-flop, a transparent High latch (ILDX) corresponds to a fallingedge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1) corresponds to a risingedge-triggered flip-flop (IFDX)
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
GE G D Q
0 X X No Change
1 0 X No Change
1 1 D D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILDX_1
Macro: Transparent Input Data Latch with Inverted Gate
IntroductionThis design element is a transparent data latch that holds transient data entering a chip. When the gate input(G) is Low, data on the data input (D) appears on the data output (Q). Data on D during the Low-to-High Gtransition is stored in the latch.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
GE G D Q
0 X X No Change
1 1 X No Change
1 0 1 1
1 0 0 0
1 ↑ D D
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILDX16
Macro: Transparent Input Data Latch
IntroductionThis design element is single or multiple transparent data latches that holds transient data entering a chip. Thelatch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).
The ILDX is the input flip-flop master latch. Two outputs can be accessed from the input flip-flop: one thatresponds to the level of the clock signal and another that responds to an edge of the clock signal. Whenusing both outputs from the same input flip-flop, a transparent High latch (ILDX) corresponds to a fallingedge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1) corresponds to a risingedge-triggered flip-flop (IFDX)
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
GE G D Q
0 X X No Change
1 0 X No Change
1 1 D D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILDX4
Macro: Transparent Input Data Latch
IntroductionThis design element is single or multiple transparent data latches that holds transient data entering a chip. Thelatch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).
The ILDX is the input flip-flop master latch. Two outputs can be accessed from the input flip-flop: one thatresponds to the level of the clock signal and another that responds to an edge of the clock signal. Whenusing both outputs from the same input flip-flop, a transparent High latch (ILDX) corresponds to a fallingedge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1) corresponds to a risingedge-triggered flip-flop (IFDX)
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
GE G D Q
0 X X No Change
1 0 X No Change
1 1 D D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILDX8
Macro: Transparent Input Data Latch
IntroductionThis design element is single or multiple transparent data latches that holds transient data entering a chip. Thelatch input (D) is connected to an IPAD or an IOPAD (without using an IBUF).
The ILDX is the input flip-flop master latch. Two outputs can be accessed from the input flip-flop: one thatresponds to the level of the clock signal and another that responds to an edge of the clock signal. Whenusing both outputs from the same input flip-flop, a transparent High latch (ILDX) corresponds to a fallingedge-triggered flip-flop (IFDX_1). Similarly, a transparent Low latch (ILDX_1) corresponds to a risingedge-triggered flip-flop (IFDX)
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
GE G D Q
0 X X No Change
1 0 X No Change
1 1 D D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILDXI
Macro: Transparent Input Data Latch (Asynchronous Preset)
IntroductionThis design element is a transparent data latch that holds transient data entering a chip. When the gate input (G)is High, data on the input (D) appears on the output (Q). Data on the (D) input during the High-to-Low (G)transition is stored in the latch.
The ILDXI is the input flip-flop master latch. Two outputs can be accessed from the input flip-flop: one thatresponds to the level of the clock signal and another that responds to an edge of the clock signal. Whenusing both outputs from the same input flip-flop, a transparent High latch (ILDXI) corresponds to a fallingedge-triggered flip-flop (IFDXI_1). Similarly, a transparent Low latch (ILDXI_1) corresponds to a risingedge-triggered flip-flop (IFDXI).
The latch is asynchronously preset, output High, when power is applied.
For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaultsto active-High but can be inverted by adding an inverter in front of the GSR input of the appropriateSTARTUP_architecture symbol.
Logic TableInputs Outputs
GE G D Q
0 X X No Change
1 0 X No Change
1 1 D D
1 ↓ D D
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ILDXI_1
Macro: Transparent Input Data Latch with Inverted Gate (Asynchronous Preset)
IntroductionThis design element is a transparent data latch that holds transient data entering a chip.
The latch is asynchronously preset, output High, when power is applied.
For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaultsto active-High but can be inverted by adding an inverter in front of the GSR input of the appropriateSTARTUP_architecture symbol.
Logic TableInputs Outputs
GE G D Q
0 X X No Change
1 1 X No Change
1 0 D D
1 ↑ D D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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INV
Primitive: Inverter
IntroductionThis design element is a single inverter that identifies signal inversions in a schematic.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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INV16
Macro: 16 Inverters
IntroductionThis design element is a multiple inverter that identifies signal inversions in a schematic.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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INV4
Macro: Four Inverters
IntroductionThis design element is a multiple inverter that identifies signal inversions in a schematic.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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INV8
Macro: Eight Inverters
IntroductionThis design element is a multiple inverter that identifies signal inversions in a schematic.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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IOBUF
Primitive: Bi-Directional Buffer
IntroductionThe design element is a bidirectional single-ended I/O Buffer used to connect internal logic to an externalbidirectional pin.
Logic TableInputs Bidirectional Outputs
T I IO O
1 X Z X
0 1 1 1
0 0 0 0
Port DescriptionsPort Direction Width Function
O Output 1 Buffer output
IO Inout 1 Buffer inout
I Input 1 Buffer input
T Input 1 3-State enable input
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
DRIVE Integer 2, 4, 6, 8, 12, 16, 24 12 Selects output drive strength (mA) forthe SelectIO buffers that use the LVTTL,LVCMOS12, LVCMOS15, LVCMOS18,LVCMOS25, or LVCMOS33 interface I/Ostandard.
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Attribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
SLEW String "SLOW", "FAST" "SLOW" Sets the output rise and fall time. See theData Sheet for recommendations of thebest setting for this attribute.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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KEEPER
Primitive: KEEPER Symbol
IntroductionThe design element is a weak keeper element that retains the value of the net connected to its bidirectional O pin.For example, if a logic 1 is being driven onto the net, KEEPER drives a weak/resistive 1 onto the net. If the netdriver is then 3-stated, KEEPER continues to drive a weak/resistive 1 onto the net.
Port DescriptionsName Direction Width Function
O Output 1-Bit Keeper output
Design Entry MethodThis design element can be used in schematics.
This element can be connected to a net in the following locations on a top-level schematic file:
• A net connected to an input IO Marker
• A net connected to both an output IO Marker and 3-statable IO element, such as an OBUFT.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LD
Primitive: Transparent Data Latch
IntroductionLD is a transparent data latch. The data output (Q) of the latch reflects the data (D) input while the gate enable(G) input is High. The data on the (D) input during the High-to-Low gate transition is stored in the latch. Thedata on the (Q) output remains unchanged as long as (G) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
1 D D
0 X No Change
↓ D D
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LD_1
Primitive: Transparent Data Latch with Inverted Gate
IntroductionThis design element is a transparent data latch with an inverted gate. The data output (Q) of the latch reflects thedata (D) input while the gate enable (G) input is Low. The data on the (D) input during the Low-to-High gatetransition is stored in the latch. The data on the (Q) output remains unchanged as long as (G) remains High.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
0 D D
1 X No Change
↑ D D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary Any 1-BitValue
All zeros Sets the initial value of Q output after configuration.
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LD16
Macro: Multiple Transparent Data Latch
IntroductionThis design element has 16 transparent data latches with a common gate enable (G). The data output (Q) of thelatch reflects the data (D) input while the gate enable (G) input is High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
1 D D
0 X No Change
↓ Dn Dn
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary Any 16-Bit Value All zeros Sets the initial value of Q output afterconfiguration
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LD16CE
Macro: Transparent Data Latch with Asynchronous Clear and Gate Enable
IntroductionThis design element has 16 transparent data latches with asynchronous clear and gate enable. When theasynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) outputs Low. (Q)reflects the data (D) inputs while the gate (G) and gate enable (GE) are High, and (CLR) is Low. If (GE) is Low,data on (D) cannot be latched. The data on the (D) input during the High-to-Low gate transition is stored in thelatch. The data on the (Q) output remains unchanged as long as (G) or (GE) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR GE G Dn Qn
1 X X X 0
0 0 X X No Change
0 1 1 Dn Dn
0 1 0 X No Change
0 1 ↓ Dn Dn
Dn = referenced input, for example, D0, D1, D2
Qn = referenced output, for example, Q0, Q1, Q2
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type AllowedValues Default Description
INIT Binary Any 16-BitValue
All zeros Sets the initial value of Q output after configuration
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LD4Macro: Multiple Transparent Data Latch
IntroductionThis design element has four transparent data latches with a common gate enable (G). The data output (Q) of thelatch reflects the data (D) input while the gate enable (G) input is High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
1 D D
0 X No Change
↓ Dn Dn
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary Any 4-Bit Value All zeros Sets the initial value of Q output after configuration
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LD4CEMacro: Transparent Data Latch with Asynchronous Clear and Gate Enable
IntroductionThis design element has 4 transparent data latches with asynchronous clear and gate enable. When theasynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) outputs Low. (Q)reflects the data (D) inputs while the gate (G) and gate enable (GE) are High, and (CLR) is Low. If (GE) is Low,data on (D) cannot be latched. The data on the (D) input during the High-to-Low gate transition is stored in thelatch. The data on the (Q) output remains unchanged as long as (G) or (GE) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR GE G Dn Qn
1 X X X 0
0 0 X X No Change
0 1 1 Dn Dn
0 1 0 X No Change
0 1 ↓ Dn Dn
Dn = referenced input, for example, D0, D1, D2
Qn = referenced output, for example, Q0, Q1, Q2
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Binary Any 4-BitValue
All zeros Sets the initial value of Q output afterconfiguration
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LD8
Macro: Multiple Transparent Data Latch
IntroductionThis design element has 8 transparent data latches with a common gate enable (G). The data output (Q) of thelatch reflects the data (D) input while the gate enable (G) input is High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
G D Q
1 D D
0 X No Change
↓ Dn Dn
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary Any 8-Bit Value All zeros Sets the initial value of Q output after configuration
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LD8CE
Macro: Transparent Data Latch with Asynchronous Clear and Gate Enable
IntroductionThis design element has 8 transparent data latches with asynchronous clear and gate enable. When theasynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) outputs Low. (Q)reflects the data (D) inputs while the gate (G) and gate enable (GE) are High, and (CLR) is Low. If (GE) is Low,data on (D) cannot be latched. The data on the (D) input during the High-to-Low gate transition is stored in thelatch. The data on the (Q) output remains unchanged as long as (G) or (GE) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR GE G Dn Qn
1 X X X 0
0 0 X X No Change
0 1 1 Dn Dn
0 1 0 X No Change
0 1 ↓ Dn Dn
Dn = referenced input, for example, D0, D1, D2
Qn = referenced output, for example, Q0, Q1, Q2
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Binary Any 8-Bit Value All zeros Sets the initial value of Q output afterconfiguration.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LDCPrimitive: Transparent Data Latch with Asynchronous Clear
IntroductionThis design element is a transparent data latch with asynchronous clear. When the asynchronous clear input(CLR) is High, it overrides the other inputs and resets the data (Q) output Low. (Q) reflects the data (D) inputwhile the gate enable (G) input is High and (CLR) is Low. The data on the (D) input during the High-to-Low gatetransition is stored in the latch. The data on the (Q) output remains unchanged as long as (G) remains low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR G D Q
1 X X 0
0 1 D D
0 0 X No Change
0 ↓ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Sets the initial value of Q output afterconfiguration.
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LDC_1Primitive: Transparent Data Latch with Asynchronous Clear and Inverted Gate
IntroductionThis design element is a transparent data latch with asynchronous clear and inverted gate. When theasynchronous clear input (CLR) is High, it overrides the other inputs (D and G) and resets the data (Q) outputLow. (Q) reflects the data (D) input while the gate enable (G) input and CLR are Low. The data on the (D) inputduring the Low-to-High gate transition is stored in the latch. The data on the (Q) output remains unchanged aslong as (G) remains High.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR G D Q
1 X X 0
0 0 D D
0 1 X No Change
0 ↑ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Sets the initial value of Q output after configuration.
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LDCEPrimitive: Transparent Data Latch with Asynchronous Clear and Gate Enable
IntroductionThis design element is a transparent data latch with asynchronous clear and gate enable. When the asynchronousclear input (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. Q reflects the data (D)input while the gate (G) input and gate enable (GE) are High and CLR is Low. If (GE) is Low, data on (D) cannotbe latched. The data on the (D) input during the High-to-Low gate transition is stored in the latch. The data onthe (Q) output remains unchanged as long as (G) or (GE) remains low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR GE G D Q
1 X X X 0
0 0 X X No Change
0 1 1 D D
0 1 0 X No Change
0 1 ↓ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Sets the initial value of Q output after configuration.
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LDCE_1Primitive: Transparent Data Latch with Asynchronous Clear, Gate Enable, and Inverted Gate
IntroductionThis design element is a transparent data latch with asynchronous clear, gate enable, and inverted gate. Whenthe asynchronous clear input (CLR) is High, it overrides the other inputs and resets the data (Q) output Low.(Q) reflects the data (D) input while the gate (G) input and (CLR) are Low and gate enable (GE) is High. Thedata on the (D) input during the Low-to-High gate transition is stored in the latch. The data on the (Q) outputremains unchanged as long as (G) remains High or (GE) remains Low
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR GE G D Q
1 X X X 0
0 0 X X No Change
0 1 0 D D
0 1 1 X No Change
0 1 ↑ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Sets the initial value of Q output afterconfiguration.
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LDCPPrimitive: Transparent Data Latch with Asynchronous Clear and Preset
IntroductionThe design element is a transparent data latch with data (D), asynchronous clear (CLR) and preset (PRE) inputs.When (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. When PRE is High and(CLR) is low, it presets the data (Q) output High. (Q) reflects the data (D) input while the gate (G) input is Highand (CLR) and PRE are Low. The data on the (D) input during the High-to-Low gate transition is stored in thelatch. The data on the (Q) output remains unchanged as long as (G) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR PRE G D Q
1 X X X 0
0 1 X X 1
0 0 1 D D
0 0 0 X No Change
0 0 ↓ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Specifies the initial value upon power-up or theassertion of GSR for the (Q) port.
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LDCP_1Primitive: Transparent Data Latch with Asynchronous Clear and Preset and Inverted Gate
IntroductionThis design element is a transparent data latch with data (D), asynchronous clear (CLR), preset (PRE) inputs, andinverted gate (G). When (CLR) is High, it overrides the other inputs and resets the data (Q) output Low. When(PRE) is High and (CLR) is Low, it presets the data (Q) output High. (Q) reflects the data (D) input while gate (G)input, (CLR), and (PRE) are Low. The data on the (D) input during the Low-to-High gate transition is stored inthe latch. The data on the (Q) output remains unchanged as long as (G) remains High.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR PRE G D Q
1 X X X 0
0 1 X X 1
0 0 0 D D
0 0 1 X No Change
0 0 ↑ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Specifies the initial value upon power-up or the assertionof GSR for the (Q) port.
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LDCPEPrimitive: Transparent Data Latch with Asynchronous Clear and Preset and Gate Enable
IntroductionThis design element is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset(PRE), and gate enable (GE). When (CLR) is High, it overrides the other inputs and resets the data (Q) outputLow. When (PRE) is High and (CLR) is Low, it presets the data (Q) output High. Q reflects the data (D) inputwhile the gate (G) input and gate enable (GE) are High and (CLR) and PRE are Low. The data on the (D) inputduring the High-to-Low gate transition is stored in the latch. The data on the Q output remains unchanged aslong as (G) or (GE) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR PRE GE G D Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Change
0 0 1 1 0 0
0 0 1 1 1 1
0 0 1 0 X No Change
0 0 1 ↓ D D
Port DescriptionsPort Direction Width Function
Q Output 1 Data Output
CLR Input 1 Asynchronous clear/reset input
D Input 1 Data Input
G Input 1 Gate Input
GE Input 1 Gate Enable Input
PRE Input 1 Asynchronous preset/set input
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Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Sets the initial value of Q output after configuration.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LDCPE_1
Primitive: Transparent Data Latch with Asynchronous Clear and Preset, Gate Enable, and InvertedGate
IntroductionThis design element is a transparent data latch with data (D), asynchronous clear (CLR), asynchronous preset(PRE), gate enable (GE), and inverted gate (G). When (CLR) is High, it overrides the other inputs and resets thedata (Q) output Low. When PRE is High and (CLR) is Low, it presets the data (Q) output High. (Q) reflects thedata (D) input while gate enable (GE) is High and gate (G), (CLR), and (PRE) are Low. The data on the (D) inputduring the Low-to-High gate transition is stored in the latch. The data on the (Q) output remains unchanged aslong as (G) is High or (GE) is Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CLR PRE GE G D Q
1 X X X X 0
0 1 X X X 1
0 0 0 X X No Change
0 0 1 0 D D
0 0 1 1 X No Change
0 0 1 ↑ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Specifies the initial value upon power-up or theassertion of GSR for the (Q) port.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LDE
Primitive: Transparent Data Latch with Gate Enable
IntroductionThis design element is a transparent data latch with data (D) and gate enable (GE) inputs. Output (Q) reflectsthe data (D) while the gate (G) input and gate enable (GE) are High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) or (GE) remains Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
GE G D Q
0 X X No Change
1 1 D D
1 0 X No Change
1 ↑ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT INTEGER 0 or 1 0 Specifies the initial value upon power-up or the assertion ofGSR for the (Q) port.
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LDE_1
Primitive: Transparent Data Latch with Gate Enable and Inverted Gate
IntroductionThis design element is a transparent data latch with data (D), gate enable (GE), and inverted gate (G). Output (Q)reflects the data (D) while the gate (G) input is Low and gate enable (GE) is High. The data on the (D) inputduring the Low-to-High gate transition is stored in the latch. The data on the (Q) output remains unchanged aslong as (G) is High or (GE) is Low.
This latch is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
GE G D Q
0 X X No Change
1 0 D D
1 1 X No Change
1 ↑ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Specifies the initial value upon power-up or theassertion of GSR for the (Q) port.
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LDPPrimitive: Transparent Data Latch with Asynchronous Preset
IntroductionThis design element is a transparent data latch with asynchronous preset (PRE). When the (PRE) input is High, itoverrides the other inputs and presets the data (Q) output High. (Q) reflects the data (D) input while gate (G)input is High and (PRE) is Low. The data on the (D) input during the High-to-Low gate transition is stored in thelatch. The data on the (Q) output remains unchanged as long as (G) remains Low.
The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditionsare simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding aninverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE G D Q
1 X X 1
0 1 0 0
0 1 1 1
0 0 X No Change
0 ↓ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT INTEGER 0 or 1 0 Specifies the initial value upon power-up or theassertion of GSR for the (Q) port.
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LDP_1Primitive: Transparent Data Latch with Asynchronous Preset and Inverted Gate
IntroductionThis design element is a transparent data latch with asynchronous preset (PRE) and inverted gate (G). When the(PRE) input is High, it overrides the other inputs and presets the data (Q) output High. (Q) reflects the data (D)input while gate (G) input and (PRE) are Low. The data on the (D) input during the Low-to-High gate transitionis stored in the latch. The data on the (Q) output remains unchanged as long as (G) remains High.
The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditionsare simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding aninverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE G D Q
1 X X 1
0 0 D D
0 1 X No Change
0 ↑ D D
Design Entry MethodThis design element is only for use in schematics.
Available Attributes
Attribute TypeAllowedValues Default Description
INIT Integer 0 or 1 0 Specifies the initial value upon power-up or the assertion of GSRfor the (Q) port.
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LDPEPrimitive: Transparent Data Latch with Asynchronous Preset and Gate Enable
IntroductionThis design element is a transparent data latch with asynchronous preset and gate enable. When theasynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. Q reflectsthe data (D) input while the gate (G) input and gate enable (GE) are High. The data on the (D) input during theHigh-to-Low gate transition is stored in the latch. The data on the (Q) output remains unchanged as long as(G) or (GE) remains Low.
The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditionsare simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding aninverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE GE G D Q
1 X X X 1
0 0 X X No Change
0 1 1 D D
0 1 0 X No Change
0 1 ↓ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Specifies the initial value upon power-up or theassertion of GSR for the (Q) port.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LDPE_1
Primitive: Transparent Data Latch with Asynchronous Preset, Gate Enable, and Inverted Gate
IntroductionThis design element is a transparent data latch with asynchronous preset, gate enable, and inverted gate. Whenthe asynchronous preset (PRE) is High, it overrides the other input and presets the data (Q) output High. (Q)reflects the data (D) input while the gate (G) and (PRE) are Low and gate enable (GE) is High. The data on the(D) input during the Low-to-High gate transition is stored in the latch. The data on the (Q) output remainsunchanged as long as (G) remains High or (GE) remains Low.
The latch is asynchronously preset, output High, when power is applied. For FPGA devices, power-on conditionsare simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be inverted by adding aninverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
PRE GE G D Q
1 X X X 1
0 0 X X No Change
0 1 0 D D
0 1 1 X No Change
0 1 ↑ D D
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Integer 0 or 1 0 Specifies the initial value upon power-up or the assertionof GSR for the (Q) port.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT1
Primitive: 1-Bit Look-Up-Table with General Output
IntroductionThis design element is a 1-bit look-up-tables (LUT) with general output (O).
An INIT attribute with an appropriate number of hexadecimal digits for the number of inputs must be attachedto the LUT to specify its function. This element provides a look-up-table version of a buffer or inverter. Theseelements are the basic building blocks. Two LUTs are available in each CLB slice; four LUTs are available in eachCLB. Multiple variants of LUTs accommodate additional types of outputs that can be used by different timingmodels for more accurate pre-layout timing estimation.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Truth Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I0 O
0 INIT[0]
1 INIT[1]
INIT = Binary number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 2-Bit Value All zeros Initializes look-up tables.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT1_D
Primitive: 1-Bit Look-Up-Table with Dual Output
IntroductionThis design element is a 1-bit look-up-table (LUT) with two functionally identical outputs, O and LO. It providesa look-up-table version of a buffer or inverter.
The O output is a general interconnect. The LO output is used to connect to another output within the same CLBslice and to the fast connect buffer. A mandatory INIT attribute, with an appropriate number of hexadecimaldigits for the number of inputs, must be attached to the LUT to specify its function.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Truth Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I0 O LO
0 INIT[0] INIT[0]
1 INIT[1] INIT[1]
INIT = Binary number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 2-Bit Value All zeros Initializes look-up tables.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT1_L
Primitive: 1-Bit Look-Up-Table with Local Output
IntroductionThis design element is a 1- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to anotheroutput within the same CLB slice and to the fast connect buffer. It provides a look-up-table version of a bufferor inverter.
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs,must be attached to the LUT to specify its function.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Truth Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I0 LO
0 INIT[0]
1 INIT[1]
INIT = Binary number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 2-Bit Value All zeros Initializes look-up tables.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT2
Primitive: 2-Bit Look-Up-Table with General Output
IntroductionThis design element is a 2-bit look-up-table (LUT) with general output (O).
An INIT attribute with an appropriate number of hexadecimal digits for the number of inputs must be attachedto the LUT to specify its function. This element provides a look-up-table version of a buffer or inverter. Theseelements are the basic building blocks. Two LUTs are available in each CLB slice; four LUTs are available in eachCLB. Multiple variants of LUTs accommodate additional types of outputs that can be used by different timingmodels for more accurate pre-layout timing estimation.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Truth Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I1 I0 O
0 0 INIT[0]
0 1 INIT[1]
1 0 INIT[2]
1 1 INIT[3]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 4-Bit Value All zeros Initializes look-up tables.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT2_DPrimitive: 2-Bit Look-Up-Table with Dual Output
IntroductionThis design element is a 2-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
The O output is a general interconnect. The LO output is used to connect to another output within the same CLBslice and to the fast connect buffer. A mandatory INIT attribute, with an appropriate number of hexadecimaldigits for the number of inputs, must be attached to the LUT to specify its function.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Truth Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I1 I0 O LO
0 0 INIT[0] INIT[0]
0 1 INIT[1] INIT[1]
1 0 INIT[2] INIT[2]
1 1 INIT[3] INIT[3]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 4-Bit Value All zeros Initializes look-up tables.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT2_LPrimitive: 2-Bit Look-Up-Table with Local Output
IntroductionThis design element is a 2- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to anotheroutput within the same CLB slice and to the fast connect buffer. It provides a look-up-table version of a bufferor inverter.
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs,must be attached to the LUT to specify its function.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Truth Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I1 I0 LO
0 0 INIT[0]
0 1 INIT[1]
1 0 INIT[2]
1 1 INIT[3]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 4-Bit Value All zeros Initializes look-up tables.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT3
Primitive: 3-Bit Look-Up-Table with General Output
IntroductionThis design element is a 3-bit look-up-table (LUT) with general output (O). A mandatory INIT attribute, withan appropriate number of hexadecimal digits for the number of inputs, must be attached to the LUT to specifyits function.
An INIT attribute with an appropriate number of hexadecimal digits for the number of inputs must be attachedto the LUT to specify its function. This element provides a look-up-table version of a buffer or inverter. Theseelements are the basic building blocks. Two LUTs are available in each CLB slice; four LUTs are available in eachCLB. Multiple variants of LUTs accommodate additional types of outputs that can be used by different timingmodels for more accurate pre-layout timing estimation.
Logic TableInputs Outputs
I2 I1 I0 O
0 0 0 INIT[0]
0 0 1 INIT[1]
0 1 0 INIT[2]
0 1 1 INIT[3]
1 0 0 INIT[4]
1 0 1 INIT[5]
1 1 0 INIT[6]
1 1 1 INIT[7]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 8-Bit Value All zeros Initializes look-up tables.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT3_D
Primitive: 3-Bit Look-Up-Table with Dual Output
IntroductionThis design element is a 3-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO.
The O output is a general interconnect. The LO output is used to connect to another output within the same CLBslice and to the fast connect buffer. A mandatory INIT attribute, with an appropriate number of hexadecimaldigits for the number of inputs, must be attached to the LUT to specify its function.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Logic Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary logic table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I2 I1 I0 O LO
0 0 0 INIT[0] INIT[0]
0 0 1 INIT[1] INIT[1]
0 1 0 INIT[2] INIT[2]
0 1 1 INIT[3] INIT[3]
1 0 0 INIT[4] INIT[4]
1 0 1 INIT[5] INIT[5]
1 1 0 INIT[6] INIT[6]
1 1 1 INIT[7] INIT[7]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 8-Bit Value All zeros Initializes look-up tables.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT3_LPrimitive: 3-Bit Look-Up-Table with Local Output
IntroductionThis design element is a 3- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to anotheroutput within the same CLB slice and to the fast connect buffer. It provides a look-up-table version of a bufferor inverter.
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs,must be attached to the LUT to specify its function.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Truth Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I2 I1 I0 LO
0 0 0 INIT[0]
0 0 1 INIT[1]
0 1 0 INIT[2]
0 1 1 INIT[3]
1 0 0 INIT[4]
1 0 1 INIT[5]
1 1 0 INIT[6]
1 1 1 INIT[7]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 8-Bit Value All zeros Initializes look-up tables.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT4
Primitive: 4-Bit Look-Up-Table with General Output
IntroductionThis design element is a 4-bit look-up-tables (LUT) with general output (O).
An INIT attribute with an appropriate number of hexadecimal digits for the number of inputs must be attachedto the LUT to specify its function. This element provides a look-up-table version of a buffer or inverter. Theseelements are the basic building blocks. Two LUTs are available in each CLB slice; four LUTs are available in eachCLB. Multiple variants of LUTs accommodate additional types of outputs that can be used by different timingmodels for more accurate pre-layout timing estimation.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Truth Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I3 I2 I1 I0 O
0 0 0 0 INIT[0]
0 0 0 1 INIT[1]
0 0 1 0 INIT[2]
0 0 1 1 INIT[3]
0 1 0 0 INIT[4]
0 1 0 1 INIT[5]
0 1 1 0 INIT[6]
0 1 1 1 INIT[7]
1 0 0 0 INIT[8]
1 0 0 1 INIT[9]
1 0 1 0 INIT[10]
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Inputs Outputs
I3 I2 I1 I0 O
1 0 1 1 INIT[11]
1 1 0 0 INIT[12]
1 1 0 1 INIT[13]
1 1 1 0 INIT14]
1 1 1 1 INIT[15]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value All zeros Initializes look-up tables.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT4_DPrimitive: 4-Bit Look-Up-Table with Dual Output
IntroductionThis design element is a 4-bit look-up-tables (LUTs) with two functionally identical outputs, O and LO
The O output is a general interconnect. The LO output is used to connect to another output within the same CLBslice and to the fast connect buffer. A mandatory INIT attribute, with an appropriate number of hexadecimaldigits for the number of inputs, must be attached to the LUT to specify its function.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Truth Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I3 I2 I1 I0 O LO
0 0 0 0 INIT[0] INIT[0]
0 0 0 1 INIT[1] INIT[1]
0 0 1 0 INIT[2] INIT[2]
0 0 1 1 INIT[3] INIT[3]
0 1 0 0 INIT[4] INIT[4]
0 1 0 1 INIT[5] INIT[5]
0 1 1 0 INIT[6] INIT[6]
0 1 1 1 INIT[7] INIT[7]
1 0 0 0 INIT[8] INIT[8]
1 0 0 1 INIT[9] INIT[9]
1 0 1 0 INIT[10] INIT[10]
1 0 1 1 INIT[11] INIT[11]
1 1 0 0 INIT[12] INIT[12]
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Inputs Outputs
I3 I2 I1 I0 O LO
1 1 0 1 INIT[13] INIT[13]
1 1 1 0 INIT14] INIT14]
1 1 1 1 INIT[15] INIT[15]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value All zeros Initializes look-up tables.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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LUT4_LPrimitive: 4-Bit Look-Up-Table with Local Output
IntroductionThis design element is a 4- bit look-up-tables (LUTs) with a local output (LO) that is used to connect to anotheroutput within the same CLB slice and to the fast connect buffer. It provides a look-up-table version of a bufferor inverter.
A mandatory INIT attribute, with an appropriate number of hexadecimal digits for the number of inputs,must be attached to the LUT to specify its function.
The INIT parameter for the FPGA LUT primitive is what gives the LUT its logical value. By default, this value iszero, thus driving the output to a zero regardless of the input values (acting as a ground). However, in mostcases a new INIT value must be determined in order to specify the logic function for the LUT primitive. Thereare at least two methods by which the LUT value can be determined:
The Truth Table Method -A common method to determine the desired INIT value for a LUT is using a truthtable. To do so, simply create a binary truth table of all possible inputs, specify the desired logic value of theoutput and then create the INIT string from those output values.
The Equation Method -Another method to determine the LUT value is to define parameters for each input tothe LUT that correspond to their listed truth value and use those to build the logic equation you are after. Thismethod is easier to understand once you have grasped the concept and more self-documenting that the abovemethod however does require the code to first specify the appropriate parameters.
Logic TableInputs Outputs
I3 I2 I1 I0 LO
0 0 0 0 INIT[0]
0 0 0 1 INIT[1]
0 0 1 0 INIT[2]
0 0 1 1 INIT[3]
0 1 0 0 INIT[4]
0 1 0 1 INIT[5]
0 1 1 0 INIT[6]
0 1 1 1 INIT[7]
1 0 0 0 INIT[8]
1 0 0 1 INIT[9]
1 0 1 0 INIT[10]
1 0 1 1 INIT[11]
1 1 0 0 INIT[12]
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Inputs Outputs
I3 I2 I1 I0 LO
1 1 0 1 INIT[13]
1 1 1 0 INIT14]
1 1 1 1 INIT[15]
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value All zeros Initializes look-up tables.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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M16_1EMacro: 16-to-1 Multiplexer with Enable
IntroductionThis design element is a 16-to-1 multiplexer with enable. When the enable input (E) is High, the M16_1Emultiplexer chooses one data bit from 16 sources (D15 – D0) under the control of the select inputs (S3 – S0). Theoutput (O) reflects the state of the selected input as shown in the logic table. When (E) is Low, the output is Low.
Logic TableInputs Outputs
E S3 S2 S1 S0 D15-D0 O
0 X X X X X 0
1 0 0 0 0 D0 D0
1 0 0 0 1 D1 D1
1 0 0 1 0 D2 D2
1 0 0 1 1 D3 D3...
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1 1 1 0 0 D12 D12
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Inputs Outputs
E S3 S2 S1 S0 D15-D0 O
1 1 1 0 1 D13 D13
1 1 1 1 0 D14 D14
1 1 1 1 1 D15 D15
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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M2_1
Macro: 2-to-1 Multiplexer
IntroductionThis design element chooses one data bit from two sources (D1 or D0) under the control of the select input (S0).The output (O) reflects the state of the selected data input. When Low, S0 selects D0 and when High, S0 selects D1.
Logic TableInputs Outputs
S0 D1 D0 O
1 D1 X D1
0 X D0 D0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
M2_1B1
Macro: 2-to-1 Multiplexer with D0 Inverted
IntroductionThis design element chooses one data bit from two sources (D1 or D0) under the control of select input (S0).When S0 is Low, the output (O) reflects the inverted value of (D0). When S0 is High, (O) reflects the state of D1.
Logic TableInputs Outputs
S0 D1 D0 O
1 1 X 1
1 0 X 0
0 X 1 0
0 X 0 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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M2_1B2
Macro: 2-to-1 Multiplexer with D0 and D1 Inverted
IntroductionThis design element chooses one data bit from two sources (D1 or D0) under the control of select input (S0). WhenS0 is Low, the output (O) reflects the inverted value of D0. When S0 is High, O reflects the inverted value of D1.
Logic TableInputs Outputs
S0 D1 D0 O
1 1 X 0
1 0 X 1
0 X 1 0
0 X 0 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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M2_1E
Macro: 2-to-1 Multiplexer with Enable
IntroductionThis design element is a 2-to-1 multiplexer with enable. When the enable input (E) is High, the M2_1E choosesone data bit from two sources (D1 or D0) under the control of select input (S0). When Low, S0 selects D0 andwhen High, S0 selects D1. When (E) is Low, the output is Low.
Logic TableInputs Outputs
E S0 D1 D0 O
0 X X X 0
1 0 X 1 1
1 0 X 0 0
1 1 1 X 1
1 1 0 X 0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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M4_1E
Macro: 4-to-1 Multiplexer with Enable
IntroductionThis design element is a 4-to-1 multiplexer with enable. When the enable input (E) is High, the M4_1Emultiplexerchooses one data bit from four sources (D3, D2, D1, or D0) under the control of the select inputs (S1 – S0). Theoutput (O) reflects the state of the selected input as shown in the logic table. When (E) is Low, the output is Low.
Logic TableInputs Outputs
E S1 S0 D0 D1 D2 D3 O
0 X X X X X X 0
1 0 0 D0 X X X D0
1 0 1 X D1 X X D1
1 1 0 X X D2 X D2
1 1 1 X X X D3 D3
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
M8_1EMacro: 8-to-1 Multiplexer with Enable
IntroductionThis design element is an 8-to-1 multiplexer with enable. When the enable input (E) is High, the M8_1Emultiplexer chooses one data bit from eight sources (D7 – D0) under the control of the select inputs (S2 – S0). Theoutput (O) reflects the state of the selected input as shown in the logic table. When (E) is Low, the output is Low.
Logic TableInputs Outputs
E S2 S1 S0 D7-D0 O
0 X X X X 0
1 0 0 0 D0 D0
1 0 0 1 D1 D1
1 0 1 0 D2 D2
1 0 1 1 D3 D3
1 1 0 0 D4 D4
1 1 0 1 D5 D5
1 1 1 0 D6 D6
1 1 1 1 D7 D7
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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MULT_AND
Primitive: Fast Multiplier AND
IntroductionThe design element is an AND component located within the slice where the two inputs are shared with the4-input LUT and the output drives into the carry logic. This added logic is especially useful for building fastand smaller multipliers however be used for other purposes as well. The I1 and I0 inputs must be connected tothe I1 and I0 inputs of the associated LUT. The LO output must be connected to the DI input of the associatedMUXCY, MUXCY_D, or MUXCY_L.
Logic TableInputs Outputs
I1 I0 LO
0 0 0
0 1 0
1 0 0
1 1 1
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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MUXCY
Primitive: 2-to-1 Multiplexer for Carry Logic with General Output
IntroductionThe direct input (DI) of a slice is connected to the (DI) input of the MUXCY. The carry in (CI) input of an LCis connected to the CI input of the MUXCY. The select input (S) of the MUXCY is driven by the output of theLook-Up Table (LUT) and configured as a MUX function. The carry out (O) of the MUXCY reflects the state of theselected input and implements the carry out function of each LC. When Low, S selects DI; when High, S selects CI.
The variants “MUXCY_D” and “MUXCY_L” provide additional types of outputs that can be used by differenttiming models for more accurate pre-layout timing estimation.
Logic TableInputs Outputs
S DI CI O
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
MUXCY_D
Primitive: 2-to-1 Multiplexer for Carry Logic with Dual Output
IntroductionThis design element implements a 1-bit, high-speed carry propagate function. One such function can beimplemented per logic cell (LC), for a total of 4-bits per configurable logic block (CLB). The direct input (DI) ofan LC is connected to the DI input of the MUXCY_D. The carry in (CI) input of an LC is connected to the CIinput of the MUXCY_D. The select input (S) of the MUX is driven by the output of the Look-Up Table (LUT) andconfigured as an XOR function. The carry out (O and LO) of the MUXCY_D reflects the state of the selected inputand implements the carry out function of each LC. When Low, S selects DI; when High, S selects CI.
Outputs O and LO are functionally identical. The O output is a general interconnect. See also “MUXCY”and “MUXCY_L”.
Logic TableInputs Outputs
S DI CI O LO
0 1 X 1 1
0 0 X 0 0
1 X 1 1 1
1 X 0 0 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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MUXCY_L
Primitive: 2-to-1 Multiplexer for Carry Logic with Local Output
IntroductionThis design element implements a 1-bit high-speed carry propagate function. One such function is implementedper logic cell (LC), for a total of 4-bits per configurable logic block (CLB). The direct input (DI) of an LC isconnected to the DI input of the MUXCY_L. The carry in (CI) input of an LC is connected to the CI input of theMUXCY_L. The select input (S) of the MUXCY_L is driven by the output of the Look-Up Table (LUT) andconfigured as an XOR function. The carry out (LO) of the MUXCY_L reflects the state of the selected input andimplements the carry out function of each (LC). When Low, (S) selects DI; when High, (S) selects (CI).
See also “MUXCY” and “MUXCY_D.”
Logic TableInputs Outputs
S DI CI LO
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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MUXF5
Primitive: 2-to-1 Look-Up Table Multiplexer with General Output
IntroductionThis design element provides a multiplexer function in a CLB slice for creating a function-of-5 lookup table or a4-to-1 multiplexer in combination with the associated lookup tables. The local outputs (LO) from the twolookup tables are connected to the I0 and I1 inputs of the MUXF5. The (S) input is driven from any internal net.When Low, (S) selects I0. When High, (S) selects I1.
The variants, “MUXF5_D” and “MUXF5_L”, provide additional types of outputs that can be used by differenttiming models for more accurate pre-layout timing estimation.
Logic TableInputs Outputs
S I0 I1 O
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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MUXF5_D
Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output
IntroductionThis design element provides a multiplexer function in a CLB slice for creating a function-of-5 lookup table or a4-to-1 multiplexer in combination with the associated lookup tables. The local outputs (LO) from the two lookuptables are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from any internal net. WhenLow, S selects I0. When High, S selects I1.
Outputs O and LO are functionally identical. The O output is a general interconnect. The LO output connects toother inputs in the same CLB slice. See also “MUXF5” and “MUXF5_L”
Logic TableInputs Outputs
S I0 I1 O LO
0 1 X 1 1
0 0 X 0 0
1 X 1 1 1
1 X 0 0 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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MUXF5_L
Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output
IntroductionThis design element provides a multiplexer function in a CLB slice for creating a function-of-5 lookup table or a4-to-1 multiplexer in combination with the associated lookup tables. The local outputs (LO) from the two lookuptables are connected to the I0 and I1 inputs of the MUXF5. The S input is driven from any internal net. WhenLow, S selects I0. When High, S selects I1.
The LO output connects to other inputs in the same CLB slice.
See also “MUXF5” and “MUXF5_D”
Logic TableInputs Output
S I0 I1 LO
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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MUXF6
Primitive: 2-to-1 Look-Up Table Multiplexer with General Output
IntroductionThis design element provides a multiplexer function in two slices for creating a function-of-6 lookup table or an8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s. The local outputs(LO) from the two MUXF5s in the CLB are connected to the I0 and I1 inputs of the MUXF6. The S input is drivenfrom any internal net. When Low, (S) selects I0. When High, (S) selects I1.
The variants, “MUXF6_D” and “MUXF6_L”, provide additional types of outputs that can be used by differenttiming models for more accurate pre-layout timing estimation.
Logic TableInputs Outputs
S I0 I1 O
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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MUXF6_D
Primitive: 2-to-1 Look-Up Table Multiplexer with Dual Output
IntroductionThis design element provides a multiplexer function in a two slices for creating a function-of-6 lookup table or an8-to-1 multiplexer in combination with the associated four lookup tables and two MUXF5s. The local outputs(LO) from the two MUXF5s in the CLB are connected to the I0 and I1 inputs of the MUXF6. The (S) input isdriven from any internal net. When Low, (S) selects I0. When High, (S) selects I1.
Outputs (O) and (LO) are functionally identical. The (O) output is a general interconnect. The (LO) outputconnects to other inputs in the same CLB slice.
Logic TableInputs Outputs
S I0 I1 O LO
0 1 X 1 1
0 0 X 0 0
1 X 1 1 1
1 X 0 0 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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MUXF6_L
Primitive: 2-to-1 Look-Up Table Multiplexer with Local Output
IntroductionThis design element provides a multiplexer function for use in creating a function-of-6 lookup table or an 8-to-1multiplexer in combination with the associated four lookup tables and two MUXF5s. The local outputs (LO)from the two MUXF5s in the (CLB) are connected to the I0 and I1 inputs of the MUXF6. The (S) input is drivenfrom any internal net. When Low, (S) selects I0. When High, (S) selects I1.
The LO output connects to other inputs in the same CLB slice.
Logic TableInputs Output
S I0 I1 LO
0 1 X 1
0 0 X 0
1 X 1 1
1 X 0 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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NAND12
Macro: 12- Input NAND Gate with Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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NAND16
Macro: 16- Input NAND Gate with Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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NAND2
Primitive: 2-Input NAND Gate with Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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NAND2B1
Primitive: 2-Input NAND Gate with 1 Inverted and 1 Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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NAND2B2
Primitive: 2-Input NAND Gate with Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND3
Primitive: 3-Input NAND Gate with Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND3B1
Primitive: 3-Input NAND Gate with 1 Inverted and 2 Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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NAND3B2
Primitive: 3-Input NAND Gate with 2 Inverted and 1 Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND3B3
Primitive: 3-Input NAND Gate with Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND4
Primitive: 4-Input NAND Gate with Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND4B1
Primitive: 4-Input NAND Gate with 1 Inverted and 3 Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND4B2
Primitive: 4-Input NAND Gate with 2 Inverted and 2 Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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NAND4B3
Primitive: 4-Input NAND Gate with 3 Inverted and 1 Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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NAND4B4
Primitive: 4-Input NAND Gate with Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND5
Primitive: 5-Input NAND Gate with Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND5B1
Primitive: 5-Input NAND Gate with 1 Inverted and 4 Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND5B2
Primitive: 5-Input NAND Gate with 2 Inverted and 3 Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND5B3
Primitive: 5-Input NAND Gate with 3 Inverted and 2 Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 389
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NAND5B4
Primitive: 5-Input NAND Gate with 4 Inverted and 1 Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
390 www.xilinx.com 10.1
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NAND5B5
Primitive: 5-Input NAND Gate with Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 391
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NAND6
Macro: 6-Input NAND Gate with Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND7
Macro: 7-Input NAND Gate with Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND8
Macro: 8-Input NAND Gate with Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NAND9
Macro: 9-Input NAND Gate with Non-Inverted Inputs
IntroductionNAND gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NANDgates of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invert inputs,use external inverters. Because each input uses a CLB resource, replace gates with unused inputs with gateshaving the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 395
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NOR12
Macro: 12-Input NOR Gate with Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR16
Macro: 16-Input NOR Gate with Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 397
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NOR2
Primitive: 2-Input NOR Gate with Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR2B1
Primitive: 2-Input NOR Gate with 1 Inverted and 1 Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 399
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NOR2B2
Primitive: 2-Input NOR Gate with Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR3
Primitive: 3-Input NOR Gate with Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR3B1
Primitive: 3-Input NOR Gate with 1 Inverted and 2 Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR3B2
Primitive: 3-Input NOR Gate with 2 Inverted and 1 Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR3B3
Primitive: 3-Input NOR Gate with Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR4
Primitive: 4-Input NOR Gate with Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR4B1
Primitive: 4-Input NOR Gate with 1 Inverted and 3 Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR4B2
Primitive: 4-Input NOR Gate with 2 Inverted and 2 Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR4B3
Primitive: 4-Input NOR Gate with 3 Inverted and 1 Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR4B4
Primitive: 4-Input NOR Gate with Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR5
Primitive: 5-Input NOR Gate with Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR5B1
Primitive: 5-Input NOR Gate with 1 Inverted and 4 Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR5B2
Primitive: 5-Input NOR Gate with 2 Inverted and 3 Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR5B3
Primitive: 5-Input NOR Gate with 3 Inverted and 2 Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR5B4
Primitive: 5-Input NOR Gate with 4 Inverted and 1 Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR5B5
Primitive: 5-Input NOR Gate with Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR6
Macro: 6-Input NOR Gate with Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR7
Macro: 7-Input NOR Gate with Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR8
Macro: 8-Input NOR Gate with Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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NOR9
Macro: 9-Input NOR Gate with Non-Inverted Inputs
IntroductionNOR gates of up to five inputs are available in any combination of inverting and non-inverting inputs. NORgates of six to nine inputs, 12 inputs, and 16 inputs are available only with non-inverting inputs. To invert someor all inputs, use external inverters. Because each input uses a CLB resource, replace gates with unused inputswith gates having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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OBUF
Primitive: Output Buffer
IntroductionThis design element is a simple output buffer used to drive output signals to the FPGA device pins that do notneed to be 3-stated (constantly driven). Either an OBUF, OBUFT, OBUFDS, or OBUFTDS must be connected toevery output port in the design.
This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists ininput/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard usedby this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
Port DescriptionsPort Direction Width Function
O Output 1 Output of OBUF to be connected directly to top-level outputport.
I Input 1 Input of OBUF. Connect to the logic driving the output port.
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OBUF16
Macro: 16-Bit Output Buffer
IntroductionThis design element is a multiple output buffer.
This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists ininput/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard usedby this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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OBUF4
Macro: 4-Bit Output Buffer
IntroductionThis design element is a multiple output buffer.
This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists ininput/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard usedby this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OBUF8
Macro: 8-Bit Output Buffer
IntroductionThis design element is a multiple output buffer.
This element isolates the internal circuit and provides drive current for signals leaving a chip. It exists ininput/output blocks (IOB). Its output (O) is connected to an OPAD or an IOPAD. The interface standard usedby this element is LVTTL. Also, this element has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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OBUFE
Macro: 3-State Output Buffer with Active-High Output Enable
IntroductionThis design element is a 3-state buffer with input I, output O, and active-High output enable (E).
When E is High, data on the inputs of the buffers is transferred to the corresponding outputs. When E is Low,the output is High impedance (off or Z state). This design element isolates the internal circuit and providesdrive current for signals leaving a chip. It is connected to an OPAD or an IOPAD, and its input is connected tothe internal circuit.
Logic TableInputs Outputs
E I O
0 X Z
1 1 1
1 0 0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OBUFE16
Macro: 16-Bit 3-State Output Buffer with Active-High Output Enable
IntroductionThis design element is a 3-state buffer with input I15-I0, output O15-O0, and active-High output enable (E).
When E is High, data on the inputs of the buffers is transferred to the corresponding outputs. When E is Low,the output is High impedance (off or Z state). This design element isolates the internal circuit and providesdrive current for signals leaving a chip. It is connected to an OPAD or an IOPAD, and its input is connected tothe internal circuit.
Logic TableInputs Outputs
E I O
0 X Z
1 1 1
1 0 0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OBUFE4
Macro: 4-Bit 3-State Output Buffer with Active-High Output Enable
IntroductionThis design element is a 3-state buffer with input I3-I0, output O3-O0, and active-High output enable (E).
When E is High, data on the inputs of the buffers is transferred to the corresponding outputs. When E is Low,the output is High impedance (off or Z state). This design element isolates the internal circuit and providesdrive current for signals leaving a chip. It is connected to an OPAD or an IOPAD, and its input is connected tothe internal circuit.
Logic TableInputs Outputs
E I O
0 X Z
1 1 1
1 0 0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OBUFE8
Macro: 8-Bit 3-State Output Buffer with Active-High Output Enable
IntroductionThis design element is a 3-state buffer with input I7-I0, output O7-O0, and active-High output enable (E).
When E is High, data on the inputs of the buffers is transferred to the corresponding outputs. When E is Low,the output is High impedance (off or Z state). This design element isolates the internal circuit and providesdrive current for signals leaving a chip. It is connected to an OPAD or an IOPAD, and its input is connected tothe internal circuit.
Logic TableInputs Outputs
E I O
0 X Z
1 1 1
1 0 0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OBUFTPrimitive: 3-State Output Buffer with Active Low Output Enable
IntroductionThis design element is a single, 3-state output buffer with input I, output O, and active-Low output enables (T).This element uses the LVTTL standard and has selectable drive and slew rates using the DRIVE and SLOW orFAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, theoutput is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is neededwith a 3-state capability, such as the case when building bidirectional I/O.
Logic TableInputs Outputs
T I O
1 X Z
0 I F
Port DescriptionsPort Direction Width Function
O Output 1 Buffer output (connect directly to top-level port)
I Input 1 Buffer input
T Input 1 3-state enable input
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OBUFT16
Macro: 16-Bit 3-State Output Buffer with Active Low Output Enable
IntroductionThis design element is a multiple, 3-state output buffer with input I, output O, and active-Low output enables(T). This element uses the LVTTL standard and has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, theoutput is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is neededwith a 3-state capability, such as the case when building bidirectional I/O.
Logic TableInputs Outputs
T I O
1 X Z
0 I F
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OBUFT4
Macro: 4-Bit 3-State Output Buffers with Active-Low Output Enable
IntroductionThis design element is a multiple, 3-state output buffer with input I, output O, and active-Low output enables(T). This element uses the LVTTL standard and has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, theoutput is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is neededwith a 3-state capability, such as the case when building bidirectional I/O.
Logic TableInputs Outputs
T I O
1 X Z
0 I F
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OBUFT8
Macro: 8-Bit 3-State Output Buffers with Active-Low Output Enable
IntroductionThis design element is a multiple, 3-state output buffer with input I, output O, and active-Low output enables(T). This element uses the LVTTL standard and has selectable drive and slew rates using the DRIVE and SLOWor FAST constraints. The defaults are DRIVE=12 mA and SLOW slew.
When T is Low, data on the inputs of the buffers is transferred to the corresponding outputs. When T is High, theoutput is high impedance (off or Z state). OBUFTs are generally used when a single-ended output is neededwith a 3-state capability, such as the case when building bidirectional I/O.
Logic TableInputs Outputs
T I O
1 X Z
0 I F
Design Entry MethodThis design element is only for use in schematics.
Available AttributesAttribute Type Allowed Values Default Description
IOSTANDARD String See Data Sheet "DEFAULT" Assigns an I/O standard to the element.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
OFD
Macro: Output D Flip-Flop
IntroductionThis design element is a single output D flip-flop.
The outputs are connected to OPADs or IOPADs. The data on the (D) inputs is loaded into the flip-flops duringthe Low-to-High clock (C) transition and appears on the (Q) outputs.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
D ↑ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFD_1
Macro: Output D Flip-Flop with Inverted Clock
IntroductionThe design element is located in an input/output block (IOB). The output (Q) of the D flip-flop is connected to anOPAD or an IOPAD. The data on the (D) input is loaded into the flip-flop during the High-to-Low clock (C)transition and appears on the (Q) output.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
D ↓ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFD16
Macro: 16-Bit Output D Flip-Flop
IntroductionThis design element is a multiple output D flip-flop.
The outputs are connected to OPADs or IOPADs. The data on the (D) inputs is loaded into the flip-flops duringthe Low-to-High clock (C) transition and appears on the (Q) outputs.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
D ↑ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFD4
Macro: 4-Bit Output D Flip-Flop
IntroductionThis design element is a multiple output D flip-flop.
The outputs are connected to OPADs or IOPADs. The data on the (D) inputs is loaded into the flip-flops duringthe Low-to-High clock (C) transition and appears on the (Q) outputs.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
D ↑ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFD8
Macro: 8-Bit Output D Flip-Flop
IntroductionThis design element is a multiple output D flip-flop.
The outputs are connected to OPADs or IOPADs. The data on the (D) inputs is loaded into the flip-flops duringthe Low-to-High clock (C) transition and appears on the (Q) outputs.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
D ↑ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDE
Macro: D Flip-Flop with Active-High Enable Output Buffers
IntroductionThis is a single D flip-flop whose output is enabled by a 3-state buffer. The flip-flop data output (Q) is connectedto the input of output buffer (OBUFE). The OBUFE output (O) is connected to an OPAD or IOPAD. The data onthe data input (D) is loaded into the flip-flop during the Low-to-High clock (C) transition. When the active-Highenable input (E) is High, the data on the flip-flop output (Q) appears on the OBUFE (O) output. When (E) isLow, the output is high impedance (Z state or Off).
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Output
E D C O
0 X X Z
1 Dn ↑ Dn
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
OFDE_1
Macro: D Flip-Flop with Active-High Enable Output Buffer and Inverted Clock
IntroductionThis design element and its output buffer are located in an input/output block (IOB). The data output of theflip-flop (Q) is connected to the input of an output buffer or OBUFE. The output of the OBUFE is connected to anOPAD or an IOPAD. The data on the data input (D) is loaded into the flip-flop on the High-to-Low clock (C)transition. When the active-High enable input (E) is High, the data on the flip-flop output (Q) appears on the (O)output. When (E) is Low, the output is high impedance (Z state or Off).
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
E D C O
0 X X Z
1 D ↓ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDE16
Macro: 16-Bit D Flip-Flop with Active-High Enable Output Buffers
IntroductionThis is a multiple D flip-flop whose outputs are enabled by 3-state buffers. The flip-flop data outputs (Q) areconnected to the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to OPADs or IOPADs.The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. Whenthe active-High enable inputs (E) are High, the data on the flip-flop outputs (Q) appears on the OBUFE outputs(O). When (E) is Low, outputs are high impedance (Z state or Off).
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
E D C O
0 X X Z
1 Dn ↑ Dn
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDE4
Macro: 4-Bit D Flip-Flop with Active-High Enable Output Buffers
IntroductionThis is a multiple D flip-flop whose outputs are enabled by 3-state buffers. The flip-flop data outputs (Q) areconnected to the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to OPADs or IOPADs.The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. Whenthe active-High enable inputs (E) are High, the data on the flip-flop outputs (Q) appears on the OBUFE outputs(O). When (E) is Low, outputs are high impedance (Z state or Off).
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
E D C O
0 X X Z
1 Dn ↑ Dn
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDE8
Macro: 8-Bit D Flip-Flop with Active-High Enable Output Buffers
IntroductionThis is a multiple D flip-flop whose outputs are enabled by 3-state buffers. The flip-flop data outputs (Q) areconnected to the inputs of output buffers (OBUFE). The OBUFE outputs (O) are connected to OPADs or IOPADs.The data on the data inputs (D) is loaded into the flip-flops during the Low-to-High clock (C) transition. Whenthe active-High enable inputs (E) are High, the data on the flip-flop outputs (Q) appears on the OBUFE outputs(O). When (E) is Low, outputs are high impedance (Z state or Off).
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
E D C O
0 X X Z
1 Dn ↑ Dn
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDI
Macro: Output D Flip-Flop (Asynchronous Preset)
IntroductionThe design element is contained in an input/output block (IOB). The output (Q) of the (D) flip-flop is connectedto an OPAD or an IOPAD. The data on the (D) input is loaded into the flip-flop during the Low-to-High clock (C)transition and appears at the output (Q).
This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
D ↑ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDI_1
Macro: Output D Flip-Flop with Inverted Clock (Asynchronous Preset)
IntroductionThis design element exists in an input/output block (IOB). The (D) flip-flop output (Q) is connected to an OPADor an IOPAD. The data on the (D) input is loaded into the flip-flop during the High-to-Low clock (C) transitionand appears on the (Q) output.
This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
D C Q
D ↓ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDT
Macro: D Flip-Flop with Active-Low 3-State Output Buffer
IntroductionThis design element is a single D flip-flops whose output is enabled by a 3-state buffer.
The data outputs (Q) of the flip-flops are connected to the inputs of output buffers (OBUFT). The outputs of theOBUFTs (O) are connected to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flopsduring the Low-to-High clock (C) transition. When the active-Low enable inputs (T) are Low, the data on theflip-flop outputs (Q) appears on the (O) outputs. When (T) is High, outputs are high impedance (Off).
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
T D C O
1 X X Z
0 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDT_1
Macro: D Flip-Flop with Active-Low 3-State Output Buffer and Inverted Clock
IntroductionThe design element and its output buffer are located in an input/output block (IOB). The flip-flop data output(Q) is connected to the input of an output buffer (OBUFT). The OBUFT output is connected to an OPAD or anIOPAD. The data on the data input (D) is loaded into the flip-flop on the High-to-Low clock (C) transition.When the active-Low enable input (T) is Low, the data on the flip-flop output (Q) appears on the (O) output.When (T) is High, the output is high impedance (Off).
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
T D C O
1 X X Z
0 D ↓ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDT16
Macro: 16-Bit D Flip-Flop with Active-Low 3-State Output Buffers
IntroductionThis design element is a multiple D flip-flop whose output are enabled by 3-state buffers.
The data outputs (Q) of the flip-flops are connected to the inputs of output buffers (OBUFT). The outputs of theOBUFTs (O) are connected to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flopsduring the Low-to-High clock (C) transition. When the active-Low enable inputs (T) are Low, the data on theflip-flop outputs (Q) appears on the (O) outputs. When (T) is High, outputs are high impedance (Off).
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
T D C O
1 X X Z
0 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDT4
Macro: 4-Bit D Flip-Flop with Active-Low 3-State Output Buffers
IntroductionThis design element is a multiple D flip-flop whose output are enabled by 3-state buffers.
The data outputs (Q) of the flip-flops are connected to the inputs of output buffers (OBUFT). The outputs of theOBUFTs (O) are connected to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flopsduring the Low-to-High clock (C) transition. When the active-Low enable inputs (T) are Low, the data on theflip-flop outputs (Q) appears on the (O) outputs. When (T) is High, outputs are high impedance (Off).
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
T D C O
1 X X Z
0 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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OFDT8
Macro: 8-Bit D Flip-Flop with Active-Low 3-State Output Buffers
IntroductionThis design element is a multiple D flip-flop whose output are enabled by 3-state buffers.
The data outputs (Q) of the flip-flops are connected to the inputs of output buffers (OBUFT). The outputs of theOBUFTs (O) are connected to OPADs or IOPADs. The data on the data inputs (D) is loaded into the flip-flopsduring the Low-to-High clock (C) transition. When the active-Low enable inputs (T) are Low, the data on theflip-flop outputs (Q) appears on the (O) outputs. When (T) is High, outputs are high impedance (Off).
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
T D C O
1 X X Z
0 D ↑ D
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDX
Macro: Output D Flip-Flop with Clock Enable
IntroductionThis design element is a single output D flip-flop. The (Q) output is connected to OPAD or IOPAD. The data onthe (D) input is loaded into the flip-flop during the Low-to-High clock (C) transition and appears on the (Q)output. When (CE) is Low, the flip-flop output does not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
1 Dn ↑ Dn
0 X X No change
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
OFDX_1
Macro: Output D Flip-Flop with Inverted Clock and Clock Enable
IntroductionThe design element is located in an input/output block (IOB). The output (Q) of the (D) flip-flop is connected toan OPAD or an IOPAD. The data on the (D) input is loaded into the flip-flop during the High-to-Low clock (C)transition and appears on the (Q) output. When the (CE) pin is Low, the output (Q) does not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
1 D ↓ D
0 X X No Change
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDX16
Macro: 16-Bit Output D Flip-Flop with Clock Enable
IntroductionThis design element is a multiple output D flip-flop. The (Q) output is connected to OPAD or IOPAD. The dataon the (D) input is loaded into the flip-flop during the Low-to-High clock (C) transition and appears on the (Q)output. When (CE) is Low, the flip-flop output does not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
1 Dn ↑ Dn
0 X X No change
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
OFDX4
Macro: 4-Bit Output D Flip-Flop with Clock Enable
IntroductionThis design element is a multiple output D flip-flop. The (Q) output is connected to OPAD or IOPAD. The dataon the (D) input is loaded into the flip-flop during the Low-to-High clock (C) transition and appears on the (Q)output. When (CE) is Low, the flip-flop output does not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
1 Dn ↑ Dn
0 X X No change
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDX8
Macro: 8-Bit Output D Flip-Flop with Clock Enable
IntroductionThis design element is a multiple output D flip-flop. The (Q) output is connected to OPAD or IOPAD. The dataon the (D) input is loaded into the flip-flop during the Low-to-High clock (C) transition and appears on the (Q)output. When (CE) is Low, the flip-flop output does not change.
This flip-flop is asynchronously cleared, outputs Low, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
1 Dn ↑ Dn
0 X X No change
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDXI
Macro: Output D Flip-Flop with Clock Enable (Asynchronous Preset)
IntroductionThe design element is contained in an input/output block (IOB). The output (Q) of the D flip-flop is connected toan OPAD or an IOPAD. The data on the (D) input is loaded into the flip-flop during the Low-to-High clock (C)transition and appears at the output (Q). When( CE) is Low, the output does not change
This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
1 D ↑ D
0 X X No Change
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OFDXI_1
Macro: Output D Flip-Flop with Inverted Clock and Clock Enable (Asynchronous Preset)
IntroductionThe design element is located in an input/output block (IOB). The D flip-flop output (Q) is connected to an OPADor an IOPAD. The data on the D input is loaded into the flip-flop during the High-to-Low clock (C) transition andappears on the Q output. When CE is Low, the output (Q) does not change.
This flip-flop is asynchronously preset, output High, when power is applied. For FPGA devices, power-onconditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can be invertedby adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
CE D C Q
1 D ↓ D
0 X X No Change
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR12
Macro: 12-Input OR Gate with Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR16
Macro: 16-Input OR Gate with Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR2
Primitive: 2-Input OR Gate with Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR2B1
Primitive: 2-Input OR Gate with 1 Inverted and 1 Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR2B2
Primitive: 2-Input OR Gate with Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR3
Primitive: 3-Input OR Gate with Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR3B1
Primitive: 3-Input OR Gate with 1 Inverted and 2 Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR3B2
Primitive: 3-Input OR Gate with 2 Inverted and 1 Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR3B3
Primitive: 3-Input OR Gate with Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR4
Primitive: 4-Input OR Gate with Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR4B1
Primitive: 4-Input OR Gate with 1 Inverted and 3 Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR4B2
Primitive: 4-Input OR Gate with 2 Inverted and 2 Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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OR4B3
Primitive: 4-Input OR Gate with 3 Inverted and 1 Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR4B4
Primitive: 4-Input OR Gate with Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR5
Primitive: 5-Input OR Gate with Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR5B1
Primitive: 5-Input OR Gate with 1 Inverted and 4 Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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OR5B2
Primitive: 5-Input OR Gate with 2 Inverted and 3 Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR5B3
Primitive: 5-Input OR Gate with 3 Inverted and 2 Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR5B4
Primitive: 5-Input OR Gate with 4 Inverted and 1 Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR5B5
Primitive: 5-Input OR Gate with Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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OR6
Macro: 6-Input OR Gate with Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR7
Macro: 7-Input OR Gate with Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR8
Macro: 8-Input OR Gate with Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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OR9
Macro: 9-Input OR Gate with Non-Inverted Inputs
IntroductionOR functions of up to five inputs are available in any combination of inverting and non-inverting inputs. ORfunctions of six to nine inputs, 12 inputs, and 16 inputs are available with only non-inverting inputs. To invertsome or all inputs, use external inverters. Because each input uses a CLB resource, replace functions with unusedinputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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PULLDOWN
Primitive: Resistor to GND for Input Pads, Open-Drain, and 3-State Outputs
IntroductionThis resistor element is connected to input, output, or bidirectional pads to guarantee a logic Low level fornodes that might float.
Port DescriptionsPort Direction Width Function
O Output 1 Pulldown output (connect directly to top level port)
Design Entry MethodThis design element can be used in schematics.
This element can be connected to a net in the following locations on a top-level schematic file:
• A net connected to an input IO Marker
• A net connected to both an output IO Marker and 3-statable IO element, such as an OBUFT.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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PULLUP
Primitive: Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs
IntroductionThis design element allows for an input, 3-state output or bi-directional port to be driven to a weak highvalue when not being driven by an internal or external source. This element establishes a High logic level foropen-drain elements and macros when all the drivers are off.
Port DescriptionsPort Direction Width Function
O Output 1 Pullup output (connect directly to top level port)
Design Entry MethodThis design element can be used in schematics.
This element can be connected to a net in the following locations on a top-level schematic file:
• A net connected to an input IO Marker
• A net connected to both an output IO Marker and 3-statable IO element, such as an OBUFT.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM16X1D
Primitive: 16-Deep by 1-Wide Static Dual Port Synchronous RAM
IntroductionThis element is a 16-word by 1-bit static dual port random access memory with synchronous write capability.The device has two address ports: the read address (DPRA3–DPRA0) and the write address (A3–A0). These twoaddress ports are asynchronous. The read address controls the location of the data driven out of the output pin(DPO), and the write address controls the destination of a valid write transaction. When the write enable (WE) isLow, transitions on the write clock (WCLK) are ignored and data stored in the RAM is not affected.
When WE is High, any positive transition on (WCLK) loads the data on the data input (D) into the word selectedby the 4-bit write address. For predictable performance, write address and data inputs must be stable before aLow-to-High (WCLK) transition. This RAM block assumes an active-High (WCLK). (WCLK) can be active-Highor active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.
The SPO output reflects the data in the memory cell addressed by A3 – A0. The DPO output reflects the datain the memory cell addressed by DPRA3–DPRA0.
Note The write process is not affected by the address on the read address port.
You can use the INIT attribute to directly specify an initial value. The value must be a hexadecimal number, forexample, INIT=ABAC. If the INIT attribute is not specified, the RAM is initialized with all zeros.
Logic TableMode selection is shown in the following logic table:
Inputs Outputs
WE (mode) WCLK D SPO DPO
0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↑ D D data_d
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Inputs Outputs
WE (mode) WCLK D SPO DPO
1 (read) ↓ X data_a data_d
data_a = word addressed by bits A3-A0
data_d = word addressed by bits DPRA3-DPRA0
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value Allzeros.
Initializes RAMs, registers, and look-uptables.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM16X1D_1
Primitive: 16-Deep by 1-Wide Static Dual Port Synchronous RAM with Negative-Edge Clock
IntroductionThis is a 16-word by 1-bit static dual port random access memory with synchronous write capability andnegative-edge clock. The device has two separate address ports: the read address (DPRA3–DPRA0) and the writeaddress (A3–A0). These two address ports are asynchronous. The read address controls the location of the datadriven out of the output pin (DPO), and the write address controls the destination of a valid write transaction.
When the write enable (WE) is set to Low, transitions on the write clock (WCLK) are ignored and data stored inthe RAM is not affected. When (WE) is High, any negative transition on (WCLK) loads the data on the datainput (D) into the word selected by the 4-bit write address. For predictable performance, write address anddata inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes an active-High(WCLK). (WCLK) can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbedinto the block.
You can initialize RAM16X1D_1 during configuration using the INIT attribute.
The SPO output reflects the data in the memory cell addressed by A3–A0. The DPO output reflects the datain the memory cell addressed by DPRA3–DPRA0.
Note The write process is not affected by the address on the read address port.
Logic TableMode selection is shown in the following logic table:
Inputs Outputs
WE (mode) WCLK D SPO DPO
0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↓ D D data_d
1 (read) ↑ X data_a data_d
data_a = word addressed by bits A3 – A0
data_d = word addressed by bits DPRA3-DPRA0
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Port DescriptionsPort Direction Width Function
DPO Output 1 Read-only 1-Bit data output
SPO Output 1 R/W 1-Bit data output
A0 Input 1 R/W address[0] input
A1 Input 1 R/W address[1] input
A2 Input 1 R/W address[2] input
A3 Input 1 R/W address[3] input
D Input 1 Write 1-Bit data input
DPRA0 Input 1 Read-only address[0] input
DPRA1 Input 1 Read-only address[1] input
DPRA2 Input 1 Read-only address[2] input
DPRA3 Input 1 Read-only address[3] input
WCLK Input 1 Write clock input
WE Input 1 Write enable input
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value All zeros Initializes RAMs, registers, and look-uptables.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM16X1SPrimitive: 16-Deep by 1-Wide Static Synchronous RAM
IntroductionThis element is a 16-word by 1-bit static random access memory with synchronous write capability. When thewrite enable (WE) is set Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM isnot affected. When WE is set High, any positive transition on WCLK loads the data on the data input (D) into theword selected by the 4-bit address (A3 – A0). This RAM block assumes an active-High WCLK. However, WCLKcan be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by thevalues on the address pins. You can initialize RAM16X1S during configuration using the INIT attribute.
Logic TableInputs Outputs
WE(mode) WCLK D O
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D D
1 (read) ↓ X Data
Data = word addressed by bits A3 – A0
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value All zeros Specifies initial contents of theRAM.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM16X1S_1
Primitive: 16-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
IntroductionThis element is a 16-word by 1-bit static random access memory with synchronous write capability andnegative-edge clock. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignoredand data stored in the RAM is not affected. When (WE) is High, any negative transition on (WCLK) loads thedata on the data input (D) into the word selected by the 4-bit address (A3 – A0). For predictable performance,address and data inputs must be stable before a High-to-Low WCLK transition. This RAM block assumes anactive-Low (WCLK). However, (WCLK) can be active-High or active-Low. Any inverter placed on the (WCLK)input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined bythe values on the address pins.
You can initialize this element during configuration using the INIT attribute.
Logic TableInputs Outputs
WE(mode) WCLK D O
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↓ D D
1 (read) ↑ X Data
Data = word addressed by bits A3 – A0
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value All zeros Specifies initial contents of theRAM.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM16X2D
Macro: 16-Deep by 2-Wide Static Dual Port Synchronous RAM
IntroductionThis element is a 16-word by 2-bit static dual port random access memory with synchronous write capability.The device has two separate address ports: the read address (DPRA3 – DPRA0) and the write address (A3 – A0).These two address ports are completely asynchronous. The read address controls the location of data driven outof the output pin (DPO1 – DPO0), and the write address controls the destination of a valid write transaction.
When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in theRAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input(D1 – D0) into the word selected by the 4-bit write address. For predictable performance, write address anddata inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-HighWCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net isabsorbed into the block.
The initial contents of this element cannot be specified directly.
The SPO output reflects the data in the memory cell addressed by A3 – A0. The DPO output reflects the datain the memory cell addressed by DPRA3 – DPRA0.
Note The write process is not affected by the address on the read address port.
Logic TableInputs Outputs
WE (mode) WCLK D1-D0 SPO1-SPO0 DPO1-DPO0
0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↑ D1 – D0 D1 – D0 data_d
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Inputs Outputs
WE (mode) WCLK D1-D0 SPO1-SPO0 DPO1-DPO0
1 (read) ↓ X data_a data_d
data_a = word addressed by bits A3 – A0
data_d = word addressed by bits DPRA3-DPRA0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM16X2S
Macro: 16-Deep by 2-Wide Static Synchronous RAM
IntroductionThis element is a 16-word by 2-bit static random access memory with synchronous write capability. When thewrite enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When WE is High, any positive transition on WCLK loads the data on the data input (D1–D0) into theword selected by the 4-bit address (A3–A0). For predictable performance, address and data inputs must be stablebefore a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK canbe active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O1–O0) is the data that is stored in the RAM at the location defined bythe values on the address pins.
You can use the INIT_xx properties to specify the initial contents of a Virtex-4 wide RAM. INIT_00 initializesthe RAM cells corresponding to the O0 output, INIT_01 initializes the cells corresponding to the O1 output,etc. For example, a RAM16X2S instance is initialized by INIT_00 and INIT_01 containing 4 hex characters each.A RAM16X8S instance is initialized by eight properties INIT_00 through INIT_07 containing 4 hex characterseach. A RAM64x2S instance is completely initialized by two properties INIT_00 and INIT_01 containing16 hex characters each.
Except for Virtex-4 devices, the initial contents of this element cannot be specified directly.
Logic TableInputs Outputs
WE (mode) WCLK D1-D0 O1-O0
0 (read) X X Data
1(read) 0 X Data
1(read) 1 X Data
1(write) ↑ D1-D0 D1-D0
1 (read) ↓ X Data
Data = word addressed by bits A3 – A0
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Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT_00 to INIT_01 Hexadecimal Any 16-Bit Value All zeros Initializes RAMs, registers, andlook-up tables.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM16X4DMacro: 16-Deep by 4-Wide Static Dual Port Synchronous RAM
IntroductionThis element is a 16-word by 4-bit static dual port random access memory with synchronous write capability.The device has two separate address ports: the read address (DPRA3 – DPRA0) and the write address (A3 – A0).These two address ports are completely asynchronous. The read address controls the location of data driven outof the output pin (DPO3 – DPO0), and the write address controls the destination of a valid write transaction.
When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in theRAM is not affected. When WE is High, any positive transition on WCLK loads the data on the data input(D3 – D0) into the word selected by the 4-bit write address. For predictable performance, write address anddata inputs must be stable before a Low-to-High WCLK transition. This RAM block assumes an active-HighWCLK. However, WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net isabsorbed into the block.
The SPO output reflects the data in the memory cell addressed by A3 – A0. The DPO output reflects the datain the memory cell addressed by DPRA3 – DPRA0.
Note The write process is not affected by the address on the read address port.
The initial contents of this element cannot be specified directly.
Logic TableInputs Outputs
WE (mode) WCLK D3-D0 SPO3-SPO0 DPO3-DPO0
0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↑ D3-D0 D3-D0 data_d
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Inputs Outputs
WE (mode) WCLK D3-D0 SPO3-SPO0 DPO3-DPO0
1 (read) ↓ X data_a data_d
data_a = word addressed by bits A3-A0
data_d = word addressed by bits DPRA3-DPRA0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM16X4S
Macro: 16-Deep by 4-Wide Static Synchronous RAM
IntroductionThis element is a 16-word by 4-bit static random access memory with synchronous write capability. When thewrite enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When WE is High, any positive transition on WCLK loads the data on the data input (D3 – D0) intothe word selected by the 4-bit address (A3 – A0). For predictable performance, address and data inputs mustbe stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However,WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O3 – O0) is the data that is stored in the RAM at the location definedby the values on the address pins.
Logic TableInputs Outputs
WE (mode) WCLK D3 – D0 O3 – O0
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D3-D0 D3-D0
1 (read) ↓ X Data
Data = word addressed by bits A3 – A0.
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT_00 to INIT_03 Hexadecimal Any 16-Bit Value All zeros INIT for bit 0 of RAM
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM16X8D
Macro: 16-Deep by 8-Wide Static Dual Port Synchronous RAM
IntroductionThis element is a 16-word by 8-bit static dual port random access memory with synchronous write capability.The device has two separate address ports: the read address (DPRA3 – DPRA0) and the write address (A3 –A0). These two address ports are completely asynchronous. The read address controls the location of datadriven out of the output pin (DPO7 – DPO0), and the write address controls the destination of a valid writetransaction. When the write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and datastored in the RAM is not affected.
When WE is High, any positive transition on WCLK loads the data on the data input (D7 – D0) into the wordselected by the 4-bit write address (A3 – A0). For predictable performance, write address and data inputs mustbe stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However,WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.
The SPO output reflects the data in the memory cell addressed by A3 – A0. The DPO output reflects the datain the memory cell addressed by DPRA3 – DPRA0.
The write process is not affected by the address on the read address port.
The initial contents of this element cannot be specified directly.
Logic TableInputs Outputs
WE (mode) WCLK D7-D0 SP7-SPO0 DPO7-DPO0
0 (read) X X data_a data_d
1 (read) 0 X data_a data_d
1 (read) 1 X data_a data_d
1 (write) ↑ D7-D0 D7-D0 data_d
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Inputs Outputs
WE (mode) WCLK D7-D0 SP7-SPO0 DPO7-DPO0
1 (read) ↓ X data_a data_d
data_a = word addressed by bits A3-A0
data_d = word addressed by bits DPRA3-DPRA0
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM16X8SMacro: 16-Deep by 8-Wide Static Synchronous RAM
IntroductionThis element is a 16-word by 8-bit static random access memory with synchronous write capability. When thewrite enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When WE is High, any positive transition on WCLK loads the data on data inputs (D7–D0) into theword selected by the 4-bit address (A3–A0). For predictable performance, address and data inputs must be stablebefore a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However, WCLK canbe active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O7–O0) is the data that is stored in the RAM at the location defined bythe values on the address pins.
Logic TableInputs Outputs
WE (mode) WCLK D7-D0 O7-O0
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D7-D0 D7-D0
1 (read) ↓ X Data
Data = word addressed by bits A3–A0
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT_00 To INIT_07 Hexadecimal Any 16-Bit Value All zeros Initializes RAMs, registers, and look-uptables.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM32X1SPrimitive: 32-Deep by 1-Wide Static Synchronous RAM
IntroductionThe design element is a 32-word by 1-bit static random access memory with synchronous write capability. Whenthe write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When (WE) is High, any positive transition on (WCLK) loads the data on the data input (D) into theword selected by the 5-bit address (A4-A0). For predictable performance, address and data inputs must be stablebefore a Low-to-High (WCLK) transition. This RAM block assumes an active-High (WCLK). However, (WCLK)can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by thevalues on the address pins. You can initialize RAM32X1S during configuration using the INIT attribute.
Logic TableInputs Outputs
WE (Mode) WCLK D O
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↓ D D
1 (read) ↑ X Data
Design Entry MethodThis design element can be used in schematics.
Available Attributes
Attribute Type Allowed Values Default Descriptions
INIT Hexadecimal Any 32-Bit Value All zeros Specifies initial contents of the RAM.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM32X1S_1Primitive: 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock
IntroductionThe design element is a 32-word by 1-bit static random access memory with synchronous write capability. Whenthe write enable is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM is notaffected. When (WE) is High, any negative transition on (WCLK) loads the data on the data input (D) into theword selected by the 5-bit address (A4-A0). For predictable performance, address and data inputs must be stablebefore a High-to-Low (WCLK) transition. This RAM block assumes an active-Low (WCLK). However, (WCLK)can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into the block.
The signal output on the data output pin (O) is the data that is stored in the RAM at the location defined by thevalues on the address pins. You can initialize RAM32X1S_1 during configuration using the INIT attribute.
Logic TableInputs Outputs
WE (Mode) WCLK D O
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↓ D D
1 (read) ↑ X Data
Data = word addressed by bits A4 – A0
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Descriptions
INIT Hexadecimal Any 32-Bit Value 0 Initializes RAMs, registers, and look-uptables.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM32X2S
Macro: 32-Deep by 2-Wide Static Synchronous RAM
IntroductionThe design element is a 32-word by 2-bit static random access memory with synchronous write capability. Whenthe write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM isnot affected. When (WE) is High, any positive transition on (WCLK) loads the data on the data input (D1-D0)into the word selected by the 5-bit address (A4-A0). For predictable performance, address and data inputs mustbe stable before a Low-to-High (WCLK) transition. This RAM block assumes an active-High (WCLK). However,(WCLK) can be active-High or active-Low. Any inverter placed on the (WCLK) input net is absorbed into theblock. The signal output on the data output pins (O1-O0) is the data that is stored in the RAM at the locationdefined by the values on the address pins.
You can use the INIT_00 and INIT_01 properties to specify the initial contents of RAM32X2S.
Logic TableInputs Outputs
WE (Mode) WCLK D O0-O1
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D1-D0 D1-D0
1 (read) ↓ X Data
Data = word addressed by bits A4 A0
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Descriptions
INIT_00 Hexadecimal Any 32-Bit Value All zeros INIT for bit 0 of RAM.
INIT_01 Hexadecimal Any 32-Bit Value All zeros INIT for bit 1 of RAM.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM32X4S
Macro: 32-Deep by 4-Wide Static Synchronous RAM
IntroductionThis design element is a 32-word by 4-bit static random access memory with synchronous write capability. Whenthe write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM isnot affected. When WE is High, any positive transition on WCLK loads the data on the data inputs (D3-D0) intothe word selected by the 5-bit address (A4-A0). For predictable performance, address and data inputs mustbe stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However,WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O3-O0) is the data that is stored in the RAM at the location defined bythe values on the address pins.
Logic TableInputs Outputs
WE WCLK D3-D0 O3-O0
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D3-D0 D3-D0
1 (read) ↓ X Data
Data = word addressed by bits A4-A0
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT_00 Hexadecimal Any 32-Bit Value All zeros INIT for bit 0 of RAM.
INIT_01 Hexadecimal Any 32-Bit Value All zeros INIT for bit 1 of RAM.
INIT_02 Hexadecimal Any 32-Bit Value All zeros INIT for bit 2 of RAM.
INIT_03 Hexadecimal Any 32-Bit Value All zeros INIT for bit 3 of RAM.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAM32X8SMacro: 32-Deep by 8-Wide Static Synchronous RAM
IntroductionThis design element is a 32-word by 8-bit static random access memory with synchronous write capability. Whenthe write enable (WE) is Low, transitions on the write clock (WCLK) are ignored and data stored in the RAM isnot affected. When WE is High, any positive transition on WCLK loads the data on the data inputs (D7 – D0) intothe word selected by the 5-bit address (A4 – A0). For predictable performance, address and data inputs mustbe stable before a Low-to-High WCLK transition. This RAM block assumes an active-High WCLK. However,WCLK can be active-High or active-Low. Any inverter placed on the WCLK input net is absorbed into the block.
The signal output on the data output pins (O7 – O0) is the data that is stored in the RAM at the location definedby the values on the address pins.
Logic TableInputs Outputs
WE (mode) WCLK D7-D0 O7-O0
0 (read) X X Data
1 (read) 0 X Data
1 (read) 1 X Data
1 (write) ↑ D7-D0 D7-D0
1 (read) ↓ X Data
Data = word addressed by bits A4 – A0
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT_00 Hexadecimal Any 32-Bit Value All zeros INIT for bit 0 of RAM.
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Attribute Type Allowed Values Default Description
INIT_01 Hexadecimal Any 32-Bit Value All zeros INIT for bit 1 of RAM.
INIT_02 Hexadecimal Any 32-Bit Value All zeros INIT for bit 2 of RAM.
INIT_03 Hexadecimal Any 32-Bit Value All zeros INIT for bit 3 of RAM.
INIT_04 Hexadecimal Any 32-Bit Value All zeros INIT for bit 4 of RAM.
INIT_05 Hexadecimal Any 32-Bit Value All zeros INIT for bit 5 of RAM.
INIT_06 Hexadecimal Any 32-Bit Value All zeros INIT for bit 6 of RAM.
INIT_07 Hexadecimal Any 32-Bit Value All zeros INIT for bit 7 of RAM.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S1Primitive: 4K-Bit Single-Port Synchronous Block RAM with Port Width Configured to 1 Bit
IntroductionThis design element is a dedicated, random access memory block with synchronous write capability. It providesthe capability for fast, discrete, large blocks of RAM in each device. This element is configured as indicated inthe following table:
Design Element Depth Width Address Bus Data Bus
RAMB4_S1 4096 1 (11:0) (0:0)
The enable (EN) pin controls read, write, and reset. When EN is Low, no data is written and the output (DO)retains the last state. When EN is High and reset (RST) is High, DO is cleared during the Low-to-High clock(CLK) transition; if write enable (WE) is High, the memory contents reflect the data at DI. When EN is Highand WE is Low, the data stored in the RAM address (ADDR) is read during the Low-to-High clock transition.When EN and WE are High, the data on the data input (DI) is loaded into the word selected by the write address(ADDR) during the Low-to-High clock transition and the data output (DO) reflects the selected (addressed)word. The above description assumes an active High EN, WE, RST, and CLK. However, the active level canbe changed by placing an inverter on the port. Any inverter placed on a RAMB4 port is absorbed into theblock and does not use a CLB resource.
This element can be initialized during configuration. Block RAM output registers are asynchronously cleared,output Low, when power is applied. The initial contents of the block RAM are not altered. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
EN RST WE CLK ADDR DI DO RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address.
RAM(addr)=RAM contents at address ADDR.
data=RAM input data.
Specifying Initial Contents of a Block RAM -
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You can use the INIT_xx attributes to specify an initial value during device configuration. The initialization ofeach of these elements is set by 16 initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a totalof 4096 bits. If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization strings arepadded with zeros to the left.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S1_S1
Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 1-bit
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
Design ElementPort ADepth
Port AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S1_S1 4096 1 (11:0) (0:0) 4096 1 (11:0) (0:0)
ADDR=address bus for the port
DI=data input bus for the port
Each port is fully synchronous with independent clock pins. All Port A input pins have setup time referencedto the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All Port Binput pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out timereferenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word. The above descriptions assume active High control pins (ENA, WEA,RSTA, CLKA, ENB, WEB, RSTB, and CLKB). However, the active level can be changed by placing an inverter onthe port. Any inverter placed on a RAMB4 port is absorbed into the block and does not use a CLB resource.
Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
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You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
1 4096 <----- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
RAMB4_S1_S16Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 1-bit and 16-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
Design ElementPort ADepth
Port AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S1_S16 4096 1 (11:0) (0:0) 256 16 (7:0) (15:0)
ADDR=address bus for the port
DI=data input bus for the port
Each port is fully synchronous with independent clock pins. All Port A input pins have setup time referencedto the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All Port Binput pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out timereferenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word. The above descriptions assume active High control pins (ENA, WEA,RSTA, CLKA, ENB, WEB, RSTB, and CLKB). However, the active level can be changed by placing an inverter onthe port. Any inverter placed on a RAMB4 port is absorbed into the block and does not use a CLB resource.
Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
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You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
1 4096 <----- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16 256 <----- 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S1_S2Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 1-bit and 2-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
Design ElementPort ADepth
Port AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S1_S2 4096 1 (11:0) (0:0) 2048 2 (10:0) (1:0)
ADDR=address bus for the port
DI=data input bus for the port
Each port is fully synchronous with independent clock pins. All Port A input pins have setup time referencedto the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All Port Binput pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out timereferenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word. The above descriptions assume active High control pins (ENA, WEA,RSTA, CLKA, ENB, WEB, RSTB, and CLKB). However, the active level can be changed by placing an inverter onthe port. Any inverter placed on a RAMB4 port is absorbed into the block and does not use a CLB resource.
Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
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About Design Elements
You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
1 4096 <----- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2 2048 <----- 7 6 5 4 3 2 1 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT_00 ToINIT_3F
Binary/Hexidecimal
Any All zeros Specifies the initial contents of the data portionof the RAM array.
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Attribute Type Allowed Values Default Description
INIT_A Binary/Hexidecimal
Any All zeros Identifies the initial value of the DOA/DOBoutput port after completing configuration. ForType, the bit width is dependent on the width ofthe A or B port of the RAM.
INIT_B Binary/Hexidecimal
Any All zeros Identifies the initial value of the DOA/DOBoutput port after completing configuration. ForType, the bit width is dependent on the width ofthe A or B port of the RAM.
INITP_00 ToINITP_07
Binary/Hexidecimal
Any All zeros Specifies the initial contents of the parity portionof the RAM array.
SIM_COLLISION_CHECK
String "ALL”, ¨NONE”,¨WARNING”, or"GENERATE_X_ONLY”
"ALL” Specifies the behavior during simulation in theevent of a data collision (data being read orwritten to the same address from both ports ofthe Ram simultaneously. "ALL" issues a warningto simulator console and generate an X or allunknown data due to the collision. This is therecommended setting. "WARNING" generatesa warning only and "GENERATE_X_ONLY"generates an X for unknown data but won’t outputthe occurrence to the simulation console. "NONE"completely ignores the error. It is suggested toonly change this attribute if you can ensure thedata generated during a collision is discarded.
SRVAL_A Binary/Hexidecimal
Any All zeros Allows the individual selection of whether theDOA/DOB output port sets (go to a one) or reset(go to a zero) upon the assertion of the RSTA pin.For Type, the bit width is dependent on the widthof the A port of the RAM.
SRVAL_B Binary/Hexidecimal
Any All zeros Allows the individual selection of whether theDOA/DOB output port sets (go to a one) or reset(go to a zero) upon the assertion of the RSTB pin.For Type, the bit width is dependent on the widthof the B port of the RAM.
WRITE_MODE_A String "WRITE_FIRST","READ_FIRST" or"NO_CHANGE”
"WRITE_FIRST”
Specifies the behavior of the DOA/DOB port upona write command to the respected port. If set to"WRITE_FIRST", the same port that is writtento displays the contents of the written data tothe outputs upon completion of the operation."READ_FIRST" displays the prior contents ofthe RAM to the output port prior to writing thenew data. "NO_CHANGE" keeps the previousvalue on the output port and won’t update theoutput port upon a write command. This is thesuggested mode if not using the read data from aparticular port of the RAM
WRITE_MODE_B String "WRITE_FIRST","READ_FIRST" or"NO_CHANGE”
"WRITE_FIRST”
Specifies the behavior of the DOA/DOB port upona write command to the respected port. If set to"WRITE_FIRST", the same port that is writtento displays the contents of the written data tothe outputs upon completion of the operation."READ_FIRST" displays the prior contents ofthe RAM to the output port prior to writing thenew data. "NO_CHANGE" keeps the previousvalue on the output port and won’t update theoutput port upon a write command. This is thesuggested mode if not using the read data from aparticular port of the RAM.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S1_S4Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 1-bit and 4-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
Design ElementPort ADepth
Port AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S1_S4 4096 1 (11:0) (0:0) 1024 4 (9:0) (3:0)
ADDR=address bus for the port
DI=data input bus for the port
Each port is fully synchronous with independent clock pins. All Port A input pins have setup time referencedto the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All Port Binput pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out timereferenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word. The above descriptions assume active High control pins (ENA, WEA,RSTA, CLKA, ENB, WEB, RSTB, and CLKB). However, the active level can be changed by placing an inverter onthe port. Any inverter placed on a RAMB4 port is absorbed into the block and does not use a CLB resource.
Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
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About Design Elements
You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
1 4096 <----- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4 1024 <----- 3 2 1 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
RAMB4_S1_S8Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 1-bit and 8-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
Design ElementPort ADepth
Port AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S1_S8 4096 1 (11:0) (0:0) 512 8 (8:0) (7:0)
ADDR=address bus for the port
DI=data input bus for the port
Each port is fully synchronous with independent clock pins. All Port A input pins have setup time referencedto the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All Port Binput pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out timereferenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word. The above descriptions assume active High control pins (ENA, WEA,RSTA, CLKA, ENB, WEB, RSTB, and CLKB). However, the active level can be changed by placing an inverter onthe port. Any inverter placed on a RAMB4 port is absorbed into the block and does not use a CLB resource.
Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
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About Design Elements
You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
1 4096 <----- 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
8 512 <----- 1 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S16Primitive: 4096-Bit Single-Port Synchronous Block RAM with Port Width Configured to 16 Bits
IntroductionThis design element is a dedicated, random access memory block with synchronous write capability. It providesthe capability for fast, discrete, large blocks of RAM in each device. This element is configured as indicated inthe following table:
Design Element Depth Width Address Bus Data Bus
RAMB4_S16 256 16 (7:0) (15:0)
The enable (EN) pin controls read, write, and reset. When EN is Low, no data is written and the output (DO)retains the last state. When EN is High and reset (RST) is High, DO is cleared during the Low-to-High clock(CLK) transition; if write enable (WE) is High, the memory contents reflect the data at DI. When EN is Highand WE is Low, the data stored in the RAM address (ADDR) is read during the Low-to-High clock transition.When EN and WE are High, the data on the data input (DI) is loaded into the word selected by the write address(ADDR) during the Low-to-High clock transition and the data output (DO) reflects the selected (addressed)word. The above description assumes an active High EN, WE, RST, and CLK. However, the active level canbe changed by placing an inverter on the port. Any inverter placed on a RAMB4 port is absorbed into theblock and does not use a CLB resource.
This element can be initialized during configuration. Block RAM output registers are asynchronously cleared,output Low, when power is applied. The initial contents of the block RAM are not altered. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
EN RST WE CLK ADDR DI DO RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address.
RAM(addr)=RAM contents at address ADDR.
data=RAM input data.
Specifying Initial Contents of a Block RAM -
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You can use the INIT_xx attributes to specify an initial value during device configuration. The initialization ofeach of these elements is set by 16 initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a totalof 4096 bits. If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization strings arepadded with zeros to the left.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S16_S16Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 16-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
Design Element Port A DepthPort AWidth
Port AADDR Port ADI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S16_S16 256 16 (7:0) (15:0) 256 16 (7:0) (15:0)
ADDR=address bus for the port
DI=data input bus for the port
All Port A input pins have setup time referenced to the CLKA pin and its data output bus DOA has a clock-to-outtime referenced to the CLKA. All Port B input pins have setup time referenced to the CLKB pin and its dataoutput bus DOB has a clock-to-out time referenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, andCLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on aRAMB4 port is absorbed into the block and does not use a CLB resource.
Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
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You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
16 256 <----- 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S2
Primitive: 4K-bit Single-Port Synchronous Block RAM with Port Width Configured to 2-bits
IntroductionThis design element is a dedicated, random access memory block with synchronous write capability. It providesthe capability for fast, discrete, large blocks of RAM in each device. This element is configured as indicated inthe following table:
Design Element Depth Width Address Bus Data Bus
RAMB4_S2 2048 2 (10:0) (1:0)
The enable (EN) pin controls read, write, and reset. When EN is Low, no data is written and the output (DO)retains the last state. When EN is High and reset (RST) is High, DO is cleared during the Low-to-High clock(CLK) transition; if write enable (WE) is High, the memory contents reflect the data at DI. When EN is Highand WE is Low, the data stored in the RAM address (ADDR) is read during the Low-to-High clock transition.When EN and WE are High, the data on the data input (DI) is loaded into the word selected by the write address(ADDR) during the Low-to-High clock transition and the data output (DO) reflects the selected (addressed)word. The above description assumes an active High EN, WE, RST, and CLK. However, the active level canbe changed by placing an inverter on the port. Any inverter placed on a RAMB4 port is absorbed into theblock and does not use a CLB resource.
This element can be initialized during configuration. Block RAM output registers are asynchronously cleared,output Low, when power is applied. The initial contents of the block RAM are not altered. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
EN RST WE CLK ADDR DI DO RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address.
RAM(addr)=RAM contents at address ADDR.
data=RAM input data.
Specifying Initial Contents of a Block RAM -
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You can use the INIT_xx attributes to specify an initial value during device configuration. The initialization ofeach of these elements is set by 16 initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a totalof 4096 bits. If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization strings arepadded with zeros to the left.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S2_S16
Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 2-bits and16-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
Design ElementPort ADepth
Port AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S2_S16 2048 2 (10:0) (1:0) 256 16 (7:0) (15:0)
ADDR=address bus for the port.
DI=data input bus for the port.
All Port A input pins have setup time referenced to the CLKA pin and its data output bus DOA has a clock-to-outtime referenced to the CLKA. All Port B input pins have setup time referenced to the CLKB pin and its dataoutput bus DOB has a clock-to-out time referenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, andCLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on aRAMB4 port is absorbed into the block and does not use a CLB resource.
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Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
2 2048 <----- 7 6 5 4 3 2 1 0
16 256 <----- 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S2_S2Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 2-bits and 2-bits
Introduction
Design ElementPort ADepth
Port AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S2_S2 2048 2 (10:0) (1:0) 2048 2 (10:0) (1:0)
ADDR=address bus for the port
DI=data input bus for the port
All Port A input pins have setup time referenced to the CLKA pin and its data output bus DOA has a clock-to-outtime referenced to the CLKA. All Port B input pins have setup time referenced to the CLKB pin and its dataoutput bus DOB has a clock-to-out time referenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, andCLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on aRAMB4 port is absorbed into the block and does not use a CLB resource.
Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
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Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.
• Start=((ADDR port+1)*(Widthport)) -1
• End=(ADDRport)*(Widthport)
Port Width Port Addresses
2 2048 <----- 7 6 5 4 3 2 1 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.
• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, thedata stored will be invalid.
• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violatingthe clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S2_S4
Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 2-bits and 4-bits
Introduction
Design Element Port A DepthPort AWidth
Port AADDR Port A DI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S2_S4 2048 2 (10:0) (1:0) 1024 4 (9:0) (3:0)
ADDR=address bus for the port.
DI=data input bus for the port.
All Port A input pins have setup time referenced to the CLKA pin and its data output bus DOA has a clock-to-outtime referenced to the CLKA. All Port B input pins have setup time referenced to the CLKB pin and its dataoutput bus DOB has a clock-to-out time referenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, andCLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on aRAMB4 port is absorbed into the block and does not use a CLB resource.
This component can be initialized during configuration. See the logic table below.
Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
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About Design Elements
You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
2 2048 <----- 7 6 5 4 3 2 1 0
4 1024 <----- 3 2 1 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S2_S8Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 2-bits and 8-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
DesignElement
Port ADepth
Port AWidth
Port AADDR Port A DI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S2_S8 2048 2 (10:0) (1:0) 512 8 (8:0) (7:0)
ADDR=address bus for the port.
DI=data input bus for the port.
All Port A input pins have setup time referenced to the CLKA pin and its data output bus DOA has a clock-to-outtime referenced to the CLKA. All Port B input pins have setup time referenced to the CLKB pin and its dataoutput bus DOB has a clock-to-out time referenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, andCLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on aRAMB4 port is absorbed into the block and does not use a CLB resource.
Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
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You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
2 2048 <----- 7 6 5 4 3 2 1 0
8 512 <----- 1 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S4Primitive: 4k-bit Single-Port Synchronous Block RAM with Port Width Configured to 4-bits
IntroductionThis design element is a dedicated, random access memory block with synchronous write capability. It providesthe capability for fast, discrete, large blocks of RAM in each device. This element is configured as indicated inthe following table:
Design Element Depth Width Address Bus Data Bus
RAMB4_S4 1024 4 (9:0) (3:0)
The enable (EN) pin controls read, write, and reset. When EN is Low, no data is written and the output (DO)retains the last state. When EN is High and reset (RST) is High, DO is cleared during the Low-to-High clock(CLK) transition; if write enable (WE) is High, the memory contents reflect the data at DI. When EN is Highand WE is Low, the data stored in the RAM address (ADDR) is read during the Low-to-High clock transition.When EN and WE are High, the data on the data input (DI) is loaded into the word selected by the write address(ADDR) during the Low-to-High clock transition and the data output (DO) reflects the selected (addressed)word. The above description assumes an active High EN, WE, RST, and CLK. However, the active level canbe changed by placing an inverter on the port. Any inverter placed on a RAMB4 port is absorbed into theblock and does not use a CLB resource.
This element can be initialized during configuration. Block RAM output registers are asynchronously cleared,output Low, when power is applied. The initial contents of the block RAM are not altered. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
EN RST WE CLK ADDR DI DO RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address.
RAM(addr)=RAM contents at address ADDR.
data=RAM input data.
Specifying Initial Contents of a Block RAM -
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You can use the INIT_xx attributes to specify an initial value during device configuration. The initialization ofeach of these elements is set by 16 initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a totalof 4096 bits. If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization strings arepadded with zeros to the left.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S4_S16
Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 4-bits and16-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
DesignElement
Port ADepth
Port AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S4_S16 1024 4 (9:0) (3:0) 256 16 (7:0) (15:0)
ADDR=address bus for the port
DI=data input bus for the port
Each port is fully synchronous with independent clock pins. All port A input pins have setup time referencedto the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All port Binput pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out timereferenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, andCLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on aRAMB4 port is absorbed into the block and does not use a CLB resource.
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Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
4 1024 <----- 3 2 1 0
16 256 <----- 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S4_S4
Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 4-bits and 4-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
DesignElement
Port ADepth
Port AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR
Port BDI
RAMB4_S4_S4 1024 4 (9:0) (3:0) 1024 4 (9:0) (3:0)
ADDR=address bus for the port
DI=data input bus for the port
Each port is fully synchronous with independent clock pins. All port A input pins have setup time referencedto the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All port Binput pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out timereferenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, andCLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on aRAMB4 port is absorbed into the block and does not use a CLB resource.
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Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.
• Start=((ADDR port+1)*(Widthport)) -1
• End=(ADDRport)*(Widthport)
Port Width Port Addresses
4 1024 <----- 3 2 1 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.
• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, thedata stored will be invalid.
• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violatingthe clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S4_S8
Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 4-bits and 8-bits
Introduction
Design Element Port A DepthPort AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR
Port BDI
RAMB4_S4_S8 1024 4 (9:0) (3:0) 512 8 (8:0) (7:0)
ADDR=address bus for the port
DI=data input bus for the port
Each port is fully synchronous with independent clock pins. All port A input pins have setup time referencedto the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All port Binput pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out timereferenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, andCLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on aRAMB4 port is absorbed into the block and does not use a CLB resource.
Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
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You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
4 1024 <----- 3 2 1 0
8 512 <----- 1 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S8Primitive: 4k-bit Single-Port Synchronous Block RAM with Port Width Configured to 8-bits
IntroductionThis design element is a dedicated, random access memory block with synchronous write capability. It providesthe capability for fast, discrete, large blocks of RAM in each device. This element is configured as indicated inthe following table:
Design Element Depth Width Address Bus Data Bus
RAMB4_S8 512 8 (8:0) (7:0)
The enable (EN) pin controls read, write, and reset. When EN is Low, no data is written and the output (DO)retains the last state. When EN is High and reset (RST) is High, DO is cleared during the Low-to-High clock(CLK) transition; if write enable (WE) is High, the memory contents reflect the data at DI. When EN is Highand WE is Low, the data stored in the RAM address (ADDR) is read during the Low-to-High clock transition.When EN and WE are High, the data on the data input (DI) is loaded into the word selected by the write address(ADDR) during the Low-to-High clock transition and the data output (DO) reflects the selected (addressed)word. The above description assumes an active High EN, WE, RST, and CLK. However, the active level canbe changed by placing an inverter on the port. Any inverter placed on a RAMB4 port is absorbed into theblock and does not use a CLB resource.
This element can be initialized during configuration. Block RAM output registers are asynchronously cleared,output Low, when power is applied. The initial contents of the block RAM are not altered. For FPGA devices,power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active-High but can beinverted by adding an inverter in front of the GSR input of the appropriate STARTUP_architecture symbol.
Logic TableInputs Outputs
EN RST WE CLK ADDR DI DO RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address.
RAM(addr)=RAM contents at address ADDR.
data=RAM input data.
Specifying Initial Contents of a Block RAM -
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You can use the INIT_xx attributes to specify an initial value during device configuration. The initialization ofeach of these elements is set by 16 initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a totalof 4096 bits. If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization strings arepadded with zeros to the left.
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S8_S16
Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 8-bits and16-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
Design Element Port A DepthPort AWidth
Port AADDR Port A DI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S8_S16 512 8 (8:0) (7:0) 256 16 (7:0) (15:0)
ADDR=address bus for the port.
DI=data input bus for the port.
All Port A input pins have setup time referenced to the CLKA pin and its data output bus DOA has a clock-to-outtime referenced to the CLKA. All Port B input pins have setup time referenced to the CLKB pin and its dataoutput bus DOB has a clock-to-out time referenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, andCLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on aRAMB4 port is absorbed into the block and does not use a CLB resource.
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Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.• Start=((ADDR port+1)*(Widthport)) -1• End=(ADDRport)*(Widthport)
Port Width Port Addresses
8 512 <----- 1 0
16 256 <----- 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the
data stored will be invalid.• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating
the clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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RAMB4_S8_S8
Primitive: 4K-bit Dual-Port Synchronous Block RAM with Port Widths Configured to 8-bits
IntroductionThis design element is a 4096-bit dual-ported dedicated random access memory block with synchronous writecapability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port isindependently configured to a specific data width, as expressed in the following table:
DesignElement
Port ADepth
Port AWidth
Port AADDR
Port ADI
Port BDepth
Port BWidth
Port BADDR Port B DI
RAMB4_S8_S8 512 8 (8:0) (7:0) 512 8 (8:0) (7:0)
ADDR=address bus for the port
DI=data input bus for the port
Each port is fully synchronous with independent clock pins. All port A input pins have setup time referencedto the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All port Binput pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out timereferenced to the CLKB.
The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and theoutput (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during theLow-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data atDIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during theLow-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loadedinto the word selected by the write address (ADDRA) during the Low-to-High clock transition and the dataoutput (DOA) reflects the selected (addressed) word.
The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and theoutput (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during theLow-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data atDIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during theLow-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into theword selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB)reflects the selected (addressed) word.
The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, andCLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on aRAMB4 port is absorbed into the block and does not use a CLB resource.
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Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contentsof the block RAM are not altered. For FPGA devices, power-on conditions are simulated when global set/reset(GSR) is active. GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR inputof the appropriate STARTUP_architecture symbol.
You can use the INIT_0x attributes to specify an initial value during device configuration. There are 16initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. If any INIT_0xattribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.
Logic TableInputs Outputs
EN(A/B) RST(A/B) WE(A/B) CLK(A/B) ADDR(A/B) DI(A/B) DO(A/B) RAM Contents
0 X X X X X No Change No Change
1 1 0 ↑ X X 0 No Change
1 1 1 ↑ addr data 0 RAM(addr) =>data
1 0 0 ↑ addr X RAM(addr) No Change
1 0 1 ↑ addr data data RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB
Port DescriptionsAddress Mapping - Each port accesses the same set of 4096 memory cells using an addressing scheme that isdependent on the width of the port. The physical RAM location that is addressed for a particular width isdetermined from the following formula.
• Start=((ADDR port+1)*(Widthport)) -1
• End=(ADDRport)*(Widthport)
Port Width Port Addresses
8 512 <----- 1 0
Port Conflict resolution - This design element is a true dual-ported RAM in that it allows simultaneous reads ofthe same memory cell. When one port is performing a write to a given memory cell, the other port should notaddress that memory cell (for a write or a read) within the clock-to-clock setup window.
• If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, thedata stored will be invalid.
• If one port attempts to read from the same memory cell that the other is simultaneously writing to, violatingthe clock setup requirement, the write will be successful but the data read will be invalid.
Design Entry MethodThis design element can be used in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ROM16X1
Primitive: 16-Deep by 1-Wide ROM
IntroductionThis design element is a 16-word by 1-bit read-only memory. The data output (O) reflects the word selected bythe 4-bit address (A3 – A0). The ROM is initialized to a known value during configuration with the INIT=valueparameter. The value consists of four hexadecimal digits that are written into the ROM from the most-significantdigit A=FH to the least-significant digit A=0H. For example, the INIT=10A7 parameter produces the data stream:0001 0000 1010 0111 An error occurs if the INIT=value is not specified.
Logic TableInput Output
I0 I1 I2 I3 O
0 0 0 0 INIT(0)
0 0 0 1 INIT(1)
0 0 1 0 INIT(2)
0 0 1 1 INIT(3)
0 1 0 0 INIT(4)
0 1 0 1 INIT(5)
0 1 1 0 INIT(6)
0 1 1 1 INIT(7)
1 0 0 0 INIT(8)
1 0 0 1 INIT(9)
1 0 1 0 INIT(10)
1 0 1 1 INIT(11)
1 1 0 0 INIT(12)
1 1 0 1 INIT(13)
1 1 1 0 INIT(14)
1 1 1 1 INIT(15)
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About Design Elements
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value All zeros Specifies the contents of the ROM.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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ROM32X1
Primitive: 32-Deep by 1-Wide ROM
IntroductionThis design element is a 32-word by 1-bit read-only memory. The data output (O) reflects the word selected bythe 5-bit address (A4 – A0). The ROM is initialized to a known value during configuration with the INIT=valueparameter. The value consists of eight hexadecimal digits that are written into the ROM from the most-significantdigit A=1FH to the least-significant digit A=00H.
For example, the INIT=10A78F39 parameter produces the data stream: 0001 0000 1010 0111 1000 1111 0011 1001An error occurs if the INIT=value is not specified.
Logic TableInput Output
I0 I1 I2 I3 O
0 0 0 0 INIT(0)
0 0 0 1 INIT(1)
0 0 1 0 INIT(2)
0 0 1 1 INIT(3)
0 1 0 0 INIT(4)
0 1 0 1 INIT(5)
0 1 1 0 INIT(6)
0 1 1 1 INIT(7)
1 0 0 0 INIT(8)
1 0 0 1 INIT(9)
1 0 1 0 INIT(10)
1 0 1 1 INIT(11)
1 1 0 0 INIT(12)
1 1 0 1 INIT(13)
1 1 1 0 INIT(14)
1 1 1 1 INIT(15)
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About Design Elements
Design Entry MethodThis design element can be used in schematics.
Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 32-Bit Value All zeros Specifies the contents of the ROM.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SOP3
Macro: Sum of Products
IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
SOP3B1A
Macro: Sum of Products
IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SOP3B1B
Macro: Sum of Products
IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
SOP3B2A
Macro: Sum of Products
IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SOP3B2B
Macro: Sum of Products
IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
SOP3B3
Macro: Sum of Products
IntroductionThree input Sum of Products (SOP) macros provide common logic functions by OR gating the output of oneAND function with one direct input. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SOP4
Macro: Sum of Products
IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SOP4B1
Macro: Sum of Products
IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SOP4B2A
Macro: Sum of Products
IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
SOP4B2B
Macro: Sum of Products
IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
SOP4B3
Macro: Sum of Products
IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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About Design Elements
SOP4B4
Macro: Sum of Products
IntroductionFour input Sum of Products (SOP) macros provide common logic functions by OR gating the outputs of twoAND functions. Variations of inverting and non-inverting inputs are available.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SR16CE
Macro: 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear
IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel outputs (Q), and clock enable(CE) and asynchronous clear (CLR) inputs. The (CLR) input, when High, overrides all other inputs and resets thedata outputs (Q) Low. When (CE) is High and (CLR) is Low, the data on the SLI input is loaded into the firstbit of the shift register during the Low-to- High clock (C) transition and appears on the (Q0) output. Duringsubsequent Low-to- High clock transitions, when (CE) is High and (CLR) is Low, data shifts to the next highestbit position as new data is loaded into (Q0) (SLI→Q0, Q0→Q1, Q1→Q2, and so forth). The register ignores clocktransitions when (CE) is Low.
Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stageand connecting clock, (CE), and (CLR) in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
CLR CE SLI C Q0 Qz – Q1
1 X X X 0 0
0 0 X X No Change No Change
0 1 SLI ↑ SLI qn-1
z = bit width - 1
qn-1 = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR16CLEMacro: 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andAsynchronous Clear
IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and asynchronous clear (CLR) . The register ignoresclock transitions when (L) and (CE) are Low. The asynchronous (CLR), when High, overrides all other inputsand resets the data outputs (Q) Low. When (L) is High and (CLR) is Low, data on the Dn – D0 inputs is loadedinto the corresponding Qn – (Q0) bits of the register.
When (CE) is High and (L) and (CLR) are Low, data on the SLI input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent clocktransitions, when (CE) is High and (L) and (CLR) are Low, the data shifts to the next highest bit position as newdata is loaded into (Q)0 (for example, SLI→Q0, Q0→Q1, and Q1→Q2).
Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (CLR) inputs in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
CLR L CE SLI Dn – D0 C Q0 Qz – Q1
1 X X X X X 0 0
0 1 X X Dn – D0 ↑ D0 Dn
0 0 1 SLI X ↑ SLI qn-1
0 0 0 X X X No Change No Change
z = bitwidth -1
qn-1 = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR16CLEDMacro: 16-Bit Shift Register with Clock Enable and Asynchronous Clear
IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q), and four control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), andasynchronous clear (CLR). The register ignores clock transitions when (CE) and (L) are Low. The asynchronousclear, when High, overrides all other inputs and resets the data outputs (Qn) Low.
When (L) is High and (CLR) is Low, the data on the (D) inputs is loaded into the corresponding (Q) bits of theregister. When (CE) is High and (L) and (CLR) are Low, data is shifted right or left, depending on the state of theLEFT input. If LEFT is High, data on the SLI is loaded into (Q0) during the Low-to-High clock transition andshifted left (for example, to Q1 or Q2) during subsequent clock transitions. If LEFT is Low, data on the SRI isloaded into the last (Q) output during the Low-to-High clock transition and shifted right during subsequentclock transitions. The logic tables indicate the state of the (Q) outputs under all input conditions.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
CLR L CE LEFT SLI SRID15 –D0 C Q0 Q15
Q14 –Q1
1 X X X X X X X 0 0 0
0 1 X X X X D15 –D0 ↑ D0 D15 Dn
0 0 0 X X X X X NoChange
NoChange
NoChange
0 0 1 1 SLI X X ↑ SLI q14 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition.
Design Entry MethodThis design element is only for use in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR16RE
Macro: 16-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset
IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE),and synchronous reset (R) inputs. The R input, when High, overrides all other inputs during the Low-to-Highclock (C) transition and resets the data outputs (Q) Low.
When (CE) is High and (R) is Low, the data on the (SLI) is loaded into the first bit of the shift register duringthe Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent Low-to-High clocktransitions, when (CE) is High and R is Low, data shifts to the next highest bit position as new data is loaded into(Q0) (for example, SLI→Q0, Q0→Q1, and Q1→Q2). The register ignores clock transitions when (CE) is Low.
Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), and (R) in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
R CE SLI C Q0 Qz – Q1
1 X X ↑ 0 0
0 0 X X No Change No Change
0 1 SLI ↑ SLI qn-1
z = bitwidth -1
qn-1 = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
SR16RLE
Macro: 16-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andSynchronous Reset
IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and synchronous reset (R). The register ignores clocktransitions when (L) and (CE) are Low. The synchronous (R), when High, overrides all other inputs during theLow-to-High clock (C) transition and resets the data outputs (Q) Low. When (L) is High and (R) is Low duringthe Low-to-High clock transition, data on the (D) inputs is loaded into the corresponding Q bits of the register.
When (CE) is High and (L) and (R) are Low, data on the (SLI) input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent clocktransitions, when (CE) is High and (L) and (R) are Low, the data shifts to the next highest bit position as newdata is loaded into Q0.
Registers can be cascaded by connecting the last Q output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (R) inputs in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
R L CE SLI Dz – D0 C Q0 Qz – Q1
1 X X X X ↑ 0 0
0 1 X X Dz – D0 ↑ D0 Dn
0 0 1 SLI X ↑ SLI qn-1
0 0 0 X X X No Change No Change
z = bitwidth -1
qn-1 = state of referenced output one setup time prior to active clock transition
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Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SR16RLED
Macro: 16-Bit Shift Register with Clock Enable and Synchronous Reset
IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q) and four control inputs — clock enable (CE), load enable (L), shift left/right (LEFT), andsynchronous reset (R). The register ignores clock transitions when (CE) and (L) are Low. The synchronous (R),when High, overrides all other inputs during the Low-to-High clock (C) transition and resets the data outputs(Q) Low. When (L) is High and (R) is Low during the Low-to-High clock transition, the data on the (D) inputs isloaded into the corresponding (Q) bits of the register.
When (CE) is High and (L) and (R) are Low, data shifts right or left, depending on the state of the LEFT input.If LEFT is High, data on (SLI) is loaded into (Q0) during the Low-to-High clock transition and shifted left (forexample, to Q1 and Q2) during subsequent clock transitions. If LEFT is Low, data on the (SRI) is loaded into thelast (Q) output during the Low-to-High clock transition and shifted right ) during subsequent clock transitions.The logic tables below indicates the state of the (Q) outputs under all input conditions.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
R L CE LEFT SLI SRID15 –D0 C Q0 Q15
Q14 –Q1
1 X X X X X X ↑ 0 0 0
0 1 X X X X D15 –D0 ↑ D0 D15 Dn
0 0 0 X X X X X NoChange
NoChange
NoChange
0 0 1 1 SLI X X ↑ SLI q14 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition
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Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SR4CE
Macro: 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear
IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel outputs (Q), and clock enable(CE) and asynchronous clear (CLR) inputs. The (CLR) input, when High, overrides all other inputs and resets thedata outputs (Q) Low. When (CE) is High and (CLR) is Low, the data on the SLI input is loaded into the firstbit of the shift register during the Low-to- High clock (C) transition and appears on the (Q0) output. Duringsubsequent Low-to- High clock transitions, when (CE) is High and (CLR) is Low, data shifts to the next highestbit position as new data is loaded into (Q0) (SLI→Q0, Q0→Q1, Q1→Q2, and so forth). The register ignores clocktransitions when (CE) is Low.
Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stageand connecting clock, (CE), and (CLR) in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
CLR CE SLI C Q0 Qz – Q1
1 X X X 0 0
0 0 X X No Change No Change
0 1 SLI ↑ SLI qn-1
z = bit width - 1
qn-1 = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SR4CLE
Macro: 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andAsynchronous Clear
IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and asynchronous clear (CLR) . The register ignoresclock transitions when (L) and (CE) are Low. The asynchronous (CLR), when High, overrides all other inputsand resets the data outputs (Q) Low. When (L) is High and (CLR) is Low, data on the Dn – D0 inputs is loadedinto the corresponding Qn – (Q0) bits of the register.
When (CE) is High and (L) and (CLR) are Low, data on the SLI input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent clocktransitions, when (CE) is High and (L) and (CLR) are Low, the data shifts to the next highest bit position as newdata is loaded into (Q)0 (for example, SLI→Q0, Q0→Q1, and Q1→Q2).
Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (CLR) inputs in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
CLR L CE SLI Dn – D0 C Q0 Qz – Q1
1 X X X X X 0 0
0 1 X X Dn – D0 ↑ D0 Dn
0 0 1 SLI X ↑ SLI qn-1
0 0 0 X X X No Change No Change
z = bitwidth -1
qn-1 = state of referenced output one setup time prior to active clock transition
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Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SR4CLED
Macro: 4-Bit Shift Register with Clock Enable and Asynchronous Clear
IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q), and four control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), andasynchronous clear (CLR). The register ignores clock transitions when (CE) and (L) are Low. The asynchronousclear, when High, overrides all other inputs and resets the data outputs (Qn) Low.
When (L) is High and (CLR) is Low, the data on the (D) inputs is loaded into the corresponding (Q) bits of theregister. When (CE) is High and (L) and (CLR) are Low, data is shifted right or left, depending on the state of theLEFT input. If LEFT is High, data on the SLI is loaded into (Q0) during the Low-to-High clock transition andshifted left (for example, to Q1 or Q2) during subsequent clock transitions. If LEFT is Low, data on the SRI isloaded into the last (Q) output during the Low-to-High clock transition and shifted right during subsequentclock transitions. The logic tables indicate the state of the (Q) outputs under all input conditions.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
CLR L CE LEFT SLI SRI D3 – D0 C Q0 Q3 Q2 – Q1
1 X X X X X X X 0 0 0
0 1 X X X X D3– D0 ↑ D0 D3 Dn
0 0 0 X X X X X NoChange
NoChange
NoChange
0 0 1 1 SLI X X ↑ SLI q2 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
qn-1 and qn+1 = state of referenced output one setup time prior to active clock transition.
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Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
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SR4RE
Macro: 4-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset
IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE),and synchronous reset (R) inputs. The R input, when High, overrides all other inputs during the Low-to-Highclock (C) transition and resets the data outputs (Q) Low.
When (CE) is High and (R) is Low, the data on the (SLI) is loaded into the first bit of the shift register duringthe Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent Low-to-High clocktransitions, when (CE) is High and R is Low, data shifts to the next highest bit position as new data is loaded into(Q0) (for example, SLI→Q0, Q0→Q1, and Q1→Q2). The register ignores clock transitions when (CE) is Low.
Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), and (R) in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
R CE SLI C Q0 Qz – Q1
1 X X ↑ 0 0
0 0 X X No Change No Change
0 1 SLI ↑ SLI qn-1
z = bitwidth -1
qn-1 = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR4RLE
Macro: 4-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andSynchronous Reset
IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and synchronous reset (R). The register ignores clocktransitions when (L) and (CE) are Low. The synchronous (R), when High, overrides all other inputs during theLow-to-High clock (C) transition and resets the data outputs (Q) Low. When (L) is High and (R) is Low duringthe Low-to-High clock transition, data on the (D) inputs is loaded into the corresponding Q bits of the register.
When (CE) is High and (L) and (R) are Low, data on the (SLI) input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent clocktransitions, when (CE) is High and (L) and (R) are Low, the data shifts to the next highest bit position as newdata is loaded into Q0.
Registers can be cascaded by connecting the last Q output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (R) inputs in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
R L CE SLI Dz – D0 C Q0 Qz – Q1
1 X X X X ↑ 0 0
0 1 X X Dz – D0 ↑ D0 Dn
0 0 1 SLI X ↑ SLI qn-1
0 0 0 X X X No Change No Change
z = bitwidth -1
qn-1 = state of referenced output one setup time prior to active clock transition
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Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR4RLED
Macro: 4-Bit Shift Register with Clock Enable and Synchronous Reset
IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q) and four control inputs — clock enable (CE), load enable (L), shift left/right (LEFT), andsynchronous reset (R). The register ignores clock transitions when (CE) and (L) are Low. The synchronous (R),when High, overrides all other inputs during the Low-to-High clock (C) transition and resets the data outputs(Q) Low. When (L) is High and (R) is Low during the Low-to-High clock transition, the data on the (D) inputs isloaded into the corresponding (Q) bits of the register.
When (CE) is High and (L) and (R) are Low, data shifts right or left, depending on the state of the LEFT input.If LEFT is High, data on (SLI) is loaded into (Q0) during the Low-to-High clock transition and shifted left (forexample, to Q1 and Q2) during subsequent clock transitions. If LEFT is Low, data on the (SRI) is loaded into thelast (Q) output during the Low-to-High clock transition and shifted right ) during subsequent clock transitions.The logic tables below indicates the state of the (Q) outputs under all input conditions.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
R L CE LEFT SLI SRI D3 – D0 C Q0 Q3 Q2 – Q1
1 X X X X X X ↑ 0 0 0
0 1 X X X X D3 – D0 ↑ D0 D3 Dn
0 0 0 X X X X X NoChange
NoChange
NoChange
0 0 1 1 SLI X X ↑ SLI q2 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition
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Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR8CE
Macro: 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Asynchronous Clear
IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel outputs (Q), and clock enable(CE) and asynchronous clear (CLR) inputs. The (CLR) input, when High, overrides all other inputs and resets thedata outputs (Q) Low. When (CE) is High and (CLR) is Low, the data on the SLI input is loaded into the firstbit of the shift register during the Low-to- High clock (C) transition and appears on the (Q0) output. Duringsubsequent Low-to- High clock transitions, when (CE) is High and (CLR) is Low, data shifts to the next highestbit position as new data is loaded into (Q0) (SLI→Q0, Q0→Q1, Q1→Q2, and so forth). The register ignores clocktransitions when (CE) is Low.
Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stageand connecting clock, (CE), and (CLR) in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
CLR CE SLI C Q0 Qz – Q1
1 X X X 0 0
0 0 X X No Change No Change
0 1 SLI ↑ SLI qn-1
z = bit width - 1
qn-1 = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR8CLEMacro: 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andAsynchronous Clear
IntroductionThis design element is a shift register with a shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and asynchronous clear (CLR) . The register ignoresclock transitions when (L) and (CE) are Low. The asynchronous (CLR), when High, overrides all other inputsand resets the data outputs (Q) Low. When (L) is High and (CLR) is Low, data on the Dn – D0 inputs is loadedinto the corresponding Qn – (Q0) bits of the register.
When (CE) is High and (L) and (CLR) are Low, data on the SLI input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent clocktransitions, when (CE) is High and (L) and (CLR) are Low, the data shifts to the next highest bit position as newdata is loaded into (Q)0 (for example, SLI→Q0, Q0→Q1, and Q1→Q2).
Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (CLR) inputs in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
CLR L CE SLI Dn – D0 C Q0 Qz – Q1
1 X X X X X 0 0
0 1 X X Dn – D0 ↑ D0 Dn
0 0 1 SLI X ↑ SLI qn-1
0 0 0 X X X No Change No Change
z = bitwidth -1
qn-1 = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR8CLEDMacro: 8-Bit Shift Register with Clock Enable and Asynchronous Clear
IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q), and four control inputs: clock enable (CE), load enable (L), shift left/right (LEFT), andasynchronous clear (CLR). The register ignores clock transitions when (CE) and (L) are Low. The asynchronousclear, when High, overrides all other inputs and resets the data outputs (Qn) Low.
When (L) is High and (CLR) is Low, the data on the (D) inputs is loaded into the corresponding (Q) bits of theregister. When (CE) is High and (L) and (CLR) are Low, data is shifted right or left, depending on the state of theLEFT input. If LEFT is High, data on the SLI is loaded into (Q0) during the Low-to-High clock transition andshifted left (for example, to Q1 or Q2) during subsequent clock transitions. If LEFT is Low, data on the SRI isloaded into the last (Q) output during the Low-to-High clock transition and shifted right during subsequentclock transitions. The logic tables indicate the state of the (Q) outputs under all input conditions.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
CLR L CE LEFT SLI SRI D7 – D0 C Q0 Q7 Q6 – Q1
1 X X X X X X X 0 0 0
0 1 X X X X D7 – D0 ↑ D0 D7 Dn
0 0 0 X X X X X NoChange
NoChange
NoChange
0 0 1 1 SLI X X ↑ SLI q6 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR8RE
Macro: 8-Bit Serial-In Parallel-Out Shift Register with Clock Enable and Synchronous Reset
IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel outputs (Qn), clock enable (CE),and synchronous reset (R) inputs. The R input, when High, overrides all other inputs during the Low-to-Highclock (C) transition and resets the data outputs (Q) Low.
When (CE) is High and (R) is Low, the data on the (SLI) is loaded into the first bit of the shift register duringthe Low-to-High clock (C) transition and appears on the (Q0) output. During subsequent Low-to-High clocktransitions, when (CE) is High and R is Low, data shifts to the next highest bit position as new data is loaded into(Q0) (for example, SLI→Q0, Q0→Q1, and Q1→Q2). The register ignores clock transitions when (CE) is Low.
Registers can be cascaded by connecting the last (Q) output of one stage to the SLI input of the next stage andconnecting clock, (CE), and (R) in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
R CE SLI C Q0 Qz – Q1
1 X X ↑ 0 0
0 0 X X No Change No Change
0 1 SLI ↑ SLI qn-1
z = bitwidth -1
qn-1 = state of referenced output one setup time prior to active clock transition
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR8RLE
Macro: 8-Bit Loadable Serial/Parallel-In Parallel-Out Shift Register with Clock Enable andSynchronous Reset
IntroductionThis design element is a shift register with shift-left serial input (SLI), parallel inputs (D), parallel outputs (Q),and three control inputs: clock enable (CE), load enable (L), and synchronous reset (R). The register ignores clocktransitions when (L) and (CE) are Low. The synchronous (R), when High, overrides all other inputs during theLow-to-High clock (C) transition and resets the data outputs (Q) Low. When (L) is High and (R) is Low duringthe Low-to-High clock transition, data on the (D) inputs is loaded into the corresponding Q bits of the register.
When (CE) is High and (L) and (R) are Low, data on the (SLI) input is loaded into the first bit of the shiftregister during the Low-to-High clock (C) transition and appears on the Q0 output. During subsequent clocktransitions, when (CE) is High and (L) and (R) are Low, the data shifts to the next highest bit position as newdata is loaded into Q0.
Registers can be cascaded by connecting the last Q output of one stage to the SLI input of the next stage andconnecting clock, (CE), (L), and (R) inputs in parallel.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
R L CE SLI Dz – D0 C Q0 Qz – Q1
1 X X X X ↑ 0 0
0 1 X X Dz – D0 ↑ D0 Dn
0 0 1 SLI X ↑ SLI qn-1
0 0 0 X X X No Change No Change
z = bitwidth -1
qn-1 = state of referenced output one setup time prior to active clock transition
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Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SR8RLED
Macro: 8-Bit Shift Register with Clock Enable and Synchronous Reset
IntroductionThis design element is a shift register with shift-left (SLI) and shift-right (SRI) serial inputs, parallel inputs (D),parallel outputs (Q) and four control inputs — clock enable (CE), load enable (L), shift left/right (LEFT), andsynchronous reset (R). The register ignores clock transitions when (CE) and (L) are Low. The synchronous (R),when High, overrides all other inputs during the Low-to-High clock (C) transition and resets the data outputs(Q) Low. When (L) is High and (R) is Low during the Low-to-High clock transition, the data on the (D) inputs isloaded into the corresponding (Q) bits of the register.
When (CE) is High and (L) and (R) are Low, data shifts right or left, depending on the state of the LEFT input.If LEFT is High, data on (SLI) is loaded into (Q0) during the Low-to-High clock transition and shifted left (forexample, to Q1 and Q2) during subsequent clock transitions. If LEFT is Low, data on the (SRI) is loaded into thelast (Q) output during the Low-to-High clock transition and shifted right ) during subsequent clock transitions.The logic tables below indicates the state of the (Q) outputs under all input conditions.
This register is asynchronously cleared, outputs Low, when power is applied.
Logic TableInputs Outputs
R L CE LEFT SLI SRI D7– D0 C Q0 Q7 Q6 – Q1
1 X X X X X X ↑ 0 0 0
0 1 X X X X D7 – D0 ↑ D0 D7 Dn
0 0 0 X X X X X NoChange
NoChange
NoChange
0 0 1 1 SLI X X ↑ SLI q6 qn-1
0 0 1 0 X SRI X ↑ q1 SRI qn+1
qn-1 or qn+1 = state of referenced output one setup time prior to active clock transition
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Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SRL16
Primitive: 16-Bit Shift Register Look-Up-Table (LUT)
IntroductionThis design element is a shift register look-up table (LUT). The inputs A3, A2, A1, and A0 select the outputlength of the shift register.
The shift register can be of a fixed, static length or it can be dynamically adjusted.
• To create a fixed-length shift register - Drive the A3 through A0 inputs with static values. The length ofthe shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.
• To change the length of the shift register dynamically - Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.
The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.
The data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK) transition. Duringsubsequent Low-to-High clock transitions data shifts to the next highest bit position while new data is loaded.The data appears on the Q output when the shift register length determined by the address inputs is reached.
Logic TableInputs Output
Am CLK D Q
Am X X Q(Am)
Am ↑ D Q(Am - 1)
m= 0, 1, 2, 3
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value All zeros Sets the initial value of Q output afterconfiguration.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SRL16_1
Primitive: 16-Bit Shift Register Look-Up-Table (LUT) with Negative-Edge Clock
IntroductionThis design element is a shift register look-up table (LUT). The inputs A3, A2, A1, and A0 select the outputlength of the shift register.
The shift register can be of a fixed, static length or it can be dynamically adjusted.
• To create a fixed-length shift register - Drive the A3 through A0 inputs with static values. The length ofthe shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.
• To change the length of the shift register dynamically - Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.
The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.
The data (D) is loaded into the first bit of the shift register during the High-to-Low clock (CLK) transition. Duringsubsequent High-to-Low clock transitions data shifts to the next highest bit position as new data is loaded. Thedata appears on the Q output when the shift register length determined by the address inputs is reached.
Logic TableInputs Output
Am CLK D Q
Am X X Q(Am)
Am ↓ D Q(Am - 1)
m= 0, 1, 2, 3
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value All zeros Sets the initial value of Q output afterconfiguration
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SRL16E
Primitive: 16-Bit Shift Register Look-Up-Table (LUT) with Clock Enable
IntroductionThis design element is a shift register look-up table (LUT). The inputs A3, A2, A1, and A0 select the outputlength of the shift register.
The shift register can be of a fixed, static length or it can be dynamically adjusted.• To create a fixed-length shift register - Drive the A3 through A0 inputs with static values. The length of
the shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.
• To change the length of the shift register dynamically - Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.
The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.
When CE is High, the data (D) is loaded into the first bit of the shift register during the Low-to-High clock (CLK)transition. During subsequent Low-to-High clock transitions, when CE is High, data shifts to the next highest bitposition as new data is loaded. The data appears on the Q output when the shift register length determined bythe address inputs is reached. When CE is Low, the register ignores clock transitions.
Logic TableInputs Output
Am CE CLK D Q
Am 0 X X Q(Am)
Am 1 ↑ D Q(Am - 1)
m= 0, 1, 2, 3
Design Entry MethodThis design element can be used in schematics.
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Available AttributesAttribute Type Allowed Values Default Description
INIT Hexadecimal Any 16-Bit Value All zeros Sets the initial value of content and output of shiftregister after configuration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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SRL16E_1
Primitive: 16-Bit Shift Register Look-Up-Table (LUT) with Negative-Edge Clock and Clock Enable
IntroductionThis design element is a shift register look up table (LUT) with clock enable (CE). The inputs A3, A2, A1, and A0select the output length of the shift register.
The shift register can be of a fixed, static length or it can be dynamically adjusted.
• To create a fixed-length shift register - Drive the A3 through A0 inputs with static values. The length ofthe shift register can vary from 1 bit to 16 bits, as determined by the following formula: Length = (8 x A3)+(4 x A2) + (2 x A1) + A0 +1 If A3, A2, A1, and A0 are all zeros (0000), the shift register is one bit long. Ifthey are all ones (1111), it is 16 bits long.
• To change the length of the shift register dynamically - Change the values driving the A3 through A0inputs. For example, if A2, A1, and A0 are all ones (111) and A3 toggles between a one (1) and a zero (0), thelength of the shift register changes from 16 bits to 8 bits. Internally, the length of the shift register is always 16bits and the input lines A3 through A0 select which of the 16 bits reach the output.
The shift register LUT contents are initialized by assigning a four-digit hexadecimal number to an INIT attribute.The first, or the left-most, hexadecimal digit is the most significant bit. If an INIT value is not specified, it defaultsto a value of four zeros (0000) so that the shift register LUT is cleared during configuration.
When CE is High, the data (D) is loaded into the first bit of the shift register during the High-to-Low clock (CLK)transition. During subsequent High-to-Low clock transitions, when CE is High, data is shifted to the next highestbit position as new data is loaded. The data appears on the Q output when the shift register length determinedby the address inputs is reached. When CE is Low, the register ignores clock transitions.
Logic TableInputs Output
Am CE CLK D Q
Am 0 X X Q(Am)
Am 1 ↓ D Q(Am - 1)
m= 0, 1, 2, 3
Design Entry MethodThis design element can be used in schematics.
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Available Attributes
Attribute TypeAllowedValues Default Description
INIT Hexadecimal Any 16-BitValue
All zeros Sets the initial value of content and output of shiftregister after configuration.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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STARTBUF_SPARTAN2
Primitive: VHDL Simulation of FPGA Designs
IntroductionThis design element is used for VHDL simulation of FPGA designs that require the use of the STARTUP block.The difference between the STARTBUF and the STARTUP block is that the STARTBUF contains output portswhich may be connected to all register set/resets in the design (GSROUT) or to all I/O three-state controls(GTSOUT) so that these functions may be functionally simulated. This design element should not be used forVerilog or schematic entry. In order to use the STARTBUF, the desired input(s) should be connected to a top-levelport in the design and the corresponding output(s) must be connected to either the three-state control signalfor all inferred and instantiated output buffers in the design (GTSOUT) or all inferred or instantiated registerset/resets in the design.
During simulation, the inputs to the STARTBUF can be toggled by the testbench in order to activate the globalthree-state or global set/reset signal in the design. This should be done at the beginning of the simulation tosimulate the behavior of the registers and I/O during configuration. It may also be applied during simulation tosimulate a reconfiguration (ProG pin high) of the device. During synthesis and implementation, this componentwill be treated as a STARTUP block. The connected input ports to this component should remain in the designand be connected to the correct corresponding global resource.
The value at port GSROUT will be always the be value at port GSRIN. The value at port GTSOUT will always bethe value at port GTSIN. CLKIN has no effect on simulation.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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STARTUP_SPARTAN2
Primitive: Spartan-II User Interface to Global Clock, Reset, and 3-State Controls
IntroductionThis design element is used for Global Set/Reset, global 3-state control, and the user configuration clock. TheGlobal Set/Reset (GSR) input, when High, sets or resets all flip-flops, all latches, and every block RAM (RAMB4)output register in the device, depending on the initialization state (S or R) of the component.
Note Block RAMB4 content, LUT RAMs, delay locked loop elements (CLKDLL, CLKDLLHF, BUFGDLL),and shift register LUTs (SRL16, SRL16_1, SRL16E, SRL16E_1) are not set/reset.
Following configuration, the global 3-state control (GTS), when High—and BSCAN is not enabled and executingan EXTEST instruction—forces all the IOB outputs into high impedance mode, which isolates the device outputsfrom the circuit but leaves the inputs active.
Note GTS= Global 3-State
Including the STARTUP_SPARTAN2 symbol in a design is optional. You must include the symbol under thefollowing conditions.
• To exert external control over global set/reset, connect the GSR pin to a top level port and an IBUF.
• To exert external control over global 3-state, connect the GTS pin to a top level port and IBUF.
• To synchronize startup to a user clock, connect the user clock signal to the CLK input. Furthermore, “userclock” must be selected in the BitGen program.
You can use location constraints to specify the pin from which GSR or GTS (or both) is accessed.
Design Entry MethodThis design element can be used in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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VCC
Primitive: VCC-Connection Signal Tag
IntroductionThis design element serves as a signal tag, or parameter, that forces a net or input function to a logic High level.A net tied to this element cannot have any other source.
When the placement and routing software encounters a net or input function tied to this element, it removes anylogic that is disabled by the Vcc signal, which is only implemented when the disabled logic cannot be removed.
Design Entry MethodThis design element is only for use in schematics.
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• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
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About Design Elements
XNOR2
Primitive: 2-Input XNOR Gate with Non-Inverted Inputs
IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Logic TableInput Output
I0 ... Iz O
Odd number of 1 0
Even number of 1 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
624 www.xilinx.com 10.1
About Design Elements
XNOR3
Primitive: 3-Input XNOR Gate with Non-Inverted Inputs
IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Logic TableInput Output
I0 ... Iz O
Odd number of 1 0
Even number of 1 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 625
About Design Elements
XNOR4
Primitive: 4-Input XNOR Gate with Non-Inverted Inputs
IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Logic TableInput Output
I0 ... Iz O
Odd number of 1 0
Even number of 1 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
626 www.xilinx.com 10.1
About Design Elements
XNOR5
Primitive: 5-Input XNOR Gate with Non-Inverted Inputs
IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Logic TableInput Output
I0 ... Iz O
Odd number of 1 0
Even number of 1 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 627
About Design Elements
XNOR6
Macro: 6-Input XNOR Gate with Non-Inverted Inputs
IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Logic TableInput Output
I0 ... Iz O
Odd number of 1 0
Even number of 1 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
628 www.xilinx.com 10.1
About Design Elements
XNOR7
Macro: 7-Input XNOR Gate with Non-Inverted Inputs
IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Logic TableInput Output
I0 ... Iz O
Odd number of 1 0
Even number of 1 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 629
About Design Elements
XNOR8
Macro: 8-Input XNOR Gate with Non-Inverted Inputs
IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Logic TableInput Output
I0 ... Iz O
Odd number of 1 0
Even number of 1 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
630 www.xilinx.com 10.1
About Design Elements
XNOR9
Macro: 9-Input XNOR Gate with Non-Inverted Inputs
IntroductionXNOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Logic TableInput Output
I0 ... Iz O
Odd number of 1 0
Even number of 1 1
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 631
About Design Elements
XOR2
Primitive: 2-Input XOR Gate with Non-Inverted Inputs
IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
632 www.xilinx.com 10.1
About Design Elements
XOR3
Primitive: 3-Input XOR Gate with Non-Inverted Inputs
IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 633
About Design Elements
XOR4
Primitive: 4-Input XOR Gate with Non-Inverted Inputs
IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
634 www.xilinx.com 10.1
About Design Elements
XOR5
Primitive: 5-Input XOR Gate with Non-Inverted Inputs
IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 635
About Design Elements
XOR6
Macro: 6-Input XOR Gate with Non-Inverted Inputs
IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
636 www.xilinx.com 10.1
About Design Elements
XOR7
Macro: 7-Input XOR Gate with Non-Inverted Inputs
IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 637
About Design Elements
XOR8
Macro: 8-Input XOR Gate with Non-Inverted Inputs
IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
638 www.xilinx.com 10.1
About Design Elements
XOR9
Macro: 9-Input XOR Gate with Non-Inverted Inputs
IntroductionXOR functions of up to nine inputs are available. All inputs are non-inverting. Because each input uses a CLBresource, replace functions with unused inputs with functions having the necessary number of inputs.
Design Entry MethodThis design element is only for use in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 639
About Design Elements
XORCY
Primitive: XOR for Carry Logic with General Output
IntroductionThis design element is a special XOR with general O output that generates faster and smaller arithmeticfunctions. The XORCY primitive is a dedicated XOR function within the carry-chain logic of the slice. It allowsfor fast and efficient creation of arithmetic (add/subtract) or wide logic functions (large AND/OR gate).
Logic TableInput Output
LI CI O
0 0 0
0 1 1
1 0 1
1 1 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
640 www.xilinx.com 10.1
About Design Elements
XORCY_D
Primitive: XOR for Carry Logic with Dual Output
IntroductionThis design element is a special XOR that generates faster and smaller arithmetic functions.
Logic TableInput Output
LI CI O and LO
0 0 0
0 1 1
1 0 1
1 1 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
10.1 www.xilinx.com 641
About Design Elements
XORCY_L
Primitive: XOR for Carry Logic with Local Output
IntroductionThis design element is a special XOR with local LO output that generates faster and smaller arithmetic functions.
Logic TableInput Output
LI CI LO
0 0 0
0 1 1
1 0 1
1 1 0
Design Entry MethodThis design element can be used in schematics.
For More Information• See the Spartan-II User Guide and the Spartan-IIE User Guide.
• See the Spartan-II Data Sheets and Spartan-IIE Data Sheets.
Libraries Guide
642 www.xilinx.com 10.1