issn 1755-4535 novel three-phase asymmetrical … · voltage source inverter ... which are the...

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Published in IET Power ElectronicsReceived on 11th September 2012Revised on 8th February 2013Accepted on 24th February 2013doi: 10.1049/iet-pel.2012.0508

696The Institution of Engineering and Technology 2013

ISSN 1755-4535

Novel three-phase asymmetrical cascaded multilevelvoltage source inverterHamza Belkamel1, Saad Mekhilef1, Ammar Masaoud1, Mohsen Abdel Naeim2

1Department of Electrical Engineering, Faculty of Engineering, University of Malaya, Kuala Lumpur 50603, Malaysia2Mechanical Engineering Department, Faculty of Engineering, Assiut University, Assiut 71516, Egypt

E-mail: [email protected]

Abstract: Series connection of power cells in asymmetrical cascaded configurations helps to cancel redundant output levels andmaximise the number of different levels generated by the inverter. A new configuration of three-phase multilevel asymmetricalcascaded voltage source inverter is presented. This structure consists of series-connected sub-multilevel inverters blocks. Thenumber of utilised switches, insulated gate driver circuits, voltage standing on switches, installation area and cost areconsiderably reduced. Cascaded-cell DC voltages in each inverter leg form an arithmetic sequence with common difference ofE. With the selected inverter DC sources, high-frequency pulse-width modulation (PWM) control methods can be effectivelyapplied without loss of modularity. Low-frequency and sinusoidal PWM techniques were successfully applied. Hence, highflexibility in the modulation of the proposed inverter is demonstrated. The prototype of the suggested inverter wasmanufactured and the obtained simulation and hardware results ensured the feasibility of the configuration, and thecompatibility of both modulation techniques was accurately noted. Lastly, the semiconductor losses in the converter werecalculated using simulation models. Based on the analysis of the total power losses, the proposed inverter provided highefficiency at different operating conditions.

1 Introduction

Many multilevel converter topologies and wide variety ofcontrol methods have been developed in the recentliteratures [1–3]. Three different basic multilevel convertertopologies are commonly used, which are the neutral pointdiode clamped (NPC); flying capacitor (FC) and thecascaded H-bridge (CHB) [4, 5].The CHB multilevel inverter combines a multiple units of

single-phase H-bridge power cells. The prominence of thisconfiguration is attributed to some characteristics lacked inother inverter topologies [6, 7]. This structure needs onlystandard low-voltage mature technology components tooutput medium voltage levels. Furthermore, theseconverters have a high modularity degree, since eachinverter can be seen as a module with similar circuittopology, control structure and modulation [8]. Thereforeany faulty module in the inverter can be quickly and easilyreplaced. Moreover, with an appropriated control technique,there is a probability to bypass the faulty module withoutstopping the load, bringing an almost continuous overallavailability [9].The symmetric structure of CHB inverter makes use of

equal DC voltage sources and for N H-bridge cells perphase, there are 2N + 1 levels produced in output of phasevoltage. Each cell of the H-bridge needs a separate DCsource, which is usually obtained by an arrangement ofthree-phase or single-phase diode-based rectifiers [10].Multiple transformers are used to provide the electrical

isolation. Recently, high-frequency transformer-basedmodules are utilised in building cascaded multilevelinverters [11] without isolated DC links, and diode-basedrectifier has been replaced with active front-end rectifierwhich is more suitable for regenerative operation [12, 13].In some applications, these DC voltages can be acquireddirectly by isolating DC sources like photovoltaic panels[14] or DC–DC isolated converters [15].Asymmetrical cascaded H-bridge (ACHB) inverters use

DC supplies with unequal voltages [16]. This topologyoffers a good opportunity to increase the number of levelswith reduced total harmonic distortion (THD) and switchinglosses. ACHB inverters show high efficiency up to 80% atthe fundamental frequency [17, 18].Furthermore, the number of voltage steps is maximised

when the cascaded-cell DC voltages form a ratio-3geometric sequence [19]. This ratio has been utilised todesign inverters with large number of levels and, therefore,small voltage distortion for multifarious applications[20, 21]. However, it has been discovered that ratio-3DC-sourced inverter is not suitable for high-frequency pulsewidth modulation (PWM) control techniques as thehigh-voltage stage is subjected to high switching frequency[22–24].A two-cell stack that is similar to the generalised

topology has been cascaded with three-level FC cell [25].This configuration significantly minimises the number ofthe utilised DC supplies, and the size of the capacitorsused in high-voltage stage is twice the one of the

IET Power Electron., 2013, Vol. 6, Iss. 8, pp. 1696–1706doi: 10.1049/iet-pel.2012.0508

Fig. 1 Proposed topology showing

a Basic unitb Proposed three-phase asymmetrical cascade n-level inverter

Table 1 Switching states of the basic unit

State Switches states Vo

S1 S2

1 ON OFF E2 OFF ON 0

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low-voltage stage. Such arrangement classifies the topologyunder the asymmetrical configurations and five voltagelevels have been produced. Unfortunately, the proposedstructure and the modulation technique may not serve thepurpose if more voltage steps are required. Moreover, alarge number of switches have been employed and largecapacitor banks need to be included in high-voltageapplications.Recently, CHB inverters employ multilevel DC-link and
came up with a higher number of total output voltage levelsusing a few single-phase inverters. A variable DC-linkvoltage provides the single-phase full-bridge (SPFB)inverter with several voltage levels starting from zero volts[26]. Also, the SPFB inverter produces the positive andnegative voltages of the supplied voltage. Theseconfigurations have the capability to deliver a high outputcurrent with low switching frequency in the SPBF. Thevariable DC-link voltage can be obtained from cascadedNPC or FC structures or even from buck DC–DCconverters [27, 28]. The inverter configuration that consistsof a multilevel DC source and a SPFB inverter waspresented in [27]. The SPFB inverter is used for creatingzero, negative and positive voltages. Unfortunately, thehalf-bridge-based multilevel DC-link inverter seems toocostly because of the symmetric DC supplies and largenumber of switches used. In [29], the author introduced anovel topology in the family of ACHB with the intent ofachieving higher number of voltage levels withoutincreasing the number of bridges. An algorithm todetermine the DC source levels is provided. Unfortunately,the proposed algorithm does not serve in creating all steps(odd and even) at the output voltage. To produce an outputvoltage with a constant number of steps, large numbers ofbidirectional switches are needed. The aforementioneddrawbacks can be overcome based on the proposed work in[26, 30], whereby all even and odd levels can be produced.It was proven that a higher number of steps with aminimised number of switches is used compared to theconfiguration in [29]. It is noteworthy that bothconfigurations in [26, 30] contributed in lessening of thenumber of switches and gate driver circuits with minimumstanding voltage on the switches, but the topology was notextended to three-phase applications. Moreover, the inverterdid not show flexibility in control, since none of the controltechniques has been employed. This paper suggests a noveltopology for three-phase asymmetrical cascaded multilevelinverters with a high number of odd and even steps. Thenumber of switches, insulated gate driver circuits, voltagestanding on switches, installation area and cost aresignificantly reduced. The magnitudes of the utilised DCsupplies have been selected in such a way that brings thehigh number of voltage level with an effective applicationof PWM techniques. Two modulation techniques have beenemployed, which are low-frequency and sinusoidal PWM.The proposed work is presented in six sections. The firstsection focuses on the research advances in developingcascaded multilevel inverter topologies. In Section 2, thesuggested topology is well explained in terms of workingprinciples, voltage steps and DC supply selection. Section 3brings out the deployed modulation techniques in detail.The results obtained and the two modulation techniques areclearly discussed in Section 4, with a brief comparisonbetween the proposed topology and the inverter introducedin [27]. In Section 5, the proposed configuration and thefollowed method for the determination of DC voltagesource levels are compared with other counterparts. Lastly,


the study and analysis of the total power losses and inverterefficiency are carried out in Section 6.

2 Proposed topology

Fig. 1a shows the basic unit of the proposed topology. Twoswitches are used with a single DC supply to output twovoltage levels 0 and E. S1 and S2 are always in invertedconditions. If the switch S1 is ON, Vo = E, however, theOFF state of S1 makes Vo = 0. Switches S1 and S2 cannot beON simultaneously to avoid the occurrence of short circuitacross the DC supply. Table 1 provides the output voltagesof the basic unit for different switching states.Fig. 1b shows the power circuit of the suggested

three-phase asymmetrical n-level cascade inverter. Eachphase in the proposed topology consists of aseries-connected basic units. Based on the desired numberof output voltage levels, a number of basic units are used.The power circuit of the introduced three-phase inverter

makes use of unequal DC sources in magnitude. Suchcharacteristic classify it under the asymmetrical multilevelinverter topologies. It is noticeable that the topology

1697& The Institution of Engineering and Technology 2013

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involves numerous DC supplies, especially if a highernumber of voltage steps are required. In this case there isthe possibility to replace the DC supplies with renewableenergy devices such as photovoltaic or fuel cell. The valueof DC supply used in each and every basic unit in aparticular inverter leg is obtained as follows
V1 = E

V2 = 2E

V3 = 3E

Vn = nE (1)

where n is the number of basic units per inverter leg. Thephase to ground voltage S is the summation of the outputvoltages of all basic units, as given in (2).

S = V1 + V2 + V3 + · · · + Vn (2)

The maximum output voltage is calculated by substituting (1)in (2)

S = E + 2E + 3E + · · · + nE

S = (1+ 2+ 3+ · · · + n)E

S = E∑ni=1

i

V = nE

2(n+ 1) (3)

The number of steps N (voltage levels) with respect to thenumber of the used basic units can be calculated using (4).

N = 2∑ni=1

i+ 1

V = nE(n+ 1)+ 1 (4)

Fig. 2 Proposed three-phase asymmetrical cascade four-level inverter


3 Modulation techniques for the proposedinverter

In multilevel inverter modulation, two groups of methodshave been followed according to the switching frequency:modulation with fundamental switching frequency or highswitching frequency PWM.

3.1 Low-frequency modulation

The fundamental frequency is considered as a beneficialmodulation technique because of its low switchingfrequency compared to other control methods [27]. Theconventional PWM technique, space vector pulse-widthmodulation (PWM, sub-harmonic PWM (SH-PWM) andswitching frequency optimal PWM (SFO-PWM) formultilevel inverters necessitate equal DC voltage sources(symmetrical topologies). For instance, if the fundamentalswitching scheme is applied using the Elimination Theory,the transcendental equations characterising the harmoniccontents (such as the 5th, 7th, 11th and 13th) can be easilytransferred to polynomial equations [31].In order to examine the performance of the proposed

inverter, a typical four-level inverter topology is extractedfrom Fig. 1b and in order to examine the performance ofthe proposed inverter, a typical four-level inverter topologyis extracted as shown in Fig. 2. The first and the secondunit are fed with E and 2E, respectively. The DC value istaken as E = 50 V.The balanced load voltage can be achieved if the inverter

operates on the modes depicted in Table 2. The invertermay have 18 different switching states within a cycle of theoutput waveform.

3.2 Sinusoidal pulse width modulation (SPWM)

The simplest way of producing the PWM signal is through thecomparison of a reference sine wave with a triangle wave[32]. As depicted in Fig. 3a, the sine wave and the threecarriers (Carrier 1, Carrier 2 and Carrier 3) are compared.The Boolean outputs of the comparison make the pulsed

signals C1, C2, C3. With some logical operations applied to


Table 2 Mode of operation of the proposed three-phase multilevel inverter during one cycle

Mode Switching states Line voltages

S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 Vab Vbc Vca

1 ON OFF ON OFF OFF ON OFF ON OFF ON OFF ON 3E 0 −3E2 ON OFF ON OFF ON OFF OFF ON OFF ON OFF ON 2E E −3E3 ON OFF ON OFF OFF ON ON OFF OFF ON OFF ON E 2E −3E4 ON OFF ON OFF ON OFF ON OFF OFF ON OFF ON 0 3E −3E5 OFF ON ON OFF ON OFF ON OFF OFF ON OFF ON −E 3E −2E6 ON OFF OFF ON ON OFF ON OFF OFF ON OFF ON −E 3E −E7 OFF ON OFF ON ON OFF ON OFF OFF ON OFF ON −3E 3E 08 OFF ON OFF ON ON OFF ON OFF ON OFF OFF ON −3E 2E E9 OFF ON OFF ON ON OFF ON OFF OFF ON ON OFF −3E E 2E10 OFF ON OFF ON ON OFF ON OFF ON OFF ON OFF −3E 0 3E11 OFF ON OFF ON OFF ON ON OFF ON OFF ON OFF −2E −E 3E12 OFF ON OFF ON ON OFF OFF ON ON OFF ON OFF −E −2E 3E13 OFF ON OFF ON OFF ON OFF ON ON OFF ON OFF 0 −3E 3E14 ON OFF OFF ON OFF ON OFF ON ON OFF ON OFF E −3E 2E15 OFF ON ON OFF OFF ON OFF ON ON OFF ON OFF 2E −3E E16 ON OFF ON OFF OFF ON OFF ON ON OFF ON OFF 3E −3E 017 ON OFF ON OFF OFF ON OFF ON OFF ON ON OFF 3E −2E −E18 ON OFF ON OFF OFF ON OFF ON ON OFF OFF ON 3E −E −2E

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C1, C2, and C3 as given in (5) to (8)

G1 = C2 × C3

( )+ C1 (5)

G2 = C1 × C2

( )+ C3 (6)

G3 = C1 + C2

( )+ C1 (7)

G4 = C2 + C3

( )+ C3 (8)

where × stands for logic AND; + stands for logic OR.The appropriate switching signals that lead to the desired

output waveform can be derived, where G1, G2, G3 and G4

are the gate signals for switches S1, S2, S3 and S4,respectively. To avoid the short-circuit across the DC-linkin each and every basic unit, the following statement has tobe maintained all the time.

G1 = G2 and G3 = G4 (9)

In Figs. 3b and c there is an illustration of the gate signals ofthe four switches in the first leg (phase A) of the suggestedmultilevel inverter. In order to obtain the gate pulses for theswitches in phases B and C, the same process andoperations have been followed to control the switches inphase A with a shifted reference signal 120° and 240°,respectively. This feature makes sinusoidal PWM apromising technique especially in three-phase applications.

4 Experimental results and discussions

To ensure the feasibility of the proposed inverter, the powercircuit was simulated in MATLAB/Simulink power blockset software. The inverter was implemented and itsprototype has been manufactured. Insulated-gate bipolartransistors (IGBTs) with anti-parallel diodes(IRG4PH50UDPBF, 24A, 1200V) were employed asswitching devices. Digital signal processor (DSP,TMS320F28335) was used to produce the switching signalsfor the inverter.Simulation and hardware results have clearly shown the

reliability of the low-frequency and SPWM techniques in


the control of the suggested inverter. As mentioned earlier,the two basic units in each inverter leg take differentvoltages, whereas the voltage in the first unit is twice thesecond unit.During the hardware implementation, the inverter was tested

under E = 50 V in the first unit and 2E = 100 V in the secondunit. For SPWM implementation, the modulation index istaken as Mi = 0.8 with switching frequency fc = 2000 Hz.The control block diagram of the proposed inverter is

depicted in Fig. 4a. The prototype of the proposed inverterthat includes the following three high-voltage DC supplies,three low-voltage DC supplies, switching devices, DSP and20-Ω three-phase resistive load is shown in Fig. 4b.Figs. 5a and 6a depict the inverter output line to ground

voltage using low-frequency and sinusoidal PWMtechniques, respectively. Both staircases show four positivevoltage levels: 0, E, 2E and 3E. The presented topologyeases the way to come up with the negative voltages (−E,−2E and −3E) without any other additional circuit.It is well known that for n-level inverter there are (2n − 1)

line-to-line voltage levels consisting of (n − 1) positivelevels, (n − 1) negative levels and zero (0 V). For fourline-to-ground voltage levels in Figs. 5a and 6a, there areseven line-to-line voltage levels, as shown in Figs. 5b and 6b.In both modulation techniques, the controller manages to

generate the appropriate switching signals that lead theinverter to output the desired voltage. The feasibility of theconfiguration is conspicuous since it offers high flexibilityto use different loads with different parameters.In the topology introduced in [27], five basic cells per

phase were utilised to come up with 11 voltage levels. Inorder to reach such level count in three-phase, 15 equal DCsupplies along with 42 switches are required. In order toflip the polarity of the DC bus voltage and create acommon ground for the inverter legs, the connectionnecessitates a SPFB per phase. Besides, the employed equalDC sources categorise the topology under symmetricalinverters. Based on these two characteristics, the inverterrequires a considerable number of DC supplies, switchesand gate driver circuits as well. In the proposed connection,a multilevel DC-link is used without the H-bridges and theDC supplies are taken asymmetrically as described inSection 2. Figs. 6b and 7a clearly show the substantial


Fig. 3 SPWM showing

a Sinusoidal pulse-width modulation (SPWM)b Simulated waveforms of switching pulses for phase Ac Experimental waveforms of switching pulses for phase A

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increment in the inverter output voltage levels with areduction in power electronics components and DCsupplies. Table 3 calculates the needed DC supplies andswitching devices to produce 11 line-to-ground voltagelevels using the proposed topology in [27] and theconfiguration suggested in this paper.The proposed configuration has been tested under different

modulation indices. The THD of the output voltage can be


calculated by

THD =

��∑1n=3,5,7,...

V 2n

√

V1(10)

where V1 and n are the fundamental component and harmonicorder, respectively. Fig. 8a shows the variation in THD with


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the modulation index for the unfiltered output line-to-linevoltage. This illustrates that the THD is inverselyproportional to the modulation index Mi. In other words, alower THD in the output voltage is experienced at highermodulation index.The frequency spectrum of the unfiltered line-to-line
voltage captured via YOKOGAWA WT 1800 precisionpower analyser is shown in Fig. 8b. The graph contains thefundamental component and an infinite number of oddharmonics. Owing to the symmetry attained in the inverteroutput line-to-line voltage, all even sub-carrier harmonicswere eliminated. As it is well known in the PWM signalfrequency spectrum, some harmonics are centralised aroundthe carrier frequency ( fc = 2000 Hz).For modulation index Mi = 0.8, the THD of the voltage

waveform was found to be 25.609%. As depicted inFig. 8a, this value corresponds very well with the oneobtained from the simulation at the same modulation index.

Fig. 4 Figure showing

a Control block diagramb Prototype of the proposed multilevel inverter


There is another possibility to reach an output voltage withhigher number of steps in cascaded multilevel inverters bymaking a binary (power of two) relationship between theDC-link voltages. Unfortunately, the employment of thisstrategy in the proposed configuration creates a greatdifference in power distribution in the inverter cells.Because of this power distribution problem, the inverterneeds to be redesigned with different switch technologieslike integrated gate commutated thyristor for high powercells, high-voltage IGBT for medium-power cells andlow-voltage IGBT for low-power cells. The differentsemiconductor switches in the same power circuit reducethe inverter modularity, and limits appear in terms ofswitching frequency and modulation index.Providing a number of 300-V DC sources with three basic

units in (Fig. 1) per inverter leg. In this case 18 switches areused and a number of 300-V DC supplies need to beconnected in series in the second and third cells. Table 4



a Number of steps against number of utilised switchesb Number of steps against number of utilised DC supplies

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compares the power component requirements and the inverteroutput voltage between the two different methods that arefollowed to determine the value of DC supplies for theintroduced three-phase multilevel inverter. In the firstmethod, relationship between the DC-link voltages isbinary, whereas the second method selects the DC suppliesas described in Section 2.From the above table, it is observed that the first

technique brought higher voltage with larger number ofsteps. Unfortunately, extra DC supplies are required andthe switching devices in the third cell are subjected tohigh voltage. Therefore the use of this methodnecessitates different switches for high voltage blockage.


a Inverter output line to ground voltage using low frequencyb Line-to-line voltagec Phase voltaged Three-phase voltages


Since the voltage standing on switches is lower, thedeployed method to determine the value of the utilisedDC supplies manages to maintain similar switches with anacceptable number of voltage steps. Therefore bettermodularity is achieved compared to other asymmetricalcascaded configurations.

5 Comparison of the proposed topology withconventional multilevel inverters

For the same number of output voltage steps, Table 5 providesa brief comparison between conventional three-phase



a Sinusoidal PWM techniqueb Line-to-line voltagec Phase voltaged Three-phase voltages

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cascaded multilevel inverters and suggested inverter withregard to power component requirements.The diode clamped multilevel inverter is an attractive

high-voltage multilevel inverter because of its robustness[33]. The deviating voltage at the neutral point remainsalways a distracting feature in NPC inverter. ThereforeDC-link capacitor voltage balancing is the crucial task insuch configuration [34].The FC multilevel converter makes use of FCs for voltage

clamping [35]. To some extent, these topologies areadvantageous. This is due to the less operation performedby the transformer and redundant phase leg states thatmakes the semiconductor switches share the samedistributed stress [36]. The main drawback in suchconverters is the excessive number of storage capacitors forhigher voltage steps. Table 6 provides a comparisonbetween the suggested inverter and the well-knownfour-level inverters: diode-clamped and FC.

Table 3 11-level inverter requirement based on [23] and theproposed topology

Number ofvoltagelevels

Number ofutilisedswitches

Number byutilising DCsupplies

the proposedinverter in [23]

11 42 5

the proposedinverter

11 24 4Fig. 8 Figure showing

a Modulation index Mi against THDb Frequency spectrum of line-to-line voltage

IET Power Electron., 2013, Vol. 6, Iss. 8, pp. 1696–1706 1703doi: 10.1049/iet-pel.2012.0508 & The Institution of Engineering and Technology 2013

Table 4 Comparison between the two methods followed todetermine the value of DC supplies for the introduced inverter

Binary Proposedmethod

number of utilised switches 18 18number of utilised DC source (300 Vunits)

7 6

number of steps 8 7third cell voltage 1200 900maximum output voltage 8400 6800similarity of switches No Yes

Table 6 Comparison of the proposed four-level inverter withthe well-known four-level inverters

Diodeclamp

Flyingcapacitors

Proposedinverter

main switchingdevices

18 18 12

diodes 30 18 12DC bus 3 3 6balancingcapacitors

0 9 0

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6 Power losses and inverter efficiency

Power loss is an important index for cost estimation andcooling system designation in multilevel inverters. Ingeneral, there are two types of semiconductor losses inmultilevel inverter configurations. The conduction loss isdue to the voltage drop across the active semiconductordevice when conducting current. The switching loss occursat each current commutation of the device and it is directlyrelated to the switching frequency. Other losses likesnubber and off state losses are disregarded, since IGBTs(5SNE 0800M170100) were used with negligibly smallleakage current during the off state [37].MATLAB/Simulink model of the proposed 400 KW

four-level inverter was developed to study the conductionand switching power losses at different operatingconditions. The inverter delivers variable power to adistribution power system. The output of the inverter wasconnected to the 25 kV, 40 MVA, 50 Hz system through a2200 V/25 KV transformer. Each leg of the inverter was fedwith constant DC supplies E = 1100 V and 2E = 2200 V.The maximum ratings of the selected IGBTs (5SNE0800M170100) are: forward current of 800 A and a directvoltage of 1700 V.Conduction losses Pcond,IGBT of IGBT are approximated

based on its forward voltage drop, Von,IGBT and theinstantaneous current I(t)

Pcond, IGBT = 1

T

∫T0Von, IGBTI(t) dt (11)

Similarly, the conduction loss in a diode can be modelled as

Pcond−d(t) = iF(t) ∗ VFO + RF . iF(t)( ) (12)

where VFO is the forward voltage drop across the diode whenthe forward current of the device iF draw near zero and RF isthe diode approximate on-state resistance slope.

Table 5 Comparison of power component requirements among conv

Symmetrical Asymmetri

Binary

maximum output voltage E(Nstep − 1)/2

E(Nste

number of utilised switches M 6(Nstep − 1) 12[{(ln(Nste

maximum voltage standing on theswitches

6E(Nstep − 1) 6E(Ns


For an IGBT with an anti-parallel freewheeling diode, theswitching loss can be modelled by the switching lossenergy associated with each switching event. In the devicedatasheet, the switching loss energies, Eon and Eoff, wereestablished by integrating the product of the collectorcurrent characteristic and the collector–emitter voltagecharacteristic across the total switching time. Over aninterval T, the average switching power losses in an IGBTmodule and turn off power loss for the diode are estimated [38].

Pon =1

T

∫T0Eon(t) dt (13)

Poff =1

T

∫T0Eoff (t) dt (14)

Poff ,D = 1

T

∫T0Eoff ,D(t) dt (15)

Once the total semiconductor losses Ploss in the introducedinverter are defined, the relative efficiency is determinedbased on the following formula.

Efficiency(%) = Pout

Pout + Ploss× 100% (16)

For 1 KHz carrier frequency with 350 KW output power at apower factor PF = 0.75, Fig. 9a depicts the power lossdistribution among the switching devices in phase (A) of theproposed inverter. D1, D2, D3 and D4 are the freewheelingdiodes with built-in switches S1, S2, S3 and S4, respectively.In Fig. 9b the inverter efficiencies were calculated at four

different power factors. The inverter output power was setto 350 and 250 KW. An improved power factor is achievedby enhancing real power flow transfer. Therefore inverterefficiency varies proportionally and linearly with respect topower factor.For Pout = 350 KW and by considering a typical operating

power factor of a transmission line, PF = 0.75. The inverterefficiencies at the corresponding five switching frequenciesare shown in Fig. 9c. The efficiency varies inversely with

entional cascaded multilevel and the proposed topology

cal Proposed topology

Trinary

p − 1)/2 E(Nstep − 1)/2 E(Nstep − 1)/2

p + 1)/ln2)} −1]

(12lnNstep)/ln3

[(Nstep + 1)/2] = (1/72)M2 + (1/12)M+ 1

tep − 1) 6E(Nstep − 1) 6E(Nstep − 1)



a Power loss distribution among the switching devices in phase (A)b Inverter efficiency at different power factorsc Inverter efficiency at different switching frequencies

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the switching frequency. As the switching frequencyincreases, the efficiency of the inverter decreases as a resultof switching loss being considerably increased in thesemiconductor components.

7 Conclusions

A novel topology of three-phase cascaded multilevelinverter was introduced and the suggested configurationcame with reduced number of switches and gate driver


circuits. The voltage standing on switches is minimisedfor realising N steps. Therefore the proposed topologyresults in reduction of installation area and cost.Low-frequency and sinusoidal PWM techniques werecomfortably employed and both techniques showed highflexibility and simplicity in control.Furthermore, the method employed to determine the

magnitudes of the DC voltage sources was well executed.In order to verify the performance of the proposedmultilevel inverter, a four-level configuration was simulatedand its prototype was manufactured.


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The obtained simulation and hardware results met the
desired output, and it should be noted that the proposedtopology is made for three-phase three-wire loadapplications. Hence, subsequent work in the future mayinclude an extension to four-wire loads with other differentcontrol techniques.

8 Acknowledgment

The authors would like to thank the Ministry of HigherEducation of Malaysia and University of Malaya forproviding financial support under the research grant no.UM.C/HIR/MOHE/ENG/16001-00-D000017.

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