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September 2009Volume 100 No. 3www.saiee.org.za

Africa Research JournalResearch Journal of the South African Institute of Electrical Engineers

Incorporating the SAIEE Transactions

ISSN 1991-1696

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(SAIEE FOUNDED JUNE 1909 INCORPORATED DECEMBER 1909)AN OFFICIAL JOURNAL OF THE INSTITUTE

ISSN 1991-1696

President Immediate Past PresidentMr du Toit Grobler Mr Ian McKechnieVice-Presidents Deputy PresidentMr Andries Tshabalala Dr Angus HayMr Mike Cary Honorary Treasurer Mr Les James

Secretary and Head OfficeMs Gerda GeyerSouth African Institute for Electrical Engineers (SAIEE)PO Box 751253, Gardenview, 2047, South AfricaTel: (27-11) 487-3003Fax: (27-11) 487-3002E-mail: [email protected]

SAIEE AFRICA RESEARCH JOURNAL

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ARJ Editor-in-Chief Prof BM Lacquet

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EDITORS AND REVIEWERSEDITOR-IN-CHIEFProf. B.M. Lacquet, Faculty of Engineering and the Built Environment, University of Witwatersrand, Johannesburg, South Africa [email protected]

MANAGING EDITORDr S. Sinha, Dept. of Electrical, Electronic & Computer Engineering, University of Pretoria, Pretoria, South Africa [email protected]

SPECIALIST EDITORSCommunications, Signal Processing:Prof. L.P. Linde, Dept. of Electrical, Electronic & Computer Engineering, University of Pretoria, Pretoria, South Africa Prof. S. Maharaj, Dept. of Electrical, Electronic & Computer Engineering, University of Pretoria, Pretoria, South Africa Dr O. Holland, Centre for Telecommunications Research, London, United Kingdom Prof. F. Takawira, School of Electrical, Electronic and Computer Engineering, University of KwaZulu-Natal, Durban, South Africa Computer, Information Systems and Software Engineering:Prof. A. van der Merwe, Meraka Institute, CSIR, Pretoria, South Africa Prof. E. Barnard, Meraka Institute, CSIR, Pretoria, South AfricaProf. B. Dwolatzky, Joburg Centre for Software Engineering, University of the Witwatersrand, Johannesburg, South AfricaControl and Automation:Dr B. Yuksel, University of Tokyo, Japan Electromagnetics and Antennas:Prof. J.H. Cloete, Dept. of Electrical and Electronic Engineering, University of Stellenbosch, South Africa Prof. T.J.O. Afullo, School of Electrical, Electronic and Computer Engineering, University of KwaZulu-Natal, Durban, South Africa Dr R. Geschke, Dept. of Electrical and Electronic Engineering, University of Stellenbosch, South Africa Electron Devices and Circuits:Prof. M. du Plessis, Dept. of Electrical, Electronic & Computer Engineering, Pre-toria, University of Pretoria, South AfricaEnergy and Power Systems:Prof. M. Delimar, Faculty of Electrical Engineering and Computing, University of Zagreb, Zagreb, Croatia Engineering and Technology Management:Prof. J-H. Pretorius, Faculty of Engineering and the Built Environment, University of Johannesburg, Johannesburg, South AfricaProf. L. Pretorius, Graduate School of Technology Management (GSTM), University of Pretoria, Pretoria, South Africa

General Topics / Editors-at-large: Dr P.J. Cilliers, Hermanus Magnetic Observatory, Hermanus, South Africa Prof. M.A. van Wyk, Dept. of Electrical and Information Engineering, University of Witwatersrand, Johannesburg, South Africa

INTERNATIONAL PANEL OF REVIEWERSW. Boeck, Technical University of Munich, Munich, GermanyW.A. Brading, AustraliaProf. G. De Jager, Dept. of Electrical Engineering, University of Cape Town, Cape Town, South AfricaProf. B. Downing, Dept. of Electrical Engineering, University of Cape Town, Cape Town, South AfricaDr W. Drury, Control Techniques Ltd, United KingdomPD Evans, Dept. of Electrical, Electronic & Computer Engineering, The University of Birmingham, Birmingham, UK Prof. J.A. Ferreira, Electrical Power Processing Unit, Delft University of Technol-ogy, Delft, The NetherlandsO. Flower, University of Warwick, UK Prof. H.L. Hartnagel, Dept. of Electrical Engineering and Information Technology, Technical University of Darmstadt, Darmstadt, GermanyC.F. Landy, Engineering Systems Inc., USAD.A. Marshall, ALSTOM T&D, FranceDr M.D. McCulloch, Dept. of Engineering Science, Oxford, United KingdomProf. D.A. McNamara, University of Ottawa, Ottawa, CanadaM. Milner, Hugh MacMillan Rehabilitation Centre, CanadaProf. A. Petroianu, Dept. of Electrical Engineering, University of Cape Town, Cape Town, South AfricaProf. K.F. Poole, Holcombe Dept. of Electrical and Computer Engineering, Clemson University, United States of AmericaProf. J.P. Reynders, Dept. of Electrical & Information Engineering, University of the Witwatersrand, Johannesburg, South AfricaI.S. Shaw, University of Johannesburg, SAH.W. van der Broeck, Phillips Forschungslabor Aachen, GermanyProf. P.W. van der Walt, University of Stellenbosch, Stellenbosch, South AfricaProf. J.D. van Wyk, Dept. of Electrical and Computer Engineering, Virginia Tech, United States of AmericaRT Waters, UKTJ Williams, Purdue University, USA

Additional reviewers are approached as necessary

Published bySAIEE Publications (Pty) Ltd, PO Box 751253, Gardenview, 2047, Tel. (27-11) 487-3003, Fax. (27-11) 487-3002, E-mail: [email protected]

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SAIEE AFRICA RESEARCH JOURNAL – NOTES FOR AUTHORS

Vol.100(3) September 2009 SOUTH AFRICAN INSTITUTE OF ELECTRICAL ENGINEERS 61

VOL 100 No 3September 2009

SAIEE Africa Research Journal

SAIEE AFRICA RESEARCH JOURNAL EDITORIAL STAFF ...................... IFC

New generation three-phase rectifi er

by W. Phipps, R.T. Harris and A.G. Roberts .............................................. 62

Symbol error probability for generalized selection

combining reception of M-QAM

by H. Xu .....................................................................................................68

Mathematical modelling of the LC-ladder and capacitive

shunt-shunt feedback LNA topology

by M. Weststrate and S. Sinha .....................................................................72

Design approach to CMOS based class-E and class-F power amplifi ers

by M. Božanić and S. Sinha ........................................................................79

NOTES FOR AUTHORS ...................................................................................IBC

Vol.100(3) September 2009SOUTH AFRICAN INSTITUTE OF ELECTRICAL ENGINEERS62

NEW GENERATION THREE-PHASE RECTIFIER W. Phipps*, R.T. Harris** and A.G. Roberts***

*Department of Electrical Engineering, Nelson Mandela Metropolitan University, Port Elizabeth 6031, South Africa E-mail: [email protected] ** Department of Electrical Engineering, Nelson Mandela Metropolitan University, Port Elizabeth 6031, South Africa E-mail: [email protected] ***Department of Electrical Engineering, Nelson Mandela Metropolitan University, Port Elizabeth 6031, South Africa E-mail: [email protected] Abstract: This paper describes an investigation into the development of a new generation of three-phase rectifier, used to power telecommunications equipment. Traditionally, the topology used is a single-phase two-stage design, with a boost converter at the input to the first stage and an isolated dc-dc converter making up the second stage. The boost converter provides power factor correction which is necessary in order to comply with the IEC1000-3-2 standard. The dc-dc stage provides isolation, as well as the fast feedback necessary to regulate the output voltage ripple. This is necessary in order to comply with the psophometric noise standard ITU-T0.41. A two-stage design however, results in a cascade effect contributing to the total power losses. A new rectifier is introduced that can satisfy the required telecommunication industry standards, whilst also having only a single-stage design. This paper discusses the principles of operation and the performance characteristics of the new generation three-phase rectifier. Key words: three-phase, new generation, telecommunication, rectifier.

1. INTRODUCTION

Traditional rectifiers used in the telecommunications industry are typically a single-phase two-stage design. The reason for a two-stage design is that there are industry specific standards that the rectifiers have to comply with. The major two being the ITU-T0.41 and the IEC1000-3-2 standard [1]. The ITU-T0.41commonly known as the psophometric noise standard was originally introduced to regulate the amount of audible noise on telephone networks. The source of this noise was due to the use at that time of full bridge SCR rectifiers. These rectifiers typically had no output filtering and as a result had considerable noise on the output. The telephone networks were initially analogue and because of the output voltage ripple, audible noise was produced on the phone lines. Nowadays, with digital exchanges the telephone systems have become more immune to dc power supply noise. The psophometric standard is still used however as the defining standard for the interface between telecommunication switching equipment and telecommunication dc power equipment, hence, dc power manufacturers have to comply with this standard in order to market their products. The IEC1000-3-2 standard was introduced to regulate harmonic currents drawn from the mains supply. These harmonic currents reduce the efficiency of the power drawn from the mains and can excite resonances, as well as overloading the circuit wiring and transformers. Having to comply with these standards has dictated the way in which telecommunications manufacturers have had to design their systems.

A typical telecommunications rectifier is a single-phase two-stage topology as shown in Figure 1. The first stage of the rectifier is usually a boost stage, used to provide power factor correction (PFC) and hence regulate the maximum allowable input harmonic current content defined by the IEC1000-3-2 standard. The boost converter is a popular choice for PFC; this is due to it having a simple topology with a high efficiency. A boost converter however, has an inherent weakness in that it cannot provide effective protection from output short-circuit failure nor high input startup currents [2]. The dc-dc converter second stage is required to provide fast regulation of the output voltage to reject the psophometric noise, as well as provide isolation and voltage transformation. The isolation is both a functional and a safety requirement of the telecommunications industry, whilst the voltage transformation is needed, as telecommunication systems typically operate off a 48V DC supply.

PFC

DC

DC

Load

Figure 1: Traditional rectifier.


The traditional single-phase rectifier has at the output of the PFC stage a second harmonic ripple component due to the mains discontinuity at the zero crossing. As a consequence of this, a large storage capacitor is required. Having a two-stage design results in the output power being processed twice, this cascade effect results in a reduction in the overall efficiency. It is well known in the industry that two-stage designs have efficiencies around 90%. Also, a two-stage design requires two independent controllers, one for each stage.

2. ENERGY TRANSFER MODEL

As the traditional two-stage rectifiers have a power factor corrected input, the load appears as being purely resistive. Thus, from a power transfer point of view, the rectifier’s input oscillates at twice the mains frequency, and in a single-phase system, because there can be no natural power transfer from the source to load at the mains voltage zero crossing, an energy storage medium (normally a capacitor) is always required to provide a constant transfer of power to the load. The total dc power delivered to the load can only ever be half the peak input power as illustrated in Figure 2. The area under the DC power line of the positive half line cycle constitutes 68% of the input power, while the area above the DC power line consists of the remaining 32% of the input power. This 32% excess power is stored in the capacitor and then used later in each cycle, when the input power drops below the required output power.

Figure 2: Single-phase normalized power transfer.

In an ideal three-phase system there is a continuous energy transfer from source to load and the total power transferred is the sum of the power from the three individual phases. For a three-phase system with resistive phase loads the power drawn by each phase is given by the following formula:

RV

P p22 sin where Vp= peak input voltage

Assuming that the voltage is unchanging

kR

Vp2

where k is a constant

2sinkP

The total power transfer Ptotal for a three-phase system assuming that the voltage is unchanging and R is fixed is given as

k

k

kkkkPtotal

23

2sin232cos

212sin

232cos

212cos3

2

)4802cos()2402cos(2cos32

)240(sin)120(sinsin 222

It can be seen that the total power drawn by a three-phase system is constant and equal to 1½ times the peak input per phase power as illustrated in Figure 3.

Figure 3: Three-phase normalized power transfer.

A three-phase system has greater supply integrity over a single-phase system, as a single-phase system requires additional phase-neutral protection and is more susceptible to imbalances and harmonics. The availability of a neutral is also known to be an issue in many installations.

3. THREE-PHASE TOPOLOGIES

A number of three-phase topologies exist that could be realized as telecommunication power supplies, with each having its own advantages and drawbacks. However, there are only two single-stage three-phase converters worth mentioning. The first is the Vienna Rectifier which is a three-switch boost-derived rectifier (Figure 4). This rectifier operates by having the input stage creating a dc voltage across the two switches connected to the transformer primary. These two switches, in turn, regulate the voltage being applied to the primary of the transformer and hence control the output voltage [3]. The Vienna Rectifier, even though it operates with only three switches endures higher stresses than that of a six-switch converter (Figure 5). Also, having fewer active switches results in less freedom when it comes to how they can be controlled to produce sinusoidal input currents [4]. The efficiency obtained from this rectifier is around 93%.


Figure 4: Vienna rectifier.

The second is the six-switch buck converter shown in Figure 5. This type of converter directly converts the three-phase ac to dc in a single isolated buck-derived stage by splitting the conversion process into a three-phase cyclo-converter section. This is then used to synthesise the high frequency ac voltage from the three-phase input voltages. The secondary ac signal is rectified and filtered to obtain the desired output dc voltage. The switching sequence of this type of converter can be implemented by either a look-up table or by an analogue derived PWM circuit. This type of converter can be implemented as a hard switched [5] or soft switched type [6][7]. This topology however, has the disadvantage of requiring ac switches and a complex control strategy. An efficiency of 92% has been documented [8], a comparative performance analysis to existing three-phase topologies can be found in [9].

Figure 5: Six-switch buck converter.

A rectifier solution is sought that meets with all the requirements of the telecommunications industry, while not displaying the weaknesses associated with a boost-derived topology and which can be realized with a relatively simple control.

4. NEW RECTIFIER TOPOLOGY

A new three-phase topology is proposed that capitalizes on the ability of a three-phase source to deliver constant power. The topology uses three single-stage converters, with each converter connected across a single phase and controlled to perform a squaring function on the input voltage. Accordingly, this results in a second harmonic

voltage waveform, which has the same profile as the natural power transferred to a resistive load. The rectifier prototype takes the form of a zero voltage switched (ZVS) full bridge converter with a current doubler output topology as shown in Figure 6.

Converter B

Converter C

RL

RC

L1

L2

Vout

D1

D2

Converter A

Figure 6: New rectifier topology.

The concept can be modelled by considering each converter A,B,C as an ideal transformer performing a 1:Vin transfer function on the input voltage (see Figure 7). Consequently, this results in a squaring action on the input voltages taking place; as a result, the secondary voltages have a power waveform profile which sums to a constant, due to the series connection of the transformer secondaries. If the load is considered resistive, the output current is also constant and unity power factor results. Since Vin varies over the range 0 to Vp ,with Vp the peak input phase voltage, then accordingly, this converter can be best realized by using a buck-derived topology.

redphase

yellowphase

bluephase

1:Vin

Load

Figure 7: Concept topology model.

Ideally, the new converter system will have the following characteristics:

Unity input power factor Zero output voltage ripple Single stage converter High output bandwidth Isolation Voltage transformation


The new rectifier constitutes an isolated topology, necessary for compliance with telecommunication functional and safety requirements. This topology offers high modularity and provides mains balancing, giving the possibility to deliver full output power in case of mains voltage imbalances, whilst using only a single controller. A unity power factor will satisfy the IEC1000-3-2 standard, and with theoretical zero output voltage ripple, compliance with the psophometric standard is guaranteed.

5. SIMULATIONS

The rectifier prototype is simulated using a package called PSIM. The system model is shown in Figure 8 consisting of a balanced three-phase 50Hz input voltage with unity magnitude. Three control blocks, each perform the Vin

2 transfer function on the input voltages, with the outputs connected in series to a resistive load.

Figure 8: Prototype simulation model.

Figure 9 shows the result of the simulation, with the red phase voltage and current inputs being in phase. Figure 10 shows the three output phase voltages Vr Vy and Vb summing together to form Vout. As can be seen, the output voltage and therefore output current are constant, with the output voltage being 1½ times the peak input phase voltage. The results of this simulation show that the proposed topology can theoretically produce zero output voltage ripple and a unity power factor.

Figure 9: Input phase voltage and current.

Figure 10: Output waveforms.

6. RECTIFIER OPERATION

A three-phase 500W rectifier prototype using three single-phase full bridge modules, each connected to a phase voltage in a star connected system was constructed. The three modules have their output transformers connected together in series, feeding into a current doubler topology (see Figure 6). The rectifier prototype was controlled using a TMS320F2812 digital signal processor (DSP) which operated at a switching frequency of 100kHZ. The system used a three-phase phase locked loop (PLL) in order to synchronise the Vin

2 switching envelope with the mains voltages. The PLL algorithm was embedded in the DSP. Three PWM output waveforms from the DSP each control a converter module. Each converter module is controlled by switching the left and right leg of the full bridge at a constant 50% duty cycle and phase shifting between them to produce the desired output voltage. The phase shifting was achieved by the use of a GAL26CV12 programmable logic device.

7. RESULTS The converter prototype was tested in order to evaluate its performance against the telecommunication industry standards. It was found that at full load the rectifier prototype produced an input current with a THD=11.9% and PF=0.99 as shown in Figure 11.

Voltage

CurrentTHD=11.9%

PF=0.99

Figure 11: Phase voltage and current.


This is consistent with the simulated waveforms showing a unity PF, however, with a current THD=11.9% the maximum power rating that the rectifier would be able to operate up to would be 6.5kW as above this level the harmonic current magnitudes would exceed the limits stipulated in the IEC1000-3-2 standard. The current THD value can be further reduced by connecting the supply in a delta configuration and in so doing eliminating the dominant third harmonic component present in the neutral. This would therefore increase the operating power range of the rectifier while still complying with the IEC1000-3-2 harmonic limits. It was not possible to test the system against the psophometric noise standard, which dictates that the output voltage ripple not exceed 2mVrms. This was due to the prototyping nature of the rectifier which did not have the necessary output filtering nor the high bandwidth closed loop control necessary for the tight output voltage regulation. The system was therefore run under open loop control. It was found that under full load the output voltage waveform exhibited a second harmonic component with a magnitude of 1.48Vrms. This is due to slight imbalances in the power transferred between the three converter modules (Figure 12).

Figure 12: Output voltage ripple.

It is the authors’ opinion that with the correct output filtering and high speed feedback loops in place, the rectifier would be able to comply with the psophometric standard necessary for any commercial telecommunications power converter. The efficiency is examined in order to determine whether there is a clear advantage over existing two-stage topologies. Typical efficiencies reached by two-stage topologies are around 90%, with each stage having around 5% losses (i.e. 95% efficiency) [10]. The rectifier efficiency curve is shown in Figure 13. The maximum efficiency of 89.3% occurs at 489W of output power. It was found that the majority of the losses (25%) originated in the output diodes as a result of conduction losses due to the high on-state voltage. This loss can be reduced by using silicon schottky diodes which have a reduced on-state voltage compared with the ultra fast diodes used.

The MOSFETs constituted the second highest loss (23%) as a result of having six of them being on at any time. These losses are conduction losses only since with ZVS there are no switching losses. These conduction losses can be reduced by using MOSFETs with lower Rds values.

Efficiency vs Output Power

828384858687888990

0 100 200 300 400 500 600

Output Power (Watts)

Effic

ienc

y (%

)

Figure 13: Efficiency vs output power.

8. CONCLUSION

As a result of the tests performed on the three-phase rectifier prototype is was found that the rectifier would meet with the IEC1000-3-2 standard up to 6.5kW. This power range could be extended by improving the current THD level by running the system on a delta connected supply and in so doing reducing the third harmonic current component which is present in the neutral that connects all three modules together. Testing the system against the psophometric noise standard was not possible due to the rectifier being at the prototype stage. This is something that can only be authenticated through future research work. The efficiency of the rectifier prototype was found to be approximately 89%, with current commercial three-phase topologies discussed in section 3 obtaining efficiencies around 93%. It was identified that the majority of the losses were conduction losses which could be reduced through componentry changes. Therefore, it is believed that future upgrades of the rectifier topology will result in efficiencies matching or possibly exceeding current commercial three-phase telecommunication rectifier models. All this can be achieved by using relatively simple control strategies, reducing the cost of the overall solution.


9. REFERENCES [1] A. Pietkiewitz and D. Tollik, “Single-stage power

factor corrected rectifier topology”, International Telecommunications Energy Conference, Copenhagen, pp. 200-206, June 1999.

[2] W. Phipps, R. Duke and M. Harrison, “New generation power converter”, Australian Journal of Electronical and Electronics Engineering, Vol. 3 No. 2, pp. 83-90, June 2007.

[3] J.W. Kolar, U. Drofenik and F. Zack, “Vienna rectifier II A novel single-stage high frequency isolated three-phase PWM rectifier system”, IEEE Transactions on Industrial Electronics, Vol. 46, No. 4, pp. 674-691, Aug. 1999.

[4] J. Shah and G. Moschopoulos, “Three-Phase rectifiers with power factor correction”, Canadian

Conference on Electrical and Computer Engineering, pp. 2070-2073, May 2005.

[5] S. Manius and P.D. Ziogas, “A novel sinewave in AC to DC converter with high frequency transformer isolation”, IEEE Transactions on Industrial Electronics, Vol. IE-32, No. 4, pp. 430-438, Nov. 1985.

[6] D. Borojevic, V. Vlatkovic and F.C. Lee, “A zero-voltage switched three phase PWM switching rectifier with power factor correction”, IEEE Power Electronics Specialist Conference, Toledo, Vol. 2, pp. 1352-1360, June 1992.

[7] D. Oliveira and I. Barbi, “A three-phase ZVS PWM DC/DC Converter with asymmetrical duty cycle for high power applications”, IEEE Transactions on Power Electronics, Vol. 20, No. 2, pp. 370-377, March 2005.

[8] R. Sheehy, J. Dekter and N. Machin, “Three phase power factor corrected isolated buck for 48V/100A”, International Telecommunications Energy Conference, Quebec, pp. 101-106, Oct. 2002.

[9] B. Singh, B. N. Chandra, K. Al-Haddad, A. Pandley and D.P. Kothari, “A review of three-phase improved power quality AC-DC converters”, IEEE Transactions on Industrial Electronics, Vol. 51, No. 3, pp. 641-660, June 2004.

[10] W. Phipps, R. Duke and M. Harrison, “A proposal for a new generation power converter with pseudo-derivative control”, International Telecommunications Energy Conference, Rhode Island, pp. 1-5, Sep. 2006.


SYMBOL ERROR PROBABILITY FOR GENERALIZED SELECTION COMBINING RECEPTION OF M-QAM H. Xu School of Electrical, Electronic & Computer Engineering, University of KwaZulu-Natal, King George V Avenue, Durban 4041, South Africa E-mail: [email protected] Abstract: In this paper, symbol error probability (SEP) for generalized selection combining (GSC) reception of M-ary quadrature amplitude modulation (M-QAM) signals in a block frequency-flat Rayleigh fading channel is considered. The paper presents a closed-form approximate SEP expression for GSC reception of M-QAM signals in the fading channel. The SEP expression is explicit and simulation results validate that it is very accurate Keywords: Symbol error probability, M-ary quadrature amplitude modulation (M-QAM), Generalized selection combining (GSC) reception, Maximal Ratio Combining (MRC).

1. INTRODUCTION

Wireless communication channels are subject to severe multipath fading, which leads to a serious deterioration in the instantaneous signal-to-noise ratio (SNR) at the receiver. Diversity is an effective low cost technique to mitigate fading. Diversity can be implemented at either transmitter or receiver. Receiver diversity reduces the occurrence of deep fades by providing the receiver with multiple faded replicas of the same information bearing signal and by taking advantage of the low probability that all diversity paths experience a deep fade simultaneously. Maximal-ratio combining (MRC) and selection combining (SC) [1] are basic well-known receiver diversity schemes. MRC provides optimum performance in terms of the signal-to-noise ratio of the combined signal at the receiver. However, MRC also has high implementation complexity since the receiver needs to estimate and combine all paths. SC has lower implementation complexity since the receiver only needs to estimate all paths and select one path, but the lower implementation complexity of SC results in performance losses. To tradeoff between performance and complexity a hybrid selection/maximal-ratio combining was proposed in [2]. The hybrid scheme was also called generalized selection combining (GSC) later. The generalized selection combining is normally expressed as ),( LLGSC C . In ),( LLGSC C , the CL ( LLC ) paths, having the highest instantaneous SNR among total L paths, are selected for combination. The ),( LLGSC C becomes MRC if LLC , while the ),( LLGSC C becomes SC if 1CL . This GSC has been investigated many times since the scheme was proposed. [2] only derived the mean and variance of the combined output SNR of GSC for multiple fading channels. [3] derived the SEP expression of M-QAM for L branch diversity reception in Rayleigh fading channels. But the SEP expression contains a hypergeometric function. [4] derived the SEP expression of M-QAM for L-fold antenna diversity on arbitrary

Nakagami-m fading channel. But the expression includes one-dimensional integration. Using the moment generating function (MGF) of the output combined SNR, [5] derived closed-form expressions for the average combined SNR, outage probability and average bit-error probability of MPSK and M-QAM over independently and identically distributed diversity fading channels. But the average bit-error probability also includes one-dimensional integration. Using the MGF approach, [6] derived a unified error probability of GSC for DPSK, DFSK, and DQPSK4/ in fading channels. [7] derived an exact SEP expression of MRC for M-QAM in the Rician fading channel. But the SEP expression of [7] also contains a hypergeometric function. Using the trapezoidal rule to calculate the finite integral, [8] derived an approximation SER expression with MRC for M-QAM in the Ricean channels. But there are errors in the SER expression (3.15) of [8] with MRC in Rayleigh fading channels. Recent research in low complexity diversity focuses on power saving GSC schemes, for example, output threshold GSC, minimum estimation and combining GSC and adaptive GSC [9-14]. The SEP expressions for GSC Reception of M-QAM in Rayleigh fading channel in all of the above work contains either a hypergeometric function or one-dimensional integration. These SEP expressions are not explicit. Motivated by the work of [8], we derive an approximation SEP for GSC reception of M-QAM in a block frequency-flat Rayleigh fading channel in this paper. Although the SEP expression is an approximation, our simulation results validate that it is very accurate. This paper is arranged as follows: In Section II the system model and channel model are given, in Section III SEP approximate expression of M-QAM in additive white Gaussian noise (AWGN) is derived, in Section IV SEP approximate expression for GSC reception of M-QAM in block frequency-flat fading channel is derived, in Section V simulation results are given and finally in Section VI the conclusion is drawn.


2. SYSTEM MODEL

We consider a ),( LLGSC C reception system with one transmit antenna and L available diversity branches at the receiver. M-QAM symbols are transmitted on block Rayleigh frequency-flat fading channel, which is adopted from [10, Fig.1], where M denotes the number of possible transmitted waveforms. An M-QAM symbol is generated according to M2log data bits. We assume the channel state information (CSI) for all L branches is perfectly estimated during the guard period at the receiver, but only up to CL branches ( LLC ) are combined at the receiver. The ),( LLGSC C becomes MRC if LLC , while the

),( LLGSC C becomes SC if 1CL . We also assume block frequency-flat Rayleigh fading for each branch. The independent identically distributed (i.i.d) fading across all of diversity branches is considered in this paper, but the work can be extended to independent nonidentically distributed fading across all of diversity branches. Let l ),,2,1( Ll be the Rayleigh fading coefficient of the lth diversity branch, and

02 /|| NESll ),,2,1( Ll be the received

instantaneous signal-to-noise ratio of the lth diversity branch, where 0/ NES is the signal-to-noise ratio per symbol. Then the probability density function (pdf) of

l is given by [1, Table 2.2] :

l

l

lll

f exp1)( (1)

where 0/ NEE Sll (assume 1]|[| 2lE ,

),,2,1( Ll ). Let l for i.i.d Rayleigh fading. If CL diversity branches are combined the pdf of the combined SNR

CL

ll

1

is given by [1, Eq. (9.5)]:

/exp)!1(

1)( 1c

c

LL

cLp (2)

3. SEP OF M-QAM IN AWGN

M-QAM is a high rate transmission scheme, which can be viewed as a combination of phase and amplitude modulation. In the AWGN channel, 0/ NES . The exact symbol error probability for square M-QAM ( M2log is even) in the AWGN channel is given by [1, Eq. (8.10) ]:

13114

13114)( 2

2

MQ

MMQ

MepQAM

(3)

where )(xQ and )(2 xQ is given by [1, Eq.(4.2) and (4.9)]:

dxxQ2/

0 2

2

sin2exp1)( (4)

dxxQ4/

0 2

22

sin2exp1)( (5)

Note that (3) is also upper SEP bound for rectangular M-QAM ( M2log is odd) [4, Eq.(2)]. Applying the trapezoidal rule to )(xQ and )(2 xQ , (3) becomes [8]:

12/

1

1

/2/

)1(22

)(n

ni

Sbn

i

Sbbb

QAMii eeaeae

naep (6)

whereM

a 11 , 1

3M

b , iiS 2sin2 ,

ni

i 4, and n is the maximum number of summation.

4. SEP FOR GSC RECEPTION OF M-QAM IN

RAYLEIGH FADING CHANNEL In the ),( LLGSC C reception system, branches with strongest cL instantaneous SNRs among L branches are selected. The GSC becomes selection combining when 1cL , while the GSC becomes MRC when

LLc . The conditional SEP of M-QAM in the ),( LLGSC C reception system is

12/

1

1

/2/

)1(22

)|(n

ni

Sbn

i

Sbbb

GSCii eeaeae

naep (7)

where CL

ll

1

, and the PDF of the combined SNR

CL

ll

1

for ),( LLGSC C is given by [1, Eq.(9.325)] :

kLe

LL

pc

L

L

c c

c

GSC )!1()(

/1 (8)

wherec c

cc

c

LL

l

L

m

m

c

LlL

cclL

Ll

mee

lL

lLL

k1

2

0

/1

1

!1)1(1

The average SEP of M-QAM in the ),( LLGSC C reception system is

0)()|()( dpepep

GSCGSCGSC (9)

Substituting (7) and (8) into (9), the average SEP of M-QAM is derived as


BAepLL

ep MRCC

GSC )()( (10)

where c c

c

LL

l

LcclL Cl

LlLL

naA

1

11)1( (11)

c cc

LL

l

LcclL Dl

LlLL

naB

1

11)1( (12)

1

1

12

)()()1(

)(2)(2n

i

n

ni cic

ci

cic

ci

cc

c

cc

c

lLSbLLS

lLSbLLSa

lLbLLa

lLbLL

C

(13)

12 2

0

1

1

1

2

0

1

2

0

1

2

0

1

)1(

11

2

22

21

n

ni

L

m

m

i

im

c

n

i

L

m

m

i

im

c

L

m

mm

c

L

m

mm

c

c

c

c

c

bSS

Ll

bSS

Lla

bLla

bLl

D

(14)

)(epMRC is the average SEP of M-QAM for MRC reception, which is shown in (15).

12

1

1

)1(

11

2

22

21

)(

n

ni

L

i

i

n

i

L

i

i

L

L

MRC

C

C

C

C

SbS

SbSa

ba

b

naep (15)

5. SIMULATION

In this section, we conduct simulations to validate our SEP expression for GSC reception in block frequency-flat Rayleigh fading channel. The additive white Gaussian noise is modelled as zero-mean complex Gaussian random variable with variance 0N /2 per dimension. All CSI is assumed to be perfectly estimated during the guard periods at the receiver. We use 16-QAM as an example of square M-QAM to simulate )3,( LLGSC C reception, where 3,2,1CL . The simulation results are shown in Fig.1. Fig.1 shows the simulation results are overlapped with theoretical ones. This validates that our SEP for square M-QAM is very accurate. We also use 32-QAM and 8-QAM as examples of rectangular M-QAM to

simulate the GSC reception. The simulation results for 32-QAM and 8-QAM are shown in Fig. 2 and Fig. 3, respectively. Fig.2 also shows that the simulation results are overlapped with theoretical ones. But Fig.3 shows that the simulation results are slightly different from theoretical ones. This is because (3) is upper SEP bound for rectangular M-QAM ) [4, Eq.(2)].

0 5 10 15 20 25

10-4

10-3

10-2

10-1

100

Average SNR per symbol (dB)

Sym

bol E

rror

Pro

babi

lity

GSC (1,3)16-QAM TheoryGSC (1,3)16-QAM Simulation

GSC (2,3)16-QAM Theory

GSC (2,3)16-QAM Simulation

GSC (3,3) 16-QAM TheoryGSC(3,3)16-QAM Simulation

Fig.1 Simulation and theoretical SEP for GSC reception

of 16-QAM.

0 5 10 15 20 25

10-4

10-3

10-2

10-1

100


Sym

bol E

rror

Pro

babi

lity




GSC (3,3) 32-QAM TheoryGSC(3,3)32-QAM Simulation

Fig.2 Simulation and theoretical SEP for GSC reception

of 32-QAM.

0 2 4 6 8 10 12 14 16 18 2010

-5

10-4

10-3

10-2

10-1

100


Sym

bol E

rror

Pro

babi

lity




GSC (3,3)8-QAM TheoryGSC(3,3)8-QAM Simulation

Fig.3 Simulation and theoretical SEP for GSC reception of 8-QAM.


6. CONCLUSION In this paper, we considered SEP for GSC reception of M-QAM signals in a block frequency-flat Rayleigh fading channel. Using the simplified Gaussian Q and 2Q functions, we derived a closed-form expression of the SEP for GSC reception of M-QAM signals. Simulation results validate that our SEP expression is very accurate for square M-QAM and rectangular 32-QAM.

7. REFERENCES [1] M. K. Simon and M.-S. Alouini: Digital

Communication over Fading Channels: A Unified Approach to Performance Analysis, A Wiley-Interscience Publication, 2000.

[2] Moe Z. Win and J. H. Winters: “Analysis of Hybrid Selection/Maximal-Ratio Combining in Rayleigh Fading”, IEEE Trans. on Commu., Vol. 47, No. 12, pp. 1773-1776, Dec. 1999.

[3] J. Lu, T. T. Tjhung and C. C. Chai: “Error probability performance of L-branch diversity reception of MQAM in Rayleigh fading”, IEEE Trans on Commu., Vol. 46, No. 2 pp: 179-181, Feb. 1998.

[4] A. Annamalai, C. Tellambura, and V. Bhargava: “Exact evaluation of Maximal-ratio and equal-gain diversity receivers for M-ary QAM on Nakagami fading channels”, IEEE Trans. on Commu., Vol.47, No.2 pp: 1335-1344, Sep. 1999.

[5] M.-S. Alouini and M. K. Simon, “An MGF-based performance analysis of generalized selective combining over Rayleigh fading channels,” IEEE Trans. Commun., vol. 48, pp. 401-415, Mar. 2000.

[6] A. Annamalai, Gautam Deora, and C. Tellambura: “Analysis of Generalized Selection Diversity Systems in Wireless Channels”, IEEE Trans. on Vehicular Technology, Vol. 55, NO. 6, pp. 1675-1775, Nov. 2006.

[7] S. Seo, C. Lee, and S. Kang: “Exact performance analysis of M-ary QAM with MRC diversity in Ricean fading channels,” Electronics Letters, vol.40, no. 8, pp. 485-486, Apr. 2004.

[8] I. Al-Shahrani: Performance of M-QAM over generalized mobile fading channels using MRC diversity, MSc thesis, King Saud University, 2007.

[9] H. C. Yang, and M.-S. Alouini: “MRC and GSC Diversity Combining With an Output Threshold”, IEEE Trans. on Vehicular Technology, Vol. 54, NO. 3, pp. 1081-1090, May 2005.

[10] M.-S. Alouini, and H. C. Yang: “Minimum Estimation and Combining Generalized Selection Combining (MEC-GSC)”, 2005 ISIT, Proceedings International Symposium on Information Theory, 4-9 Sept., 2005. Page: 578-582.

[11] R. K. Mallik, P. Gupta, and Q. T. Zhang: “Minimum Selection GSC in Independent Rayleigh Fading”, IEEE Trans. on Vehicular Technology, Vol. 54, NO. 3, pp. 1013-1021, May 2005.

[12] H.-C. Yang: “New results on ordered statistics and analysis of minimum selection generalized selection combining,” IEEE Trans. Wireless Commun., vol. 5, no. 7, pp. 1876-1885, Jul. 2006.

[13] H.-C. Yang, and L. Yang: “Exact Error Rate Analysis of Output-Threshold Generalized Selection Combining (OT-GSC)”, IEEE Trans. Wireless Commun., vol. 6, no. 9, pp. 3159-3162, Sep. 2007.

[14] A. S. Lioumpas, G. K. Karagiannidis, and T. A. Tsiftsis: “Adaptive Generalized Selection Combining (A-GSC) Receivers”, IEEE Trans. Wireless Commun., vol.7, no. 12, pp: 5214-5219, Dec. 2008.


MATHEMATICAL MODELLING OF THE LC-LADDER AND CAPACITIVE SHUNT-SHUNT FEEDBACK LNA TOPOLOGY

M. Weststrate* and S. Sinha**

* Carl and Emily Fuchs Institute for Microelectronics, Dept. of Electrical, Electronic & Computer Engineering, Corner of University Road and Lynnwood Road, University of Pretoria, Pretoria 0002, South Africa E-mail:[email protected] ** Carl and Emily Fuchs Institute for Microelectronics, Dept. of Electrical, Electronic & Computer Engineering, Corner of University Road and Lynnwood Road, University of Pretoria, Pretoria 0002, South Africa E-mail: [email protected]

Abstract: In this paper a new low noise amplifier configuration is proposed to achieve wideband operation. This configuration consists of an LC-ladder filter and a common-emitter stage employing shunt-shunt capacitive feedback to realize wideband matching. Design equations for this configuration are derived, as well as equations for the important performance measures namely noise figure, gain and IIP3. The results of a design for achieving typical low noise amplifier specifications in the ultra-wideband are calculated from these equations and plotted. Without any optimization S11 of less than -10 dB over the entire frequency band and a minimum noise figure of 2.7 dB are predicted when achieving S21 of 20 dB. These results indicate that very good performance can be attained through the use of this technique. Simulations were also done to verify the calculated results.

Key words: low noise amplifier, ultra-wideband, input matching, LC-ladder filter, capacitive feedback.

1. INTRODUCTION

Low noise amplifiers (LNAs) play a vital role in any wireless receiver since it dominates the noise figure (NF) of the entire system [1] and as such has remained an active area of research for many years. While LNA design techniques in narrowband applications have been researched for some time, wideband techniques have received more thorough investigation in the last few years as well; especially since the approval of the application of ultra-wideband (UWB) technology for commercial use in 2002. The ultra-wideband ranges from 3.1 to 10.6 GHz and the implementation of UWB systems and its sub-systems has been a challenge for integrated circuit designers since its approval [2].

Wideband LNAs typically require a 50 input impedance over the entire bandwidth to efficiently interface with antennas. A flat gain is also required over the entire frequency band of interest, as well as a low average NF. This poses unique design challenges compared to the narrowband case in addition to any further linearity or power consumption requirements.

Although improvements in transistor speed and device scaling has served to improve noise performance of LNAs over the past years, the NF ultimately depends on the input matching network [3]. Various traditional matching schemes exist; however the shortcomings of these techniques have been discussed in [4], and it was shown that narrowband techniques are often applied directly to wideband design resulting in suboptimal performance. Therefore a new implementation is proposed that combines a common-emitter (CE) amplifier employing

capacitive shunt-shunt feedback and a LC-ladder configuration at the input providing wideband matching.

This work describes the design principles of this implementation in detail and straight forward design equations are also derived. A LNA designed for operation over the UWB is presented to illustrate the results that can be obtained using this configuration, based on the mathematical analysis presented; this is also validated with simulation results. Designing for the UWB was an arbitrary selection however since, as will be shown, such LNAs can be designed for an arbitrary bandwidth.

2. DESIGN PRINCIPLES

2.1 Input matching

Wideband input matching is achieved through the use of a fourth order LC-ladder filter allowing the realization of an arbitrary wide matched bandwidth at the input [5]. This is combined with the capacitive shunt-shunt feedback technique [2], [6] shown in Fig. 1, which is used to generate the resistance and capacitance of the series RLC part of the circuit, rather than using inductive emitter degeneration.

As shown in Fig. 2 the LC-ladder consists of four reactive elements where C2 and L1 determine the lower cut-off frequency of the matched band and C1 and L2 the upper cut-off frequency. The appropriate values for these components are given by [5]

SLL

S

RfCand

fRL

21

2 21 (1a)


Figure 1: Schematic of a capacitive shunt-shunt feedback amplifier used to produce an equivalent series RLC

circuit [2].

SHH

S

RfCand

fRL

21

2 12 (1b)

where RS is the source resistance and fL and fH the lower and upper cut-off frequencies of the matched bandwidth respectively.

A benefit of using this configuration is that it takes advantage of what would in many cases be regarded as unwanted parasitic components and incorporates them into the matching network. The shunt capacitor C1 can be implemented as the pad capacitance, and the shunt inductor L1 as the DC bias choke. Both inductors L1 and L2 are implemented using spiral inductors for which good optimization techniques exist [7]. The series capacitance however is derived from the equivalent capacitance resulting from the feedback network.

Through straight forward small signal analysis it is easily shown that, while j RLCL << 1 + gmRL, the equivalent capacitance and resistance at the base of the transistor is respectively given by [2]

M

FLmeq

CCCCRgCCC 12

, (2a)

BC

L

m

M

M

BC

L

Lm

Leq

CC

g

CCC

CC

RgRR

11

1)1(

2

. (2b)

With reference to Fig. 1 in these equations gm is the transistor transconductance, C the base-emitter capacitance, C the base-collector capacitance, and CF an intentionally added capacitance in parallel with C to increase the total base-collector capacitance (CBC). RL and CL are the respective parallel connected load resistance and capacitance, including the input impedance of a

Figure 2: Fourth order LC-ladder filter used to generate an arbitrary wide resistive impedance [5].

following amplifier stage. The approximation of Req holds if gmRL is much larger than one and the Miller-capacitance is much larger than C .

The result is similar to that achieved in [5] where inductive emitter degeneration was used to generate the series RLC circuit, however in this design the base-emitter voltage does not roll-off at 20 dB per decade. In the emitter degeneration case, the current flowing into the transistor is approximated as vS/(2RS) over the band of interest. The voltage over the base-emitter capacitance and thus the base-emitter junction is then given by

ffv

CjRvv

Ls

S

s

2

12 2 , (3)

indicating the voltage roll-off [5].

In the capacitive feedback case however the transistor and feedback network, as opposed to the emitter inductor, is used to generate the resistive component and thus the voltage over the base-emitter junction is the voltage over both the equivalent resistance and capacitance, which results in

2

12

12

2

2

2

s

S

Ss

SS

s

vCRj

CRjv

CjR

Rvv

, (4)


and is a decreasing function at -20 dB per decade from infinity to a corner at -6 dB at the lower cut-off frequency, from where the zero results in a constant voltage drop over the junction with frequency.

In this derivation the base series resistance (rb) of the transistor was neglected, and thus it is worth noting whether this still applies in the super high frequency (SHF) range. The effect of this resistor becomes noticeable when the impedance of C drops at high frequencies, causing a greater portion of the input voltage to fall across rb. This decreases the voltage gain by introducing a pole at

b

bbe

rCj

CjrCjv

11

11'

. (5)

However for a typical C of 40 fF and a base resistance of less than 50 this pole is above 30 GHz and as such rb can be safely neglected.

2.2 First stage gain

The gain of this amplifier stage, characterised as S21, is given by

LMinv ZGAS ,21 2 , (6)

where Av,in is the gain of the input ladder network, i.e. from the source to the base-emitter junction. GM is the transconductance of the amplifier and ZL the load impedance.

The complete transfer function of the ladder network is given by

inTS

inT

S

Sinv ZLjZ

ZRZA

,2

,, , (7)

where a Norton and subsequent Thévenin transform was used to place the source in series with the impedance of the parallel RLC circuit (ZS) comprised of RS, L1 and C1. ZT,in is the total equivalent input impedance as defined in (2a) and (2b).

The transconductance and load impedance are given respectively by

BCmM CjgG , (8)

)(1)(1

LBCL

L

LBCLL CCRj

RCCj

RZ .

(9)

Since the transfer function of the ladder network was shown to be approximately constant over the band of interest it is apparent that there is a single dominant pole at the output of the amplifier given by

LBCLP CCR

11 . (10)

Unfortunately a small collector current is required to generate the equivalent 50 resistance (as shown in Section III), and as such a large RL is typically required to achieve large gain. Therefore the pole is often within the band of interest resulting in a -20 dB per decade roll-off in the frequency response.

Even if this is not the case, the gain-bandwidth product (GBP) or fT of the transistor will often not allow large gain for operation up to the high SHF range. If the gain is higher than fT/fH there will be a -20 dB per decade roll-off of gain regardless of the position of the output pole.

2.3 Gain flattening

From the preceding discussion it is desirable to equalize the gain of the amplifier by introducing a zero into the system to cancel the output pole of the first stage. This can be done by adding a second amplifier stage with an inductive load, resulting in the complete amplifier circuit shown in Fig. 3. The voltage gain of the second stage is

232, mv gLjA , (11)

where gm2 is the transconductance of the second stage transistor and L3 the load inductance. The overall gain can then be defined as

)(1))((2

11

2311,21

LBCL

mBCmLinv CCRj

gLjCjgRAS (12)

where gm1 is usually sufficiently larger than the base-collector impedance for the frequency dependence of that term to be neglected.

If the second stage gain is designed to be unity at the peak of the first stage gain, the overall gain will have the value of that peak gain equalized over the entire band of interest. Alternatively, the overall gain can be distributed between the two stages with an arbitrary ratio and used to optimize the overall linearity or NF.


Figure 3: Schematic of the proposed amplifier showing the LC-ladder matching network, capacitive shunt-shunt feedback and the second amplifier stage used to generate

a zero in the frequency response for pole-zero cancellation.

2.4 Additional gain stages

The LNA configuration of Fig. 3 provides wideband conjugate input matching as well as gain with a flat frequency response. Depending on the transistor process that is used it might however not be possible to achieve the desired gain specification. In such a case additional common-emitter stages employing resistive loads may be added to increase the overall gain further.

3. DESIGN EQUATIONS

For a given frequency band and gain specification, compact equations can be derived for the design of an amplifier using the configuration discussed in the previous section.

The frequency specification is met through proper selection of the reactive elements in the ladder input matching network. As an initial estimate (1a) and (1b) can be used; and through subsequent plotting of the various performance measures these values can be altered to optimize the design.

The characteristics of the first amplification stage are determined by the collector current (IC) as well as three components: RL1, CL1 and CF in conjunction with the parasitic C of the transistor. The load resistance together with the collector current is used to set the gain of the first stage.

In the design process this voltage gain (Av1) is selected first. The equivalent capacitance used to synthesize C2 is determined by CF and Av1 and thus the equation for CF can be derived from (2a) as

11

12

1C

ACCC

vF . (13)

The equivalent resistance in (2b) is a function of the feedback and the load capacitance as well as gm and thus can be used to derive an equation for IC as

S

T

BC

LC R

VCCI 1 . (14)

Although CL also strongly affects Req it should not be used to alter Req but rather kept to a minimum to avoid making the dominant pole frequency even lower.

Once the collector current has been determined RL1 is set based on the initial selection of Av1.

4. PERFORMANCE MEASURES

4.1 Noise figure

The circuit shown in Fig. 4 includes all the relevant noise sources of the first amplifier stage and could be used to calculate the NF. The analysis however is complicated by the presence of the feedback capacitance, as well as the RS and R1 noise sources which form part of the parallel RLC circuit. To simplify the final NF equation the equivalent circuit in Fig. 5 can be used.

Where shunt-shunt feedback is applied to an amplifier the equivalent noise voltage source is not affected [8] and is thus given by [9]

2

2

02

22

24

224

m

Cb

bC

m

CbCEEQ

gqIkTr

rqIgqIkTrvv

, (15)

where k is Boltzmann’s constant, T is absolute temperature in degrees Kelvin and q is the electron charge; rb is the base series resistance and 0 is the DC current gain of the transistor.

Figure 4: Equivalent circuit of the first amplification stage showing parasitic components and noise sources.


Figure 5: Equivalent circuit used in the derivation of the NF equation.

The equivalent noise current increases however due to the current flowing through the feedback network resulting from the equivalent noise voltage [8] and is given by [9]

2222

0

22222

)(12 CEFm

C

CEFCEEQ

vCg

CCqI

vCii

.

(16)

By first using a Norton and then Thévenin transformation the RS and R1 noise sources can be moved in series with the rest of the input loop as in Fig. 5 and results in

212

1

22

,12

2

22

, RS

EQRRSS

SEQRS v

Z

Zvandv

RZ

v , (17)

where Z1 = R1 + j L1.

The noise factor of the first stage can now be defined as

2,

2,

22,

21,

2,

2,

1

RS

RSRRieqveq

v

vvvvvF , (18)

where each term represents the equivalent power spectral density of the respective noise sources over the base-emitter junction. From the discussion above with Z2 = R2 + j L2 the noise factor becomes

22

2

22

212

1

222

22

1 1

RSS

S

RRS

EQSEQ

vR

Z

vvZ

ZiZZv

F , (19)

and with the further substitution of (15) and (16) and simple algebraic manipulation can be written as

2

2

2

22

21

212

2

2

222

221

1

111

RS

S

S

RRCE

S

CEFSS

vR

Zv

Zvi

ZZ

vCZZ

ZF

. (19)

4.2 Linearity

Although NF and gain can be quantified relatively well using small signal analysis amplifier linearity, being a large signal phenomenon, is harder to evaluate. A Volterra-series can be used to analyze circuits operating in weak non-linearity [10], however the derivation of the Volterra-series is very laborious and offer little insight that cannot be gained through large signal circuit simulations. Therefore only an approximation that can be used as an initial estimate of the IIP3 is derived here.

The third order input intermodulation product (IIP3) voltage of a CE amplifier can be approximated as [11]

TCEIIP VV 22)(3 , (20)

where VT is the thermal voltage. Since the proposed amplifier consists of two cascaded CE stages in which the first stage acts as a pre-amplifier which reduces the linearity of the last stage, the final IIP3 voltage of the amplifier is given by

1,

1,,

)2(3)(3

24

v

T

vinv

CEIIPLNAIIP

AV

AAV

V, (21)

resulting in

dBmRA

VIIPSv

T 32

1,

2

1016log103 . (22)

5. RESULTS

To gain insight into the potential performance of this configuration an amplifier with S21 of 20 dB was designed using the equations derived in this paper for an arbitrary bandwidth of 3 to 10 GHz (the UWB). The IBM 8HP BiCMOS process with transistor emitter lengths of 12 m was assumed. The component values that were obtained are given in Table 1 and the critical performance measures as calculated are plotted in Fig. 6 to Fig. 9.


Table 1: Component values used in the UWB LNA design.

Symbol Value C1 320 fF CF 93 fF L1 2.65 nH L2 795 pH L3 561 pH RL1 325 IC1 0.9 mA IC2 4 mA

Even without any optimization good results were obtained. The input reflection was calculated to be less than -10 dB over the entire frequency band, and as desired a flat S21 response of 20 dB was obtained. The calculated maximum NF of the first stage is 3.92 dB and the minimum 2.84 dB close to the centre of the frequency band. IIP3 increases linearly with the log of frequency from -27.4 dBm to -18.4 dBm over the band of interest. This improvement of IIP3 with frequency is due to the -20 dB per decade roll-off in the first stage voltage gain, thus causing less reduction of the overall IIP3.

To verify the equations derived in this paper the design was also simulated in Cadence using Spectre RF and the HIT-kits supplied by IBM. The comparison of the calculated results with the S-parameter simulations are shown in Fig. 10 and the NF comparison in Fig. 11 which shows that the simulated NF is better than predicted. In both cases there is good tracking between the results.

The calculated results were obtained with a 0 of 300 and a pessimistic inductor quality factor of 5. A supply voltage of 1.5 V was used; thus the power consumption resulting from the collector currents in Table 1 is only 7.35 mW excluding biasing circuitry.

Figure 6: Calculated input reflection coefficient versus frequency from 3 to 10 GHz.

Figure 7: Calculated voltage gain of the individual stages as well as the overall S21 of the amplifier versus

frequency.

Figure 8: Calculated noise figure of the first amplifier stage versus frequency from 3 to 10 GHz.

Figure 9: Calculated third order input intermodulation product versus frequency from 3 to 10 GHz.

(3;-14)

(10;-11)

(5.18;-29) (3;-27.4)

(20;-18.4)

(5.18;2.84)

(10;3.92)


Figure 10: Comparison of the calculated and simulated S-parameter results.

6. CONCLUSION

The design principles of a newly proposed wideband LNA topology combining a LC-ladder network and capacitive shunt-shunt feedback were discussed and compact design equations were derived. Equations for the important performance measures were also given and verified with simulations using parameterized cells which include device parasitics. Based on this analysis, this configuration has great potential for achieving good performance, especially when component values are further optimized through simulation. A comparison of the results to other LNAs in literature is given in Table 2 and shows improved noise performance.

7. ACKNOWLEDGMENT

The authors would like to thank ARMSCOR, the Armaments Corporation of South Africa Ltd, (Act 51 of 2003) for sponsoring this study.

8. REFERENCES

[1] H. T. Friis, “Noise figure of radio receivers,” Proc. of the IRE, vol. 32, no. 7, pp. 419-422, July 1944.

[2] Y. Lin, H. Chen, T. Wang, Y. Lin and S. Lu, “3-10-GHz Ultra-Wideband Low-Noise Amplifier Utilizing Miller Effect and Inductive Shunt-Shunt Feedback Technique,” IEEE Trans. on Microwave Theory and Techniques, vol. 55, no. 9, pp. 1832-1843, September 2007.

Figure 11: Comparison of the calculated and simulated noise figure results.

[3] H. A. Haus et al., “Representation of noise in linear two-ports,” Proc. of the IRE, vol. 48, no. 8, pp. 69-74, January 1960.

[4] M. Weststrate and S. Sinha, “Mathematical Analysis of Input Matching Techniques With Application in Wide-band LNA Design,” Proc. of the South African Conference on Semi- and Superconductor Technology, Stellenbosch, pp. 128-132, April 2009.

[5] A. Ismail and A. A. Abidi, “A 3-10-GHz low-noise amplifier with wideband LC-ladder matching network,” IEEE J. of Solid-State Circuits, vol. 39, no. 12, pp. 2269-2277, December 2004.

[6] B. Kang, S. Yang, J. Yu, W. Choo and B. Park, “Design and analysis of a high-performance cascode bipolar low noise amplifier with shunt feedback capacitor,” IEEE Radio Frequency Integrated Circuits Symp., Atlanta, pp. 613-616, June 2008.

[7] M. Božani and S. Sinha, "Software Aided Design of a CMOS Based Power Amplifier Deploying a Passive Inductor," SAIEE Africa Research Journal, vol. 99, no. 1, pp. 18-24, March 2008.

[8] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, “Analysis and design of analog integrated circuits,” John Wiley & Sons Inc, 4th ed., 2001, pp. 776-779.

[9] G. Niu, “Noise in SiGe HBT RF Technology: Physics, Modelling, and Circuit Implications,” Proc. of the IEEE, vol. 93, no. 9, pp. 1583-1597, September 2005.

[10] G. Niu, Q. Liang, J. D. Cressler, C. S. Webster, and D. L. Harame, "RF linearity characteristics of SiGe HBTs," IEEE transactions on microwave theory and techniques, vol. 49, no. 9, pp. 1558-1565, September 2001.

[11] B. Razavi, “RF Microelectronics,” Upper Saddle River, NJ: Prentice-Hall, 1st ed., 1998, pp. 175.

[12] J. Lee and J. D. Cressler, “Analysis and Design of an Ultra-Wideband Low-Noise Amplifier Using Resistive Feedback in SiGe HBT Technology,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no. 3, pp. 1262-1268, March 2006.

Table 2: Comparison of results to state-of-the-art UWB LNA implementations

Ref. Technique Techa [ m]

BW [GHz]

S11 [dB]

S21 [dB] NF [dB] IIP3

[dBm] P [mW]

This work

LC-ladder & capacitive-feedback 0.13 3–10 < -10 20 2.8–3.9 -21.9

@ 5.4 GHz 7.4

[2] Shunt-shunt capacitive-feedback 0.35 3–14 < -9 23 2.5–5.8 -17

@ 5 GHz 25.8

[5] LC-ladder & emitter degeneration 0.18 3–10 < -9 21 2.5–4.5 -5.5

@ 3.4 GHz 30

[12] Resistive feedback 0.18 3–10 < -10 20 3.4–4.7 -17 @ 3.5 GHz 42.5

(4.3;-2.69)


DESIGN APPROACH TO CMOS BASED CLASS-E AND CLASS-F POWER AMPLIFIERS M. Božani * and S. Sinha** *,**Carl and Emily Fuchs Institute for Microelectronics, Dept. of Electrical, Electronic & Computer Engineering, Corner of University Road and Lynnwood Road, University of Pretoria, Pretoria 0002, South Africa * E-mail: [email protected] **E-mail: [email protected] Abstract: This paper presents the design flow for an integrated power amplifier. The flow is presented as a software routine. For a given set of amplifier specifications and CMOS process parameters, the routine computes the passive component values for a Class-E or Class-F based power amplifier. The routine includes the matching network for standard impedance loads. The routine also provides its user with a spiral inductor search algorithm, which can be used to generate layouts of inductors with Q-factors optimised at a desired frequency. For a typical power amplifier design case where several amplifiers are designed for application over different channels, the routine presented in this paper contributes by streamlining the design flow. The operation of the software routine was demonstrated by simulations in Austriamicrosystems 0.35 μm single-supply process for a 14 dBm, 2.4 GHz power amplifier design. Keywords: Power Amplifier, CMOS, spiral inductor, Class-E amplifier, Class-F amplifier, impedance matching, SPICE netlist.

1. INTRODUCTION

The power amplifier (PA) technology has matured rapidly over recent years and has become highly integrated into several process technologies including SiGe BiCMOS, CMOS and GaAs [1]. Original PA designs were based around metal-oxide semiconductor (MOS) transistors, but after the introduction of a bipolar transistor with a wide-gap emitter, or HBT, bipolar transistors emerged as a preferred choice because of their higher gain and current densities at radio frequencies (RF). This resulted in transmitter systems that included at least two ICs in their implementation: a silicon CMOS based front end and, usually, GaAs based PA, which made them bulky and expensive. In the first decade of this century, SiGe HBT devices have emerged as an alternative to GaAs because they are able to bridge this integration gap by including both MOS transistors and HBTs on one die, which as a result reduces the cost of transmitter manufacturing. The costs can however be reduced by disregarding HBTs and implementing PAs in pure silicon CMOS processes using only MOS transistors. In many RF modulation schemes, it is necessary to perform rapid design of several PAs in order to ensure the operation of a system over different channels of the same band. One such system is presented in [2], where transmission occurs over a number of channels in 2.4 GHz Industrial, Scientific and Medical (ISM) band. Additional to active devices (transistors), a number of passive components (inductors and capacitors) are included in PA design. When drawing mask layers on

silicon wafer (layout design), designing of inductors poses a special problem, because the more affordable electronic design automation (EDA) software packages are not provided with built-in procedures for extraction of inductor netlist and layout from their models in schematics. This drawback requires manual modelling of inductors for the post-layout simulations. Inductor modelling becomes particularly important in the design of PAs at RF, due to the fact that even small differences between actual and designed values of inductance can strongly affect the centre frequency, gain or efficiency of an amplifier. Often, these mismatches can only be seen after the fabrication of the chip is completed, thus introducing additional unnecessary chip fabrication iterations which increase the design costs. In this paper, a new design methodology for the rapid design of CMOS Class-E and Class-F PAs [3] is proposed. For a given set of specifications such as PA bandwidth, centre frequency and class of operation, the best possible PA is found and designed. This method is coined as a software routine. The same routine determines geometry of a spiral inductor that gives the highest possible quality factor, using process parameters for a particular process. Extracted layout and netlist can be exported by the routine and imported into layout design software for correct layout-level modelling. This work is the expansion of the work reported in [4]. To verify this software routine, Class-E and Class-F PAs have been designed and simulated in the C35 (0.35 μm CMOS) process from Austriamicrosystems (AMS).

Copyright © 2009 IEEE: An earlier version of this paper was first published in AFRICON '09, 22-25 September 2009,

Nairobi, Kenya


2. POWER AMPLIFIER

2.1 Background Class-E amplifiers [5] and Class-F amplifiers [6] have been used in communication ever since they were theorized in the nineteen-seventies. They are classified as switching amplifiers and as such they can exhibit efficiencies close to 100%. 2.2 Class-E Design Equations Class-E amplifier uses combination of a series resonator and a shunt capacitor to shape the drain voltage and current waveforms in order to deliver the maximum power to the load. A single ended Class-E PA with matching is shown in Figure 1 [5]. Simple PA analysis can be performed if the following is assumed: inductance of the RF choke (RFC) L1 is very high; output capacitance of the transistor is independent of the switching voltage and it can be included in C1; and transistor is an ideal switch with zero resistance and zero switching time, open for half of the signal period. From [5], the value of the optimum load resistance to deliver the highest power to the load Poutmax with peak voltage equal to supply voltage (vpeak = VDD) is:

max

2

max

2

2 577.014

2

out

DD

out

DDL P

VPVR (1)

For the desired Q-factor of the output resonant tank QL, inductance L2 can be calculated:

fRQL LL

22 (2)

Where: f = fo = the centre frequency of the channel Shunt capacitance C1 is given by:

)2(447.51

21421

21LL fRfR

C (3)

Resonant capacitance C2 is given by:

08.242.11447.5

08.242.11

)2(1

12

22LLL QQ

CQLf

C

(4) 2.3 Class-F Design Equations Class-F amplifier includes waveform-shaping circuitry in its output network that shapes drain waveforms in such a way that load appears to be short at even harmonics and open at odd harmonics. As a result, the ideal drain voltage waveform approximates a square wave, while the drain current waveform approximates a half-sine wave. Shaping of waveforms can be done by means of transmission lines, but this is not a practical implementation for the low-gigahertz integration. Instead, several passive resonators are used. Monolithic implementations of the Class-F amplifiers would require an infinite number of resonators to correctly shape output waveforms. Most real life integrated Class-F amplifier implementations consider only a few harmonics, usually two or three. Figure 2 shows the Class-F PA, where bottom resonator constitutes the third harmonic peaking circuit and top two resonators constitute the amplifier with the resonators up to the fifth harmonic [7]. In this circuit, the tank at 3fo provides an open circuit at 3fo and short circuit at 2fo, whilst the tank at 5fo provides an open circuit at 5fo and short circuit at 4fo. Theoretical efficiencies for the two circuits are 81.7 % and 90.5 % respectively [8]. Similar to the case of the Class-E PA, the optimum load resistance can be determined [8]:

max

22

2 out

DDVL P

VR (5)

DC current needed for correct waveform shaping is given by:

LI

DDVDC R

VI (6)

Figure 1: Complete Class-E PA schematic

3

3

5

5

3

3

Resonators up to fifth harmonic

Resonators up to third harmonic

Figure 2: Class-F PA circuits with resonators up to third or

fifth harmonics


Peaks of the drain voltage and current waveforms are given by:

DDVDm Vv (7) And:

DCIDm Ii (8) Coefficients V, I, V and I are maximum efficiency coefficients and are defined in Table I [8]. There is no generic equation that can relate Lo, L3 and L5 to other quantities, except to resonant capacitors (Co, C3 and C5), which can be calculated, if the values for the inductors are chosen, by:

iii Lf

C 221 (9)

Where: i = o, 3 or 5 Capacitor CC is a coupling capacitor of an arbitrary value.

2.4 Design Algorithm PA is designed around a single NMOS. Several input parameters are needed for the Class-E and Class-F design algorithm to converge successfully. These include the centre frequency of the channel (fo), output power (Pout) and supply voltage (VDD). In the case of Class-E design, loaded Q-factor (QL) is also required, and in the case of Class-F design, Lo, L3 and L5 must be specified. Centre frequency is determined by the specifications of the transmitter system of which the PA is a part. Output power (Pout) is also determined by the transmitter system specifications. The higher the output power requirement, the smaller the load (RL) will have to be, which will pose higher demands on the output impedance matching. High output power can also result in the need for a higher supply voltage. Supply voltage can be arbitrarily chosen by the designer, but the choice must be constrained to prevent the transistor from entering the breakdown region. Quality factor is the Q-factor of the series resonator created by the inductance L2 and capacitance C2 of Class-E stage. The Q-factor can be chosen freely by the PA designer, but there is a tradeoff between high efficiency and power (low QL) on one side, and total harmonic distortion (THD) of the output signal on the

other (high QL), which needs to be considered. A plausible Q-factor is in the range of 5 to 10 [9]. If the emphasis is on efficiency, a lower QL can be chosen and harmonics can be removed by additional filters at the output of the amplifier [5]. A narrowband output matching network can serve for this purpose. The Class-E design algorithm utilizes (1) through (4) to calculate RL, L2, C2 and C1. DC current (IDC), peak transistor voltage and current are also presented as the outputs of the software program. The Class-F algorithm utilizes (5) to (9) to calculate RL, capacitors Co, C3 and C5 and the required voltages and currents. As specified before, inductor values are chosen by the designer. The gain of both Class-E and Class-F output stages depends on the width of the RF NMOS available for specific design. In principle, very wide transistors should be used to support high power gains at high operating currents at RF frequencies. It is the responsibility of the designer to support the input of the PA with correct impedance matching and biasing depending on the available gain.

3. SPIRAL INDUCTOR 3.1 Background Traditionally, capacitor and resistor implementations are easily accomplished in CMOS and these components are almost exclusively fabricated on-chip, which is not always the case with the inductors. Inductor size, low Q-factor of integrated passive inductors and other factors often result in alternative implementations, including external inductors, active integrated inductors, microelectromechanical systems (MEMS) inductors and bond wires. These implementations are normally too complex to implement or make the PA devices too bulky and expensive, leaving the passive spiral inductors as a reasonable choice for integration with PAs. A square spiral, shown in Figure 3, has become more popular over some other spiral geometries [10] since some IC processes constrain all angles to 90° [11], but it generally has a lower Q-factor than the circular spiral, which most closely resembles the common off-chip solenoid inductors. It is fully specified by the number of turns (n), the turn width (w) and two of the following: inner, outer or average of inner diameter (din) and outer

Figure 3: Square inductor spiral with geometry parameters

shown

Table I: Maximum-Efficiency Waveforms Coefficients [8]

Coefficient Value (Resonators up to third-harmonic)

Value (Resonators up to fifth-harmonic)

V 1.1547 1.2071 V 2 2 I 1.4142 1.5 I 2.1863 3


diameter (dout). The parameter s is a pitch between the turns of the spiral. 3.2 Inductor Model A lumped single- nine-component inductor model shown in Figure 4 is sufficient to accurately model spiral inductors for frequencies below resonance [10]. In this model, LS is the inductance at a given frequency, RS is the parasitic resistance and CS is parasitic capacitance of the spiral inductor structure. Cox is parasitic capacitance due to oxide layers directly under the metal inductor spiral. Finally, CSi and RSi represent parasitic capacitance and resistance due to the silicon substrate, respectively. The topology shown in Figure 4 correctly models the parasitic effects of the metal spiral and the oxide below the spiral, as well as for the substrate effects, but does not model the distributive capacitive effects. The series inductance is calculated by data-fitted monomial expression that results in an error typically not greater than 3%. It has been developed by curve fitting over a family of 19000 inductors [10]. Inductance in nanohenries (nH) is calculated as

54321 sndwdL avgoutS (10) Where: = 1.62 10-3 1 = -1.21 2 = -0.147 3 = 2.40 4 = 1.78 5 = -0.030

Different coefficients are used to implement other inductor geometries and/or symmetric inductor structures, which is beyond the scope of this paper. Although the inductance as specified in (10) is independent of frequency, parasitics add to the apparent value of inductance as well as decrease the quality factor of the inductor, as described later in this paper. Parasitic resistance is dependent on the frequency of operation. At high frequencies, the resistance is dominated by the resistance resulting from eddy currents. Parasitic resistance depends on resistivity of the metal

layer in which the inductor is laid out ( ), total length of all inductor segments, as well as on the width and effective thickness (teff) of the inductor [12]:

effS wt

lR (11)

Where:

)1( /teff et (12)

= skin depth dependent on frequency f via relation:

r 0 f (13)

And: t = actual thickness of the conductor

r = relative permeability of the metal layer

0 = permeability of free space (4 10-7 H/m)

Parasitic capacitance is the sum of all overlap capacitances created between the spiral and all underpasses. For only one underpass of the same width as the spiral, the capacitance is equal to [12]:

21

2

MoxM

oxS t

nwC (14)

Where: toxM1-M2 = oxide thickness between the spiral and the underpass

ox = dielectric constant of the oxide layer between the two metals The oxide and substrate parasitics are approximately proportional to the area of the inductor spiral (l w), but are also highly dependent on conductivity of the substrate and operating frequency. In order to calculate the oxide capacitance Cox and substrate capacitance CSi, effective thickness (teff) and effective dielectric constant ( eff) of either oxide or substrate must be determined. Effective thickness is in this case is calculated as [13]:

16

144.042.2wt

wt

twwteff

, for 1wt

(15) And:

tw

wtwteff

48ln2

, for 1wt (16)

Figure 4: Nine-component spiral inductor model [8]


Equations (15) and (16) are valid for both oxide and substrate. Effective dielectric constant is determined as:

2/11012

12

1w

teff

(17)

Then:

effox

effoxox t

wlC 0 (18)

And:

Si

Si0Si

effox

eff

twl

C (19)

Similarly, to calculate RSi, effective thickness (teff) and effective conductivity ( eff) of substrate are needed. As for the capacitance, effective thickness is given by Equation (15), and effective conductivity can be obtained from [13]:

2/110121

21

wt

eff (20)

Where: = substrate conductivity Therefore:

wlt

Reff

effSiSi (21)

3.3 Quality Factor Quality factor is the basic characterisation technique for inductors. For a single- model, the inductor Q-factor can be calculated as [14]:

S

SSSP

SSSP

P

S

S

LR

LCCRRLR

RRL

Q2

22 1

1 (22) Where:

2

2SiSi

Si22

1

ox

ox

oxP C

CCRRC

R (23)

2Si

2Si

2

2SiSiSi

2

11

RCCRCCCCC

ox

oxoxP

(24)

And:

= 2 f (25) Low Q-factors of spiral inductors are attributed to the losses of the inductor spiral, substrate loss in the semiconducting silicon substrate and self resonance loss due to total capacitance CS + CP. 3.4 Inductance Search Algorithm Although spiral inductors are a good choice for exclusively on-chip PAs, their usage is not as straight forward. All spiral inductor parameters are interrelated; hence a single parameter to be increased or decreased to change the inductance value in a set manner cannot easily be identified. This complexity of spiral inductor models is one of the reasons why it is a common practice to use an iterative process in their design [4]. As part of this process, one guesses the geometry parameters that could result in the required inductance (and Q-factor) value, calculates inductance and other relevant parameters given guessed parameters, thereafter repeating this process until satisfied with the performance of the inductor. In this section, a new non-iterative routine is proposed that will result in an inductor of the specified value, with the highest possible Q-factor, occupying a limited area, and using the predetermined technology layers. The intention behind this routine is to find a square inductor geometry resulting in the highest Q-factor for the specified inductance given some design constraints. For accurate inductor modelling, the process parameters and frequency of operation of the inductor must be known. Geometry needs to be constrained by the minimum input diameter, maximum output diameter, and minimum turn spacing and turn width. The search algorithm looks into a range of geometries and identifies a geometry that results in the required inductance within certain tolerance by using (10). More than one geometry can result in the correct inductance at a given frequency and the geometry that gives the highest Q-factor is chosen by the algorithm as its output. Accuracy of the algorithm depends on the tolerance for the required inductance values and on the search grid resolution. A simplified flow diagram of the inductance search algorithm is shown in Figure 5. 3.5 Verification In order to verify the correctness of the inductance search algorithm, eleven inductors were designed using parameters for the C35 BiCMOS process from AMS. The geometries of those inductors were the same as the inductors designed and measured by AMS. Their predicted behaviour was compared to the results obtained experimentally by the foundry, as well as to the results obtained by means of EM simulations. Comparison of the Q-factors of these inductors at their optimal frequencies is shown in Figure 6. The average relative errors between calculated values, values measured by the foundry and EM simulated values were determined to be less than 5 % for both inductance and quality Q-factor.


4. PA DESIGN PROGRAM Class-E and Class-F PA design algorithms as well as the inductor search algorithm are included into a C# program used to perform complete PA system integration. The primary user interface of the software is shown in Figure 7. In this dialogue, the user is required to enter parameters for the Class-E or Class-F PA design. On the click of the Calculate button, either the Class-E or Class-F design subroutine, described in Section 2, is executed. After this, the user has a choice to perform output impedance matching to the standard impedance of 50 . The program employs impedance matching using discrete components. Three impedance networks are available: a wideband two-component network (L network, Figure 1) and two narrowband three-component networks (T and networks). Finally, the user can choose to invoke another user form which will utilize the inductor search algorithm to design spiral inductors for all the inductors (including the matching

ones), required for the full PA design. Process parameters can either be specified in a separate screen, or they can be loaded from a configuration file. For the AMS CMOS process, the process parameters for both 3-metal and thick-metal inductors are included. Furthermore, the program can also export SPICE netlist of each inductor structure, complete with the inductance value and the parasitics, and a GDSII file, which contains the mask geometry information of any inductor [15]. The netlist can be used in SPICE simulations without the need for one to draw the schematic of the inductor with its parasitics in the schematic editor. A typical inductor SPICE netlist is shown in [4]. The GDSII file can be imported into the layout software to eliminate the need for manually drawing inductor layout structures.

5. SIMULATION One Class-E and one Class-F PA were designed using the program described in Section 4 in the AMS C35 process. For both PAs, an RF NMOS transistor was used with transistor width-to-length ratio equal to (200 m)/(0.35

m). The design was accomplished at 2.4 GHz to enable operation in the ISM band. A conservative value for output power (25 mW or 14 dBm) was chosen. For the Class-E PA simulation, a moderate quality factor of the resonant tank (QL = 5) was used. The design was powered from 0.8 V in order to make sure that the transistor stays well away from its breakdown region. For the same design, an L-network was used for the matching for simplicity, as shown in Figure 1. Table II lists the calculated values for all required Class-E PA quantities. For Class-F PA simulation, the circuit with resonators up to the fifth harmonic was chosen over the third-harmonic peaking circuit for better waveform shaping. The supply used in this stage was 1.3 V, higher than for Class E,

Enter input parameters

Set to smallest geometry

Calculate L

L in tolerance level?

Change geometry

Calculate parasitics, Q

Q > stored Q?

Store Q, parasitics, geometry

Geometries exhausted?

Output stored L, Q, geometry, parasitics (if found)

Yes

Yes

Yes

No

No

No

Figure 5: Flow diagram of the inductance search algorithm.

1 2 3 4 5 6 7 8 9 10 110

1

2

3

4

5

6

7

Inductor number

Qua

lity

fact

or

EM simulation dataAMS mesaured dataPredicted data

Figure 6: Comparison of Q-factors of eleven M3 inductors

Figure 7: Primary user interface of the PA design software


because the swing on the drain waveform is about 1.8 times lower, allowing for higher voltage supplies to be used. Such a high voltage supply also allowed for matching to be excluded without loss in output power. Table III lists the calculated values of all required Class-F PA quantities. Output waveforms (vO) of two simulated systems are shown in Figure 8 and Figure 9, respectively. In both cases, waveforms were shown for designs using both ideal and spiral inductors. The frequency response for the two PAs is shown in Figure 10, showing the relation between drains and output voltage waveforms. Table IV shows geometries, parasitics and Q-factor of thick-metal inductors L2 and LM used in Class-E amplifier design, as well as 1 nH inductors used in Class-F amplifier design, determined by the inductance search algorithm and used in simulations using spiral inductors. The layout of 4.9 nH created by importing of the GDSII file by layout design software is shown in Figure 11. Furthermore, it

has been assumed that the RFC inductor for both designs is external to the integrated system, and has a very high inductance value. With ideal inductors, the output voltage has the peak of

Table II: Calculated Quantities for Class-E PA

Parameter Value Unit Parameter Value Unit RL 14.8 IDC 31.2 mA C2 1.33 pF LM 2.15 nH L2 4.90 nH CM 2.94 pF C1 0.82 pF RM 50

Table III: Calculated Quantities for Class-F PA

Parameter Value Unit Parameter Value Unit RL 50 C3 0.49 pF Lo 1 nH L5 1 nH Co 4.4 pF C5 0.18 fF L3 1 nH IDC 21.2 mA

0.5 1 1.5 2 2.5 3

-1

-0.5

0

0.5

1

Time (ns)

Vol

tage

(V)

Ideal inductorsSpiral inductors

Figure 8: Output voltage waveforms for Class-E PA with ideal and spiral inductors.

0 0.5 1 1.5 2 2.5 3-1.5

-1

-0.5

0

0.5

1

1.5

Time (ns)

Vol

tage

(V)

Ideal inductorsSpiral inductors

Figure 9: Output voltage waveforms for Class-F PA with ideal and spiral inductors.

108

109

1010

1011

Frequency (Hz)

Vol

tage

(dB)

Drain voltageOutput voltage

(a)

108

109

1010

1011

Frequency (Hz)V

olta

ge (d

B)

Drain voltageOutput voltage

(b) Figure 10: Frequency domain representation of drain and output voltage waveforms for (a) Class-E PA (b) Class-F

PA.

Table IV: Geometry Parameters and Parasitics of Inductors

Parameter Value (L2) Value (LM) Value (1 nH) Unit LS 4.93 2.16 1.00 nH Lself 4.38 2.01 0.94 nH Q 6.8 9.96 13.0 - w 11 25 48 m s 2 2 2 m din 121 206 90 m dout 221 310 286 m n 4 2 2 - RS 5.26 1.77 0.72 CS 17.1 44.2 163 fF CSi 82.6 73.9 67.0 fF Cox 153 209 280 fF RSi 257 287 315

Figure 11: Layout of 4.9 nH inductor used in Class-E PA design.


about 1.2 and 1.4 V for Class-E and Class-F stages respectively, which is equivalent to powers of about 11.6 and 12.3 dBm. This is roughly 2 dBm decrease from the value the design was intended for. This can be attributed to the fact that transistor was assumed to be an ideal switch in both cases. With spiral inductors, Class-E amplifier has the peak of about 0.75 V, which results in the power of about 7.5 dBm. For Class-F amplifier, the peak is about 0.9 V, giving the power of 9.1 dBm. This is a further 3.5 dBm decrease in power for both classes, which can be attributed to the presence of parasitics in inductors. Although the search algorithm finds inductors with the highest Q-factors possible within the space and technology constraints, the Q-factors are still fairly low and highly influential to the total performance of the integrated PA. For Class-E stage, the current drawn from the supply is 26.3 mA, slightly lower than the predicted value, resulting in efficiency of 64 % for ideal design and 24 % for the practical design with spiral inductors. For Class-F stage, the DC current drawn from the supply is 23.5 mA, which corresponds to the predicted value, resulting in drain efficiencies of 64 % for ideal design and 27 % for the practical design with spiral inductors. Evidently, a loss in efficiency of the PA is present in the design involving spiral inductors.

6. CONCLUSION In this paper, a software routine for the design of CMOS PAs was presented. Apart from determining the optimum values of passives needed for correct waveform filtering for Class-E and Class-F PAs, the program handles output impedance matching and spiral inductor design. The inductor search algorithm has been used for filtering and matching inductor design. This allowed for obtaining of spiral inductors with Q-factors that are the highest within geometry and process constraints. The streamlined use of the software-aided design described in this paper was demonstrated by designing two complete 2.4 GHz PAs, which were subsequently simulated using the AMS C35 process. While the results were short of the goal parameters of the amplifier, the value of this paper is aimed to provide a starting point for more detailed analogue simulation of Class-E and Class-F amplifiers.

7. REFERENCES [1] K. Nellis and P. Zampardi, “A Comparison of Linear

Handset Power Amplifiers in Different Bipolar Technologies,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 10, pp. 1746-1754, Oct. 2004.

[2] N. Naudé, M. Božani and S. Sinha, “Analogue CMOS direct sequence spread spectrum transceiver with carrier recovery employing complex spreading sequences,” Proceedings: IEEE Mediterranean Electrotechnical Conference, Málaga, pp. 1227-1230, 16-19 May 2006.

[3] M. K. Kazimierczuk: RF Power Amplifiers, John Wiley and Sons, Ltd., UK, first edition, 2008.

[4] M. Božani and S. Sinha, “Software Aided Design of a CMOS Based Power Amplifier Deploying a Passive Inductor,” SAIEE Africa Research Journal, Vol. 99, No. 1, pp. 18-24, 2008.

[5] N. A. Sokal and A. D. Sokal, “Class E-A New Class of High-Efficiency Tuned Single-Ended Switching Power Amplifiers,” IEEE Journal of Solid-State Circuits, Vol. 10, No. 3, pp. 168-176, June 1975.

[6] P. Colantonio, F. Giannini, G. Leuzzi and E. Limiti, “On the Class-F Power Amplifier Design,” International Journal of RF and Microwave Computer-Aided Engineering, Vol. 9, No. 2, pp. 129-149, 1999.

[7] S. Gao, “High-Efficiency Class F RF/Microwave Power Amplifiers,” IEEE Microwave Magazine, Vol. 7, No. 1, pp. 40-48, Jan. 2006.

[8] F. H. Raab, “Maximum Efficiency and Output of Class-F Power Amplifiers,” IEEE Transactions on Microwave Theory and Techniques, Vol. 49, No. 6, pp. 1162-1166, June 2001.

[9] S. H. L. Tu and C. Toumazou, “Effect of the Loaded Quality Factor on Power Efficiency for CMOS Class-E RF Tuned Power Amplifiers,” IEEE Transactions on Circuits and Systems—I: Fundamental Theory and Applications, Vol. 46, No. 5, pp. 628-634, May 1999.

[10] S. S. Mohan, M. del Mar Hershenson, S. P. Boyd and T. H. Lee, “Simple Accurate Expressions for Planar Spiral Inductances,” IEEE Journal of Solid-State Circuits, Vol. 34, No.10, pp. 1419-1424, Oct. 1999.

[11] A. M. Niknejad and R. G. Meyer: Design, Simulation and Application of Inductors and Transformers for Si RF ICs, Kluwer Academic Publishers, USA, 2nd edition, 2002.

[12] C. P. Yue and S. S. Wong, “Physical Modeling of Spiral Inductors on Silicon,” IEEE Transactions on Electron Devices, Vol. 47, No. 3, pp. 560-568, 2000.

[13] X. Huo, P. C. H. Chan, K. J. Chen and H. C. Luong, “A Physical Model for On-Chip Spiral Inductors with Accurate Substrate Modeling,” IEEE Transactions on Electron Devices, Vol. 53, No. 12, pp. 2942-2949, Nov. 2006.

[12] C. Y. Lee, T. S. Chen, J. D. S. Deng and C. H. Kao, “A Simple Systematic Spiral Inductor Design with Perfected Q Improvement for CMOS RFIC Application,” Transactions on Microwave Theory and Techniques, Vol. 53, No. 2, pp. 523-528, Feb. 2005.

[14] Anon., Design Data Translator's Reference, Cadence Design Systems, USA, 2006.


Notes

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