itea2 - 09013 international workshop on challenges in methodology, representation, and tooling for...

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ITEA2 - 09013

International Workshop on Challenges in Methodology, Representation, and Tooling for Automotive Embedded Systems, Berlin 2012

Target Mapping in a Multi-core Environment

Results and Plans

Erik Kamsties, Burkhard Igel

FH Dortmund

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ITEA2 - 09013

Overview

•Background AMALTHEA

•What is Target Mapping?

•Details and Results– Multi-core CPU Target Platform– Damos and SCT Modeling– Projection of models– AUTOSAR

•Tools

•Case Study

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AMALTHEA Overview on Work Packages

Continuous design flowand methodology

WP 1

Continuous tool chain platformWP 4

Dem

ons

trat

or

WP 5

Project managementWP 7

Target mapping

WP 3

Definition of DSLs

WP 2

Dis

sem

inat

ion

an

d e

xplo

itatio

n

WP 6

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ITEA2 - 09013

What is Target Mapping?

Definition: Target mapping is the AUTOSAR-conformant projection of models of an automotive software system on a multi-core target platform.

WP3 roadmap:

1.Select and utilize a multi-core platform for automotive systems

2.Select and extend a modeling technique and a respective tool for describing parallel systems

3.Develop a design flow to project models (2) to a target platform (1)

4.AUTOSAR conformance shall be ensured in the design flow (3).

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ITEA2 - 09013

Multi-core CPU Target Platform• Requirements

– Number and type of cores (>= 2 cores, symmetric cores)

– Automotive I/Os: CAN, Flexray

– Open/free tool chain

• Popular multi-core CPUs for automotive embedded systems– Freescale MPC 55xx,

56xx series

– Infineon TriCore, AURIX (multi-core TriCore)

– Renesas ?

• Within AMALTHEA:– Adopting code

generator to chosenplatform

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Damos Modeling

• Damos – part of Yakindu (open source, Eclipse-based tool chain, developed by itemis)– is a data flow-oriented modeling environment – includes a block diagram editor, simulator and C code generator

• Within AMALTHEA– Partitioning data flow models, mapping to runnables/tasks– Generating AUTOSAR compatible C code (.arx files)

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SCT Modeling

• SCT– part of Yakindu (open source, Eclipse-based tool chain, developed by itemis)– based on finite automata– includes hierarchical state chart editor (based on Harel statecharts), simulator and

C code generator

• Within AMALTHEA– Partitioning, mapping to runnables/tasks– Generating AUTOSAR compatible C code (.arx files)

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Projection of Models to the Platform

SPEM SPEM Diagram

Partitioning

Communication

Agglomeration

Mapping

Software Components

Tasks

Dependencies

GroupedTasks

MappedTasks

CodeGeneration

Component Code

Damos

SCT

HardwareModel

Optimization

TA Toolset

Yakindu CodeGen

itemis: AUTOSAR-conformant extension

of Damos

FhDO: Metamodel, methods, and tool

FhDO: Partitioning of Damos models

BHTC: Prototypical implementation and evaluation of target hardware platform

clab: AUTOSAR, scheduling, tracing

TA/HSR: Refinement of agglomeration

TA/HSR: Generating a mapping

itemis: extension of code generator

t

ifak: scheduling, tracing

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AUTOSAR

• Within AMALTHEA, the overall goal is to support an AUTOSAR conformant model-based software development

• Derived requirements– A model (e.g. Damos) describes the behavior of a software component

(architectural modeling in not considered in WP3)– The code generator shall produce the respective AUTOSAR files (this implies that

the meta model of the modeling technique is aligned to AUTOSAR) – AUTOSAR-OS has to be used

• Regarding target mapping, the current version 4.0 R3– permits only local instead of global scheduling– the schedulers of the different cores are required to be independent of each other– atomic software components (SWCs) can be mapped to cores only 1:1– if memory protection boundary is used for a set of SWCs, all these SWCs must

be mapped to the same core

• Bottom line: current version 4.0 R3 is overly restrictive regarding multi-core aspects extensions are required

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Tools

• Yakindu Damos and SCT– Extending embedded code generators towards multi-core– The Damos code generator was adapted to the Arduino platform and a respective

hardware model was created in order to collect experiences about generating hardware-dependent code.

• Timing Architects Simulator/Optimizer– Early evaluation of performance attributes (e.g., real-time requirements) based on

models of the software and the selected HW platform– For the mapping of tasks to cores a solution based on genetic algorithms is

extended towards considering communication based influences and scheduling effects.

• Tools for Creating Modeling Tools (DSLs)– Xtext/Xtend are employed

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Case Studies

• Industrial case study 1: HVAC on the BHTC “Rapid Control Prototyping Box”– Utilizing MPC5668G evaluation board, redesign of current RCP box – Adaptation of Matlab tool chain (providing hardware abstraction layer, adaptation

of Matlab/Simulink code generator templates) – Comparison of Matlab baseline and new open source tool chain

• Case Study 2: Multi-OS on a multi-core system

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Links to MAENAD, SAFE, TIMMO-2-USE

• MAENAD:– It is commonly accepted that parallelism which is introduced by multi-core

processors should be addressed on higher level of design. Abstractions in modeling are sought which represent parallelism in systems.

• SAFE– Multi-core processors are

• beneficial, because they easily allow for redundancy (e.g., MPC 56xx lock-step mode)

• introduce a number of issues, e.g. shared resources may lead to timing problems

• TIMMO-2-USE– Timing information is required for the latter steps of the target mapping process

(e.g., timing properties of the different tasks)

itea2 - 09013 international workshop on challenges in methodology, representation, and tooling for...

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